Lesson 5. The input-output system
Computers Structure and
Organization
Graduated in Computer Sciences
Graduated in Computers Engineering
Automatic Department
Lesson 5:
The input-output system
Slide: 2 / 50
Computers Structure and Organization.
Graduate in Computer Sciences / Graduate in Computer Engineering Automatic Department
Contents
Input-output system characteristics
Input-output management
– Device selection
– Synchronization
– Control signal handling
Buses
– Types of buses
– Bus access
– Bus arbitration
– Standards
External memory
Input-output and operating system
Apple Macintosh 7200
Bibliography
Lesson 5:
The input-output system
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Computers Structure and Organization.
Graduate in Computer Sciences / Graduate in Computer Engineering Automatic Department
Contents
Input-output system characteristics
Input-output management
– Device selection
– Synchronization
– Control signal handling
Buses
– Types of buses
– Bus access
– Bus arbitration
– Standards
External memory
Input-output and operating system
Apple Macintosh 7200
Bibliography
Lesson 5:
The input-output system
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I/O characteristics (I)
The aim of this system is to communicate computer with world.
Devices are used in such communication.
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I/O characteristics (II)
Devices’ classification:
– Input devices: keyboard, mouse, scanner, electrical and mechanical magnitude sensors, etc.
– Output devices: screen, printer, etc.
– Input and output devices: hard disks, flash drives, pendrives, etc.
Part of the device
Description Purpose
Controller Handles communication between device and CPU
Data tranfer Transfer protocol
Device Made of several different compositions: mechanical, electrical, etc.
Outside relationship
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The input-output system
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I / O communication handling
To be taken into account:
– Device selection: identify device among other available
devices by using data and control registers addressing.
– CPU-device synchronization: avoid different speeds
problems between CPU and devices.
– Control signals handling: what control signals will be
needed in different synchronization methods and device
selection policies.
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Device selection (I)
Registers / port are used to select a device among several ones
CPU must do:
– Specify device address: input-output port indetification among
several different ports.
– Specify if it’s a reading or wrint operation.
– Send data: for writing operations only
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Device selection (and II)
Port addresses specification
– Isolated input-output: addressing maps are different for memory and input-output operations. Different instructions will be required. E.g., i80x86 IN, OUT and MOV instructions.
– Memory mapped input-output: same instructions are used for memory and input-output operations because the same addresses space is used.
Sent / Received information (writings / readings):
– Data
– Order to the devices: setting up devices, operation mode if several allowed, device reset, etc.
– Status information: device availabilty, error alert, etc.
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CPU-device synchronization (I)
To fit different working speeds.
– Programmed input-output: CPU handles communication with devices by executing a program.
– Interrupts driven input-output: devices alert CPU when they’re ready
– Direct Memory Access input-output: devices are able of working directly with memory position. Devices transfer blocks from memory to memory, memory to device, device to memory or device to device.
– Input-output processors: a slave CPU is used to handle with input-output operations
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The input-output system
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CPU-device synchronization (II) Programmed input-output (I)
CPU handles communication with devices by executing a program
– CPU is dedicated to the full input-output operation hanling. Most of the time by testing device avaliability, what is named pooling.
– Hardware is simple and program for one only device too.
– Program increases in complexity when it’s needed to handle several devices.
– Device priority is fixed because depends on the program
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CPU-device synchronization (III) Programmed input-output (and II)
Available
data?
Other tasks
yes
no finish?
yes
no
Reading (input)
Data reg. reading
Status reg. reading
Available for
Accepting data?
Other tasks
yes
no finish?
yes
no
Writing (outpu)
Data reg. writing
Status reg. reading
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CPU-device synchronization (IV) Interrupts driven Input-output (I)
Devices interrupt CPU when ready. Basic operation:
– CPU issues read command
– I/O module gets data from peripheral whilst CPU does other work
– I/O module interrupts CPU
– CPU requests data
– I/O module transfers data
What to take into account when designing a interrupts driven I/O:
– How to request an interrupt
– How to acknowledge an interrupt
– How to identify a device
– How to handle device priorities when some of them request at once
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CPU-device synchronization (V) Interrupts driven Input-output (II)
If there are several devices, we need to deal with device priorities
To be taken into account:
– How to attach devices to CPU
– How to deal with multiple interrupts
– How do you identify the module issuing the interrupt
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CPU-device synchronization (VI) Interrupts driven Input-output (III)
Software pool
– There is only one interrupt line.
– CPU ask each module in turn.
– Very slow.
– Device priority is set by asking each device in different order.
(0, 1, 1, 1, 2, 3, n, 0, 1, 1, 1).
CPU
INT
PER. 0 PER. 1 PER. n
? ? ?
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CPU-device synchronization (VII) Interrupts driven Input-output (IV)
CPU with different interrupt lines
– Each device is attached to one different line
– Interrupt service address routine is fixed but different in each line
– CPU set priority
– Limits the number of devices to be attached
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CPU-device synchronization (VIII) Interrupts driven Input-output (V)
CPU with only one requesting and accepting line (I)
– CPU has and INT line in which devices ask for attention.
– CPU has and INTA line to send the acknowledge to device
– Module responsible places vector on bus
– CPU uses vector to identify handler routine
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CPU-device synchronization (IX) Interrupts driven Input-output (VI)
CPU with only one requesting and accepting line (II)
Daisy-chain
– Interrupt Acknowledge sent down a chain
– Module responsible places vector on bus
– CPU uses vector to identify handler routine
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CPU-device synchronization (X) Interrupts driven Input-output (VII)
CPU with only one requesting and accepting line (III)
Vectored interrupts
– INT line is used by all devices to request CPU attention.
– CPU accept highest priority device by sending setting INTA
line. The selected devices send to data bus the address of the
service routine.
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The input-output system
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CPU-device synchronization (XI) Interrupts driven Input-output (VIII)
CPU with only one requesting and accepting line (IV)
Programmable Interrupt Controller (PIC)
– A PIC allow several devices connection to the same INT line
– Flexible priority handling
– Allow to mask several lines
– It’s possible to have several slave PICs to expand interrupt lines
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The input-output system
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CPU-device synchronization (XII) Interrupts driven Input-output (and IX)
PIC 8259
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The input-output system
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CPU-device synchronization (XIII) Direct Access Memory (I)
Additional Module (hardware) on bus
DMA controller takes over from CPU for I/O
CPU tells DMA controller:- – Read/Write
– Device address
– Starting address of memory block for data
– Amount of data to be transferred
CPU carries on with other work
DMA controller deals with transfer
DMA controller sends interrupt when finished
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Architecture. 8th Edition Slides
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CPU-device synchronization (XIV) Direct Access Memory (II)
Multi-gate memories
Several data transfer are allowed by using different data and addresses gates / ports / registers.
Cycle Stealing
DMA controller takes over bus for a cycle
Transfer of one word of data
Not an interrupt
CPU does not switch context
CPU suspended just before it accesses bus. I.e. before an operand or data fetch or a data write
Slows down CPU but not as much as CPU doing transfer
MEMORY
D1 M1 D2 M2 D3 M3
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CPU-device synchronization (XV) Direct Access Memory (and III)
Controlador DMA 8237
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CPU-device synchronization (XVI) Input-Output processors
Use another CPU to take over I/O operations.
CPU instructs I/O controller to do transfer
I/O controller does entire transfer
I/O processor can handle I/O operation by using programmed I/O, interrupt driven I/O or DMA I/O.
It’s a more powerful and complex I/O system
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The input-output system
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Control signals handling
I/O control signals o be taken into account when designing different I/O systems:
– IO / M: to indicate if it’s a memory or I/O address
– RD: reading request
– WR: writing request
– INTR: interrupt requested by device controller
– INTA: CPU interrupt acknowledge
– HOLD: DMA request access by device controller
– HOLDA: CPU DMA acknowledge
Lesson 5. The input-output system
Computers Structure and
Organization
Graduated in Computer Sciences
Graduated in Computers Engineering
Automatic Department
Lesson 5:
The input-output system
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Computers Structure and Organization.
Graduate in Computer Sciences / Graduate in Computer Engineering Automatic Department
Contents
Input-output system characteristics
Input-output management
– Device selection
– Synchronization
– Control signal handling
Buses
– Types of buses
– Bus access
– Bus arbitration
– Standards
External memory
Input-output and operating system
Apple Macintosh 7200
Bibliography
Lesson 5:
The input-output system
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Computers Structure and Organization.
Graduate in Computer Sciences / Graduate in Computer Engineering Automatic Department
Contents
Input-output system characteristics
Input-output management
– Device selection
– Synchronization
– Control signal handling
Buses
– Types of buses
– Bus access
– Bus arbitration
– Standards
External memory
Input-output and operating system
Apple Macintosh 7200
Bibliography
Lesson 5:
The input-output system
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Computers Structure and Organization.
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Buses (I)
Bus. Is a communication channel between different subsystems
Buses are composed by:
– Control signals
– Data lines
Advantages:
– Versatility, once system is defined new devices can be added.
– Low cost, wires can be shared in different ways.
Drawbacks:
– Bottle-neck
– Difficult design
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The input-output system
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Buses (II) Types of buses
Buses classification
– Memory-processor bus. Adapted to system memory to improve bandwidth, they’re fast and short
– Backplane bus. Build on the chasis CPU, Memory and devices are connected
– Input-output bus. Allow to connect different bandwidth devices. They can be very long.
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Buses (V) Operation mode
Synchronous and assynchronous buses.
Synchronous buses. Clock is one of their control signals. They also have a communication protocol by using clock signal.
Asynchronous buses. A handshacking protocol is used to handl communicaiton because no clock control signal is present.
Synchronous buses are faster than asynchronous ones.
Asynchronous buses are more flexible than synchronous ones.
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Buses (VI) Bus access
Bus control access avoids conflicts in accessing to the bus by several different elements.
Bus is reserved by on device
Access mechanism: one or more bus masters and several bus slaves
– Bus master. Controls bus access. It’s able to start and control all bus access requests.
– Bus slave. Answer to masters requests. It never stars a request.
Processor is always a bus master and memory a slave one
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Buses (VII) Bus arbitration
If several masters are present it will be needed to decide which one of them is allowed to access to the bus
All master must be served.
Arbitration methods:
– Daisy-chain. One only concession line is attached to all masters
– Centralized arbitration. A central system chooses a devices and promote it to master
– Auto-selection distributed arbitration. All devices show their priority. Highest priority device is become master
– Collision detected distributed arbitration. Once a collision happened a distributed approach is used to become one master from devices that caused the collision
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Buses (VIII) Timming
Timming reffers to how addressing and data phases are handled
Types of timming:
– Full cycle. Addressing and data phases are carried without bus releasing. Simple design but small broadband
– Bus realeasing. Bus is not reserved during addressing and data phases. Several master are allowed to access to the bus. Big broadband but complex design. Bus slaves may be able to request the bus.
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Buses (IX) Bandwidth
Protocol and timming set bus broadband. Other involved parameters are:
– Data bus width.
– Splited or multiplexed data and addresses lines.
– Burst transfers
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Buses (X) Operation types on buses
– Simple reading or writing cycle
– Multiple reading or writing cycle
– Interrupt cycle
– Direct Memory Access Cycle
– Reading after writing cycle
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Buses (XI) I/O Buses. Performance and cost
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Buses (and XII) Bus standards
Standards are because they easy buses and devices design
Types of standards:
– Facts standard. The use is very common. E.g. PC-AT, MNP modem.
– Industry standard. Several companies reach and agreement on bus specification. E.g. SCSI, Ethernet, Bluetooth
– Committee standard. Authorized organization to create new standards. E.g. PCI
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External memory (I)
Magnetic Disk
Optical
CD-ROM
CD-Recordable (CD-R)
CD-R/W
DVD
Blueray
Magnetic Tape
Flash Drive
Solid State Drive (SSD)
RAID
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External memory (II) Magnetic disk (I)
Disk substrate coated with magnetizable material (iron oxide)
Substrate used to be aluminium
Nowadays glass
– Improved surface uniformity
– Reduction in surface defects
– Lower flight heights
– Better stiffness
– Better shock/damage resistance
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External memory (III) Magnetic disk (II)
Writing and reading via conductive coil called a head
May be a single read/write head or separate ones
During read/write, head is stationary, platter rotates
Images from William Stallings. Computer Organization and
Architecture. 8th Edition Slides
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Must be able to identify start of track and sector
Format disk
– Additional information not available to user
– Marks tracks and sectors
Images from William Stallings. Computer Organization and
Architecture. 8th Edition Slides
External memory (IV) Magnetic disk (and III)
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External memory (V) CD-ROM
• Originally for audio. 650Mbytes giving over 70 minutes audio
• Polycarbonate coated with highly reflective coat, usually
aluminium
• Data stored as pits
• Read by reflecting laser
• Constant packing density
• Constant linear velocity
• Track (spiral) is 5.27km long
Image from William Stallings. Computer Organization and
Architecture. 8th Edition Slides
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External memory (VI) DVD
• Multi-layer
• Very high capacity (4.7G per layer)
• Full length movie on single disk
—Using MPEG compression
• Finally standardized
• Movies carry regional coding
• Players only play correct region films
• Can be “fixed”
Image from William Stallings. Computer Organization and
Architecture. 8th Edition Slides
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External memory (VII) Blue-Ray Disk
Data layer closer to laser
Tighter focus, less distortion, smaller pits
25GB on single layer
Available:
Read only (BD-ROM),
Recordable once (BR-R)
Re-recordable (BR-RE)
Image from William Stallings. Computer Organization and
Architecture. 8th Edition Slides
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External memory (VIII) Magnetic tape
Serial access
Slow
Very cheap
Backup and archive
Linear Tape-Open (LTO) Tape Drives
� Developed late 1990s
� Open source alternative to proprietary tape systems
Image from Pedro de Miguel Anasagasti. Fundamentos de
los Computadores. Ed. Thompson
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External memory (IX) Flash drive(I)
• USB flash drive is a data storage device that include flash memory with
an integrated USB interface
• There are typically five parts to a flash drive:
• Standard-A USB plug – provides a physical interface to the host
computer.
• USB mass storage controller – a small microcontroller with a small
amount of on-chip ROM and RAM.
• NAND flashmemory chip(s) – stores data.
• Crystal oscillator produces the device's main 12 MHz clock
signal and controls the device's data output.
•Cover typically made of plastic or metal, protecting the electronics
against mechanical stress and even possible short circuits.
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External memory (X) Flash drive(and II)
•File system: FAT32 and exFAT
•Even distribution.Some file systems are designed to distribute usage
over an entire memory device without concentrating usage on any part to
prolong the life of simple flash memory devices.
•Hard disk drive. Sectors are 512 bytes long, for compatibility with hard
disk drives, and the first sector can contain a master boot record and a
partition table. Therefore, USB flash units can be partitioned just like hard
disk drives.
•Longevity. The memory in flash drives is commonly engineered with
multi-level cell (MLC) based memory that is good for around 3,000-5,000
program-erase cycles but some flash drives have single-level cell (SLC)
based memory that is good for around 100,000 writes. There is virtually no
limit to the number of reads from such flash memory.
•The USB connector hardware is specified to withstand only around 1,500
insert-removal cycles
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External memory (XI) Solid State Drive SSD (I)
A solid-state drive (SSD is a solid-state storage device that uses integrated circuits as memory to store data. SSD technology primarily uses electronic interfaces compatible with traditional block input/output (I/O) hard disk drives (HDDs), which permit simple replacements.
New I/O interfaces like SATA Express and M.2 designed to address specific requirements of the SSD technology.
SSDs have no moving mechanical components. Compared with electromechanical disks, SSDs are typically more resistant to physical shock, run silently, and have lower access time and lower latency.
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External memory (XII) Solid State Drive SSD (II)
Architecture and function
The key components of an SSD are the controller and the memory to store the data. The primary memory component in an SSD was traditionally DRAM volatile memory, but since 2009 it is more commonly NAND flash non-volatile memory.
Controller
Every SSD includes a controller that incorporates the electronics that bridge the NAND memory components to the host computer.
• Bad block mapping
• Read and write caching
• Encryption
• Error detection and correction via Error-correcting code (ECC)
• Garbage collection
• Read scrubbing and read disturb management
• Wear leveling
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External memory (XIII) Solid State Drive SSD (and III)
File Systems
Typically the same file systems used on hard disk drives can also be used on solid state disks.
The file system must support the TRIM command which helps the SSD to recycle discarded data.
There is no need for the file system to take care of wear leveling or other flash memory characteristics, as they are handled internally by the SSD.
Operating systems must also align partitions correctly to avoid excessive read-modify-write cycles. A typical practice for personal computers is to have each partition aligned to start at a 1 MB (= 1,048,576 bytes) mark, which covers all common SSD page and block size scenarios, as it is divisible by 1 MB, 512 KB, 128 KB, 4 KB, and 512 bytes.
Modern operating system installation software and disk tools handle this automatically.
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External memory (XIV) RAID sytems (I)
RAID stands for Redundant Array of Inexpensive or Redundant Array of Independent Disks. RAID several HDDs are made into one logical disk.
Advantages:
• To make the loss of data happen less often. This is done by having several copies of the data.
• To get more storage space by having many smaller disks.
• To get more flexibility (Disks can be changed or added while the system keeps running)
• To get the data more quickly.
Drawbacks:
• In some RAIDs can protect against data being lost because a disks failed. They don’t protect against the data being deleted or overwritten.
• In some RAID can tolerate that one or a number of disks fail. After the failed disks have been replaced, the data needs to be reconstructed. Depending on the configuration and the size of the disks, this reconstruction can take a long time.
• Certain kinds of errors will make it impossible to read the data
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External memory (XV) RAID (II)
• 6 levels in common use
• Not a hierarchy
• Set of physical disks viewed as single logical drive by O/S
• Data distributed across physical drives
• Can use redundant capacity to store parity information
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External memory (XVI) RAID sytems (III)
Basics and most simple RAID levels
• RAID 0 "striping"
• RAID 1 "mirroring"
• RAID 5 "striping with distributed parity" is what is
probably used most of the time. At least three hard
disks are needed to build a RAID 5 storage array. A
RAID 5 with a failed disk will continue to work. It is
in degraded mode. A degraded RAID 5 can be very
slow. For this reason an additional disk is often added.
This is called hot spare disk. If a disk fails, the data
can be directly rebuilt onto the extra disk.
Images from https://www.wikiwand.com/simple/RAID
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External memory (XVII) RAID sytems (IV)
RAID levels used less
• RAID 2. This was used with very large computers. Special
expensive disks and a special controller are needed to use
RAID 2. The data is distributed at bit-level. It is the only
RAID level that can repair errors, the other RAID levels can
only detect them. RAID 2 needs at least 6 disks to work
• RAID 3 "striping with dedicated parity" It is similar to
RAID Level 0. An additional disk is added to store parity
information. RAID 3 is done with at least 3 disks.
• RAID 4 "striping with dedicated parity" This is very
similar to RAID 3, except that the parity information is
calculated over larger blocks, and not single bytes. At least
three disks are needed for a RAID 4 array.
• RAID 6. was not an original RAID level. It adds an
additional parity block to a RAID 5 array. It needs at least
four disks. Images from https://www.wikiwand.com/simple/RAID and https://edgarfrpr.blogspot.com.es/2010/10/tecnologias-raid.html
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External memory (and XVIII) RAID sytems (and V)
Joining RAID levels (Nested levels)
With RAID different disks can be put together to get a
logical disk.The user will only see the logical disk
• RAID 0+1: Two or more RAID 0 arrays are combined
to a RAID 1 array; This is called a Mirror of stripes
• RAID 1+0: Same as RAID 0+1, but RAID levels
reversed; Stripe of Mirrors. This makes disk failure rarer
than RAID 0+1 above.
• RAID 5+0: Stripe several RAID 5's with a RAID 0. One
disk of each RAID 5 can fail, but makes that RAID 5 the
single point of failure; if another disk of that array fails,
all the data of the array will be lost.
• RAID 5+1: Mirror a set of RAID 5: In a situations
where the RAID is made of six disks, any three can fail
(without data being lost).
•RAID 6+0: Stripe several RAID 6 arrays over a RAID 0;
Two disks of each RAID 6 can fail without data loss. Images from https://www.wikiwand.com/simple/RAID and
http://www.icc-usa.com/raid-calculator.html
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Computers Structure and Organization.
Graduate in Computer Sciences / Graduate in Computer Engineering Automatic Department
I/O and Operating System (I)
I / O operations are compiled to systems calls when using high level languages.
Operating system manage devices to match memory addresses and device names
– Advantage: portable programs
– Drawback: a bit slow
Real time systems manage directly I / O operations
Lesson 5:
The input-output system
Slide: 58 / 50
Computers Structure and Organization.
Graduate in Computer Sciences / Graduate in Computer Engineering Automatic Department
I/O and Operating System (II)
Operating system takes into account:
– I/O system is shared for all computer programs
– I/O operations must only works on user data and addresses
– I/O systems often use interrupt driven that must be handled by the operating system
– I/O system calls simplify devices structure
Operating system must communicate with devices
– By sending order to devices: reading, writing, hard disk heads positioning, etc.
– By receiving notifications from devices: operation is completed, operation error, etc.
– By transferring data among memory and I/O devices.
Lesson 5:
The input-output system
Slide: 59 / 50
Computers Structure and Organization.
Graduate in Computer Sciences / Graduate in Computer Engineering Automatic Department
I/O and Operating System (and III)
UNIX system calls have been bold highlited in following C program:
#define BUFSIZE 512
Void copy (from, to)
Char * from, *to;
{
int fromfd, tofd, nread;
char buf[BUFSIEZE];
if ((fromfd = open( from, 0) == -1) syserr(from);
if ((tofd = creat (to, 0666)) == -1) syserr(to);
while ((nread = read(fromfd, buf, sizeof(buf))) > 0)
if (write(tofd, bud, nread) !=nread) syserr (“write”);
if (nread == -1) syserr (“read”);
if (close(fromfd) == -1 || close (tofd) == -1) syserr (“close”);
}
Lesson 5:
The input-output system
Slide: 60 / 50
Computers Structure and Organization.
Graduate in Computer Sciences / Graduate in Computer Engineering Automatic Department
Apple Macintosh 7200
El PCI se usa como bus backplane y los dispositivos de menor rendimiento emplean un SCSI
Lesson 5:
The input-output system
Slide: 61 / 50
Computers Structure and Organization.
Graduate in Computer Sciences / Graduate in Computer Engineering Automatic Department
Bibliography
Estructura y diseño de computadores
David A. Patterson y John L. Hennessy. Reverté, 2000
Capítulo 8
Arquitectura de computadores. Un enfoque cuantitativo
John L. Hennessy y David A. Patterson. Mc Graw Hill, 3ª ed, 2002
Capítulo 9
Arquitectura de computadores
José A. de Frutos y Rafael Rico. Servicio de Publicaciones de la Universidad de Alcalá, 1995
Capítulo 6
Fundamentos de computadores
Pedro de Miguel Anasagasti. Paraninfo, 1999
Capítulo 8