FD-SOI  Symposium|  Ali  Erdengiz – Olivier   Thomas|  April  13,  2016

FD-SOI  POWER  OPTIMIZATION FLOW

Everything you wanted to  know  about  back  bisaing but  were afraid to  ask

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• Introduction  to  Leti

• The  Challenges  to  FD-SOI  adoption

• Leti’s FD-SOI  Power  Management  Strategy

• Conclusions

AGENDA

©  2016  CEA FD-SOI  Symposium  |  April  13,  2016

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CEA  TOP  2015  R&D INSTITUTION

Leti is the MicroelectronicsR&D Branch of CEA

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Micro  &  Nano  Electronics

7,000m2 Clean  Room€1B  of  Investment

Characterization Labs2,500m2 - 80  People€30M  of  Investment

IC  Design100+  People

Embedded  Systems200+  People

LETI

• Some of  our Activities• Semiconductor Process Development (SOI,  FDSOI,  GaN,  RRAM,  etc.)• 2.5D  /  3D  Technology Development• Silicon Photonics• IC  Design  (RF,  Mixed  Signal,  Digital)

• Main  Application  Areas• IoT,  ADAS,  Sensor Fusion,  Ultra  Low Power  Design,  High  Performance  

Computing©  2016  CEA FD-SOI  Symposium  |  April  13,  2016

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SILICON IMPULSE

• Leti launched its Silicon Impulse  platform in  2015  to  grow the  FD-SOI  ecosystem and  enable the  industry by  lowering the  barriers to  access

• Silicon Impulse  relies  on  a  growing network  of  leading partnersproviding strong support  to  the  FD-SOI  ecosystem

• Silicon Impulse  offers:• Leadership  in  Ultra  Low Power  design• Key  functional blocks  for  power  and  performance  optimization• Advanced  FD-SOI  design  services• Access  to  MPW  shuttles• Low volume  production  through its network  of  partners

©  2016  CEA FD-SOI  Symposium  |  April  13,  2016

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• Availability of  multiple  sources• The  momentum is on  with ST,  Samsung  and  GlobalFoundries

• IP  availability• Synopsys,  Cadence,  Invecas,  Leti…

• Design  Flows• The  typical design  flow  for  FD-SOI  design  is very similar to  bulk

• However…

• A  direct  copy  &  paste approach will not  provide the  optimum  result• Early adopters,  including Leti,  have  developed their own internal flows to  

leverage the  unique  features of  FD-SOI  to  maximize device power  and  performance

• There  is need to  streamline and  automate  these features to  the  benefit of  the  user  community at  large

CHALLENGES  TO  FD-SOI  ADOPTION  

©  2016  CEA FD-SOI  Symposium  |  April  13,  2016

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• Simulation  and/or  characterization  data:

• The  optimal  control  strategy  will  be  determined  based  on  the  mix  of  static  and  dynamic  operational  ranges  and  through  the  correct  combination  of  static  user  controlled  parameters.

DESIGN  TOOL  INPUTS

©  2016  CEA FD-SOI  Symposium  |  April  13,  2016

Inputs

Static  Parameters

Substrate RVT,  LVT

Poly  Bias 0nm,  4nm,  10nm,  16nmProcess  Corner SS,  TT,  FF

Dynamic  Parameters  

User  controlled

Vdd [0.6V,  1.4V]Vbb in  LVT [0V,  1.5V]Vbb in  RVT [−1.5V,  0V]

Operating  Conditions

Temp [−40°C,  125°C]Toggle  Rate [0.1%,  50%]

MeasurementsFmaxIswitchIleak

Additional  parameters  bring  inadditional  degrees  of  freedom

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POWER  MANAGEMENT  STRATEGIES

©  2016  CEA FD-SOI  Symposium  |  April  13,  2016

Dynamic  Power  Dominates Static Power  Dominates  Dynamic  ≅ Static

DBBVS DVSDBB DBB DBBDBB DVS

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STRATEGY  SELECTION

Process TTVbb =  -‐1.5V  to  0VVdd =  0.6V  to  1.4V

DVSDBB  for  extreme  speed-‐up

DBB  for  low  speedDVS  for  high  speed

DBBVS

©  2016  CEA FD-SOI  Symposium  |  April  13,  2016

Static  PwrDynamic  Pwr

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DYNAMIC  POWER  MANAGEMENT  AND  PROCESS  VARIABILITY  COMPENSATION  IP

©  2016  CEA FD-SOI  Symposium  |  April  13,  2016

Core

V  regulator

F  generatorCtrl.

Power  Domain

Data  fusionAdjustment

BB  generator

FMAX monitor

T° monitor

PVT  monitor

UWVR  foundation  IPs  (Standard  cell,  SRAM)

VDD  generator

Back  bias  generator

Frequency  generator

ActuatorsCTRL Sensors

Control  theory  &  fast  adjustment

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FINE  GRAIN  STRATEGY PER  CORE

©  2016  CEA FD-SOI  Symposium  |  April  13,  2016

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UWVR  32b DSP  IN  28NM  FD-SOI

KEY FEATURESo UWVR  standard  cells  

o UWVR  SRAM

o Pulsed  latches  FF  

o -2V  to  2V  FBB/RBB  IOs  

o PVT  sensors

o Timing  slack  sensors

o Fast  loop  adjustment

x100

“28nm  FD-SOI  and  full  voltage  scaling  break  low-power  limits  for  DSPs”IEEE  Times  Europe

ISSCC’14476MHz

2GHz

High-Performance,  Low  power,  Dynamic  Flexibility

©  2016  CEA FD-SOI  Symposium  |  April  13,  2016

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ADVANCED  POWER  MANAGEMENT  FUNCTIONS   in 28nm*

©  2016  CEA FD-SOI  Symposium  |  April  13,  2016

These  functions  are  the  building  blocks  for  enabling  quantum  improvement  in  power  consumption

Application Function Description Type

Digital  Power  Management

FLL Programmable  clock  generator   (15  MHz  -‐ 2.3  GHz) HardPVT  Sensor Continuois   monitoring   of  PVT  variability HardTiming  Fault  

SensorCritical  path   timing  sensor Hard

Timing  Fault  Ring Timing  variability  monitor HardVDD  Hopping  Ctrlr Smooth  voltage  transition  control   SoftCVP  Controller Clock  variability  power  controller Hard

Analog  Power  Management

Charge  Pump Fine  grain  BB  generation HardULP  Oscillator 40KHz  ULP  oscillator  with  temperature  compensation Hard

ULP  RTC ULP  RTC  module   for  sensor  node HardBandgap 0.9V  VREF  generation Hard

ULP  Regulator 0.9V  output   voltage HardULP  ADC HardULP  Radio Wake-‐up  radio   receiver Hard

Low  Power  Memory

LV  SRAM 0.5V  32KB  SRAM Hard

Hybrid  Memory Mixed  volatile/non-‐volatile   (CBRAM/OXRAM)  (Power  off  context  saving)

Hard

NV  Register  File Context  saving  for  MCU  (Flip-‐Flop  system  based  on  CBRAM/OXRAM)

Hard

*  22  FDX  versions  in  planning

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SIMPLIFIED  FLOW

2)  Circuit  extraction

3)  Power  behavior  

Activity,  multi-VT,  cell   types,  …

1)  Report

Technology

4)  Choice  of  management  technique

For  power  behavior  analysis,  consider  static  parameters  (cells,  multi-Vt,…)

VDD  &  VBB  exploration  and  identification  of  optimal  config.

Consider  dynamic  conditions  

(T°,  Activity,…)

©  2016  CEA FD-SOI  Symposium  |  April  13,  2016

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• In  order to  reap the  full  benefits of  FD-SOI  a  straight  porting will not  suffice

• Leti has  developed and  tested advanced techniques  and  building  blocks  to  optimize the  power  and  performance  of  FD-SOI  designs

• To  make the  transition  seamless to  the  design  community further cooperation between tool vendors,  library and  IP  developers are  required

• Leti is ready to  engage  with EDA  vendors as  well as  IP  providers  to  make it happen

CONCLUSIONS

©  2016  CEA FD-SOI  Symposium  |  April  13,  2016

Some  assembly  required…

Leti,   technology research instituteCommissariat  à   l’énergie   atomique   et  aux  énergies   alternativesMinatec  Campus   | 17  rue  des  Martyrs  | 38054   Grenoble   Cedex  |  Francewww.leti.fr

TECHNICAL   INQUIRIES:olivier.thomas@cea.fr  |  www.leti.fr+33  (0)4  38  78  29  54  |  +33  (0)6  86  12  78  79

COMMERCIAL  INQUIRIES:ali.erdengiz@cea.fr  +33  (0)1  69  08  92  03  |  +33  (0)6  78  97  78  86

Centre   de  Grenoble17  rue  des  Martyrs

38054  Grenoble   Cedex

Centre   de  SaclayNano-‐Innov PC  172

91191  Gif sur  Yvette  Cedex