@let@token Towards a Modelling and Design Framework for...

OutlineIntroduction

Design Disciplines related to MCS designProposed core MCS ontology

Open aspects and features for MCS designConclusions

Towards a Modelling and Design Framework forMixed-Criticality SoCs and Systems-of-Systems

F.Herrera, H. Attarzadeh and I. Sander

KTH Royal Institute of Technology

DSD’13, Santander (Spain), Sept. 26th, 2013

F.Herrera, H. Attarzadeh and I. Sander Towards a Modelling and Design Framework for Mixed-Criticality SoCs and Systems-of-Systems

OutlineIntroduction



Introduction

Design Disciplines related to MCS design

Proposed core MCS ontology

Open aspects and features for MCS design

Conclusions


OutlineIntroduction



Mixed-Criticality Systems (MCSs)

I Integrated suite of hardware, operating system andmiddleware services and application software that supports theexecution of safety-critical, mission-critical, and non-criticalsoftware within a single, secure compute platform [Barhorst etal., 2009]

I Core fundational concept in Cyber-Physical Systems [Baruahet al., 2010]


OutlineIntroduction



Mixed Criticality Applications

systemscaleembedded distributed

Criticality

Mixed

Single

FCS

Mixed-Criticality Application

Safety-Critical Best-Effort


OutlineIntroduction



Mixed Criticality Systems


Criticality

Mixed

Single

FCS



Platform

Shared Resources:- computation- communication- memory

Predictability - Efficiencytrade-off


OutlineIntroduction



Mixed Criticality System Scales


Criticality

Mixed

Single

FCS



Platform



MCSoSMCSoC


OutlineIntroduction



Current View


Criticality

Mixed

Single

FCS



Platform



MCSoSMCSoC

NoC EDSHRT


OutlineIntroduction



Towards a Wider Approach


Criticality

Mixed

Single

FCS



Platform



MCSoSMCSoC

NoC EDSHRT


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Extension of Hard Real Time (HRT) Theory


Criticality

Mixed

SingleNoC EDS

HRT

I For Multi-Processors: from [Liu&Lailand, 73] to[David&Burns, 11]

I Consideration of impact of communication resources of the:I NoC [Shi&Burns, 10][Pellizoni et al., RTSSS’09]I Embedded Distributed network, e.g. ECU networks [Rajeev et

al, 10], MAST2 [Harbour et al.&Burns, 12]


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Extension of Hard Real Time theory for MCS


Criticality

Mixed

SingleNoC EDS

HRT

I Priority-based, Reservation-based (→ Criticality inversion)I New scheduling theory [Baruah et al, 2010], e.g. OCPB

I criticality 6= priorityI workloads depend on criticality, i.e. WCET = f (χ) | χ ∈ N+

I schedulign algorithms: OCPB, CAPA

I Standard IEC 61508, SIL


OutlineIntroduction



Other disciplines which should be involved

I Model-driven technologies, MDE, MDA (OMG)I Metamodel, Graphical and standard front-endI M2T (Correctness-by-construction in SW development), M2MI Views (Separation-of-Concerns)

I System-Level modelling/specificationI Abstraction, Concurrency, HeterogeneityI Models of ComputationI Modelling constraints for Properties (Determinism, Deadlock

protection, Boundeness, etc)I Ptolemy II, Metropolis II, ForSyDe, HetSC, SysteMoC,

SystemC-H, ...


OutlineIntroduction



Other disciplines which should be involved

I Design Space ExplorationI Analytical TechniquesI Simulation-based TechniquesI Joint analytical and simulation-based (JAS) techniques

I Simulation-based Performance EstimationI ISS, cycle-accurate ISS, RTL simulatorI VirtualizationI Native Simulation


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Communication modelling and analysis

I Variety of taxonomies:I NoC vs Distributed systemI Switched vs Packetized

I Variety of standards, domains and architecturesI Standards: WiDom, CAN, Spacewire, Flexray, TTEthernet,

AFDX, etc

I Predictable networks: Main parameter: WCCL

I Other properties: Scalability, SegregationI Variety of tools

I NoC simulators: TOPAZ, Nostrum, NoximI DE: MAST2, OMNET, etc..


OutlineIntroduction



A bunch of integrating work already done!

I MoC theory and DSE

I MoC and NoC

I MDA and MoC

I MDA and DSE

I ...


OutlineIntroduction



Core Ontology: SoC

Applications

Platform

S-Mapping

I/O-node

A1

PE3PE1 ...

SoC interconnection(intra-SoC bus / NoC)

n1

�1

�3

G1

�4

m1 m2

sch2

PE2

sch1

PE4

S-IF

in-IFI-SIF(sensor)

O-SIF(actuator)

PE5

m11

m12

�2

�0

m13

MCSoC

A0

SoC platform

SoC-levelmapping

��

f2

intra-SoCmapping


OutlineIntroduction



Core Ontology: SoC/SoS

SoS platform

P-node I-node(sensor)

Applications

Platform

S-Mapping

I/O-node

P-node

A1

SoS interconnection(off-chip bus/network)

PE3PE1 ...


SoS-levelmapping

��

MCSoS

G3

G2

n2

n1

n3 n4

n5

n6

�1

�3

�9 �10

�5

�6

�7

�8G1

�4

m1 m2

m3m4 m5

m6

m7

m8

m9

m10

sch2

PE2

sch1

O-node(actuator)

PE4

S-IF

in-IFI-SIF(sensor)

O-SIF(actuator)

PE5

m11

m12

�2

�0

��

m13

MCSoC

A0

SoC platform

SoC-levelmapping

��

f2

P-node

intra-SoCmapping

A2


OutlineIntroduction



Core Ontology: SoC/SoS (Environment)

SoS platform


Applications

Platform

S-Mapping

I/O-node

P-node

A1


PE3PE1 ...


SoS-levelmapping

��

Environment

MCSoS

G3

G2

n2

n1

n3 n4

n5

n6

�1

�3

�9 �10

�5

�6

�7

�8G1

�4

m1 m2

m3m4 m5

m6

m7

m8

m9

m10

sch2

PE2

sch1

O-node(actuator)

analog

digital

system-levelmodel

domain IF

SoS I/O

PE4

S-IF

in-IF

(e.g., 1&2OSI layers) I-SIF

(sensor)

O-SIF

low-levelmodel

(actuator)

PE5

m11

m12

�2

�0

��

m13

MCSoC

A0

SoC platform

SoC-levelmapping

��

f2

P-node

intra-SoCmapping

A2


OutlineIntroduction



Core Ontology: MCSoC/SoS

SoS platform


Applications

Platform

S-Mapping

I/O-node

P-node

A1


PE3PE1 ...


SoS-levelmapping

��

Environment

MCSoS

G3

G2

n2

n1

n3 n4

n5

n6

�1

�3

�9 �10

�5

�6

�7

�8G1

�4

m1 m2

m3m4 m5

m6

m7

m8

m9

m10

sch2

PE2

sch1

O-node(actuator)

analog

digital

system-levelmodel

domain IF

SoS I/O

PE4

S-IF

in-IF

(e.g., 1&2OSI layers) I-SIF

(sensor)

O-SIF

low-levelmodel

(actuator)

PE5

m11

m12

�2

�0

��

m13

MCSoC

A0

SoC platform

SoC-levelmapping

��

f2

P-node

intra-SoCmapping

WCD(G2)

P<1W

��

Deadlock-free A2


OutlineIntroduction



Multi-level approach

Networks

specific models

generic model

Buses

TTEthernet, Flexray

n3

priority, etc topology, routing policies, buffer sizes, etc.

c24: Dij, BWij,, Lij

BWT, ST

#slots, BWslot, etc

802.11 , WiDom802.3, CAN AFDX, AEthereal

S-IF / in-IF

ap4

n1

n2

n4

For computation nodes

I abstract level: trafficgenerators, and statisticcollectors

I detailed level: SoC model

For the interconnection

I abstract-level: matrix ofP2P links with specificattributes

I detailed-level: specificNoC and network models


OutlineIntroduction



Open Aspects and Features

I Agreed core terminology for modelling elements, e.g. . . .I task = a system-level concurrent behaviour?. . .

I . . . or a software-level concurrent behaviour (thread/process)?

I . . . only for modelling elements?

I actor mapping and actor scheduling [Kumar et al.,12]I Multiprocessor scheduling algorithm → scheduling =

allocation + job ordering [David and Burns,11]


OutlineIntroduction




I Agreed core terminology for modelling elements, e.g. . . .I task = a system-level concurrent behaviour?. . .I . . . or a software-level concurrent behaviour (thread/process)?





OutlineIntroduction









OutlineIntroduction





I . . . only for modelling elements?I actor mapping and actor scheduling [Kumar et al.,12]

I Multiprocessor scheduling algorithm → scheduling =allocation + job ordering [David and Burns,11]


OutlineIntroduction





I . . . only for modelling elements?I actor mapping and actor scheduling [Kumar et al.,12]I Multiprocessor scheduling algorithm → scheduling =



OutlineIntroduction




A2

�1

P1 PN2

PN1

P2

P4

P3 P9 P10

PE1sch1

schedulable(RMA)?

consistency?

�2

N1

N2

N4

N3 N9 N10

(SDF) MoC perspective

HRT perspective

modelComposability of modelsand techniques

I specifically, hard-realtime models andMoCs

I combination ofconstraints andassumptions →properties-byconstruction andanalizability


OutlineIntroduction



Multi-level (platform-model) approach

Seamless swap of computationnodes and networks

I at different levels ofabstraction (enables gradualrefinement and segregationof analysis)

I of different types of physicalplatforms without having tochange sw-level platforms(reuse of RTOS modellingengines, facilitatesautomated exploration)


OutlineIntroduction



Enhanced DSE techniques

I criticality-aware exploration(and optimization)

I Combined static (analytical)and dynamic (simulation-based)DSE techniques

I Combine time constraints e.g.,throughput and deadlines

I DSE enabling exploration ofscheduling policies pluscomputation andcommunication infrastructures

WCA-DSE

SAS-DSE

DesignSpace

Efficient SafeSolutions (ESS)

Scenarios

Environment model

Safe Solutions (SS)

[Herrera&Sander, FDL’13]


OutlineIntroduction



Enhanced DSE techniques

I criticality-aware exploration(and optimization)

I Combined static (analytical)and dynamic (simulation-based)DSE techniques

I Combine time constraints e.g.,throughput and deadlines

I DSE enabling exploration ofscheduling policies pluscomputation andcommunication infrastructures

WCA-DSE

SAS-DSE

DesignSpace

Efficient SafeSolutions (ESS)

Scenarios

Environment model

Safe Solutions (SS)

[Herrera&Sander, FDL’13]


OutlineIntroduction



Integration of MDA/MDE techniques I

I MCSoC/MCSoS metamodel← MCS ontology

I standard and graphicalfront-end,

I integration and automaticgeneration of executablemodels...

I ...for SoC (e.g., COMPLEX),

I ...for MCSoC/SoS (e.g.,[Ebeid et al., UKSim2013])


OutlineIntroduction










OutlineIntroduction




ConsistencyCheckers

model

codegenerators

CCView Platform

Data Functional

Architectural Environment

COMPLEXEclipse App.

SystemArchitecture

Design SpaceEnvironment(SystemC)

CB App. Arch.(C++-based)

SystemC-2.2 SCoPE+ MOST







OutlineIntroduction




ConsistencyCheckers

model

codegenerators

CCView Platform

Data Functional


NoC/SoS

Design Space

Environment CB App.Arch.

PerformanceEstimation

ExplorationTool

SoC/SoSNetwork

PEs/Nodes

codegenerators

NetworkSimulator







OutlineIntroduction



Integration of MDA/MDE techniques: Separation ofConcerns

ConsistencyCheckers

model

codegenerators

CCView Platform

Data Functional


Views (for independent andconcurrent development)

I at SoC-level (e.g.,UML/MARTE COMPLEX)

I at NoC/SoS-level,communication centric,

I analysis-based (MoC vsHRT)

I Criticality-awareperspectives

I and how to combine them?


OutlineIntroduction




ConsistencyCheckers

model

codegenerators

Environment

Nodes Networks

Architectural

Applications








OutlineIntroduction




SchedulabilityAnalysis

tasks

dependencies

rates

channel typesperiod

deadline

WCET model

SDF MoCtheory

schedulable/not schedulableutilization

processors

static scheduling?static schedule

Perspective 1

Perspective 2








OutlineIntroduction




WCET2

WCET1

(�L)

WCET3

(�L)

HighercriticalityAnalysis

model

High Criticality Perspective

WCET2

WCET1

(��)

WCET3

(��)

Lower Criticality Perspective

LowercriticalityAnalysis








OutlineIntroduction











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I Tunable platform in terms of resources for predictability andfor average-optimization

I Techniques for fast assesment of platform requirements interms of the aforementioned resources (criticality profile)

I Criticality regarding performance metrics and properties


OutlineIntroduction



Conclusions

I Mixed Criticality (MC)I a logic consequence of complexity and efficiency,I present at different system scales

I MC System (MCS) Design requires:I A broader, more interdisciplinary, perspectiveI an important integration effort of existing methodologiesI developping novel aspects and features

I This paper:I has provided a view of the main disciplines to be integrated,I proposed a core ontology for MCSoC and MCSoS design,I identified novel aspects and features for MCS design regarding

MDA integration, criticality-aware DSE, etc


OutlineIntroduction



Thanks to:

I the reviewers,

I attendees,

I KTH/ICT Excellence Postdoc position grantI-2011-0646

I We are willing to collaborate!

I Contact:I [email protected] [email protected]


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