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XXX-X-XXXX-XXXX-X/XX/$XX.00 ©20XX IEEE LFN and RTN in Nanoscale Devices: Modeling and Impact on Circuit Operation Christoforos Theodorou IMEP-LAHC Univ. Grenoble Alpes, Univ. Savoie Mont Blanc, CNRS, Grenoble INP Grenoble, France [email protected] Gérard Ghibaudo IMEP-LAHC Univ. Grenoble Alpes, Univ. Savoie Mont Blanc, CNRS, Grenoble INP Grenoble, France [email protected] Abstract—In this work, we present the latest modeling approaches regarding LFN and RTN in advanced MOSFETs, with a special focus on the FDSOI technology. Furthermore, various methods of model implementation are shown, allowing for accurate defect-aware circuit noise and reliability studies. Keywords—Low frequency noise, Random Telegraph Noise, Modeling, Verilog-A, FDSOI, MOSFET I. INTRODUCTION As the intensity of Low frequency noise (LFN) and Random Telegraph Noise (RTN) fluctuations increases with the reciprocal device area, they can therefore jeopardize the functionality of both analog and digital circuits. In Ultra- Thin Body and Box (UTBB) Fully Depleted Silicon-On- Insulator (FDSOI) MOSFETs in particular, LFN and RTN can be further influenced by coupling effects. In this work, we present some important aspects concerning the LFN/RTN modeling in advanced devices, as well as the development of circuit noise simulation methods. II. NOISE MODEL APPROACHES A. Dependence of Hooge parameter on inversion charge As the Hooge mobility fluctuations depend only on the phonon scattering rate [1], the Hooge parameter, α H , should be modulated by its contribution among other scattering mechanisms limiting the carrier mobility: = 0 [ 1 ℎ ( 1 ℎ + 1 + 1 ) ⁄ ] 2 (1) where H0 refers to the intrinsic Hooge parameter and μ ph , μ Cs and μ SR are respectively the phonon, Coulomb and surface roughness scattering limited mobility in the inversion layer [2]. The dependence of H is evaluated theoretically versus the inversion charge from weak to strong inversion, revealing that H is far from being independent of inversion charge, and is maximized when the PH contribution prevails with respect to CS and SR rates. B. Impact of QMEs on Random Telegraph Noise When the trap is not located right at the oxide-channel interface, but at a depth x t in the oxide, the apparent trap energy E t depends on the band bending in the gate dielectric [3], [4]. Moreover, the capture (τ c ) and emission (τ e ) times should be updated when quantum mechanical effects (QMEs) become important. So, finally, τ c and τ e can be expressed in a way that accounts for both x t and QMEs: ̅ = ∙ ∙ () ̅ = . ∙( + ) ∙ ∙ ∙ 1 () (2) where freq is the escape frequency (2.10 13 Hz) of the electrons in the quantized sub-band, Q i1 the inversion charge when E f crosses E t and Q d the depletion charge. C. Flicker noise (1/f) in FDSOI MOSFETs The two-interface Carrier Number Fluctuations (CNF) with Correlated Mobility Fluctuations (CMF) model for the input-referred gate voltage noise, accounting also for the source-drain series resistance noise, can be expressed as (analytical explanation in the extended paper): , = ,i [(1 + i ,i ) 2 + ,j ,i ( 1 1+ , / ) 2 ]+( ,i + 1 2 ) 2 (3) where i corresponds to the operating gate interface and j to the opposite. This equation reveals that the contribution of the back interface to the total 1/f level depends on both the trap density ratio and the oxide to silicon thickness ratios. III. FROM NOISE MODELING TO CIRCUIT SIMULATIONS In the extended paper, we will present the methodology for the implementation of noise models in both time [5] and frequency domains, as well as the Periodic Transient Noise [7] simulation approach. An example of defect-aware transient circuit simulations can be seen in Fig. 1(left), where we used the Verilog-A module we created based on the modelling described in II.B. A method to implement this module in one-step simulations using already existing PDK devices is also presented (Fig. 1(right)). REFERENCES [1] F. N. Hooge, “1/F Noise Sources,” IEEE Trans. Electron Devices, vol. 41, no. 11, pp. 1926–1935, 1994. [2] K. Takagi, T. Mizunami, T. Shiraishi, and M. Wada, “Excess noise generation by carrier fluctuation in semiconductor devices,” in IEEE International Symposium on Electromagnetic Compatibility, 1994. [3] K. S. Ralls et al., “Discrete Resistance Switching in Submicrometer Silicon Inversion Layers: Individual Interface Traps and Low-Frequency Noise,” Phys. Rev. Lett., vol. 52, no. 3, pp. 228–231, 1984. [4] M. J. Kirton, M. J. Uren, S. Collins, and M. Schulz, “Individual defects at the Si:SiO2 interface,” Semicond. Sci. Technol., vol. 4, pp. 1116–1126, 1989. [5] C. G. Theodorou and G. Ghibaudo, “A Self-contained Defect-aware Module for Realistic Simulations of LFN, RTN and Time-dependent Variability in FD-SOI Devices and Circuits,” in IEEE S3S Conference, 2018. [6] C. G. Theodorou, E. G. Ioannidis, S. Haendler, C. A. Dimitriadis, and G. Ghibaudo, “Dynamic variability in 14nm FD-SOI MOSFETs and transient simulation methodology,” Solid. State. Electron., vol. 111, no. September, pp. 100–103, 2015. Fig. 1. Right versus left node voltage plot to extract Read Static Noise Margin with and without the impact of defects (after [5]) (left) and module implementation in existing PDK (right). PDK entity RTN module D G V g -ΔV t S subckt I d
