Libero SoC PolarFire v2.3 Release Notes€¦ · Libero SoC PolarFire v2.3 Release Notes Release...

Libero SoC PolarFire v2.3

Release Notes 11/2018

Libero SoC PolarFire v2.3 Release Notes

Release Notes 1.1 2

Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Fax: +1 (949) 215-4996 Email: [email protected] www.microsemi.com ©2018 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are registered trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.

Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice. About Microsemi Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions; security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, California, and has approximately 4,800 employees globally. Learn more at www.microsemi.com.

51300207-1/11.18

mailto:[email protected]

http://www.microsemi.com/

http://www.microsemi.com/


Release Notes 1.1 3

Revision History

The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.

Revision 1.1 Revision 1.1 includes the following changes (11/02/2018):

• Updated first SPI Flash Programming limitation in section 5.1 SPI Flash Programming• Added section 5.11 IOD_CDR.

Revision 1.0 Revision 1.0 was the first publication of this document (09/14/2018).


Release Notes 1.1 4

Reference Documents

PO0137: Product Overview PolarFire FPGA

DS0141: PolarFire FPGA Datasheet

UG0722: PolarFire FPGA Packaging and Pin Descriptions User Guide

Pin package Assignment Tables:

• MPF300T/MPF300TS-FCG484 Package Pin Assignment Table • MPF300T/MPF300TS-FCVG484 Package Pin Assignment Table • MPF300T/MPF300TS-FCSG536 Package Pin Assignment Table • MPF300T/MPF300TS-FCG784 Package Pin Assignment Table • MPF300T/MPF300TS-FCG1152 Package Pin Assignment Table

UG0752: PolarFire FPGA Power Estimator User Guide

UG0680: PolarFire FPGA Fabric User Guide

UG0684: PolarFire FPGA Clocking Resources User Guide

UG0686: PolarFire FPGA User I/O User Guide

UG0677: PolarFire FPGA Transceiver User Guide

UG0685: PolarFire FPGA PCI Express User Guide

UG0687: PolarFire FPGA 1G Ethernet Solutions User Guide

UG0727: PolarFire FPGA 10G Ethernet Solutions User Guide

UG0676: PolarFire FPGA DDR Memory Controller User Guide

Athena TeraFire Cryptographic Algorithm Library (CAL) Users Guide

UG0743: PolarFire FPGA Debugging User Guide

UG0714: PolarFire FPGA Programming User Guide

UG0725: PolarFire FPGA Device Power-Up and Resets User Guide

UG0726: PolarFire FPGA Board Design User Guide

UG0753: PolarFire FPGA Security User Guide

UG0786: PolarFire FPGA Splash Kit User Guide

DG0755: PolarFire FPGA JESD204B Interface Demo Guide

DG0756: PolarFire FPGA PCIe Endpoint Demo Guide

DG0757: PolarFire FPGA 10GBASE-R Ethernet Loopback Demo Guide

DG0759: PolarFire FPGA Multi-Rate Transceiver Demo Guide

DG0762: PolarFire FPGA DSP FIR Filter Demo Guide

UG0758: PolarFire FPGA Design Flow User Guide

UG0776: PolarFire FPGA Design Constraints User Guide

https://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=136518



https://www.microsemi.com/document-portal/doc_download/136928-mpf300t-mpf300ts-fcg484-package-pin-assignment-table-jun17

https://www.microsemi.com/document-portal/doc_download/136930-mpf300t-mpf300ts-fcsg536-package-pin-assignment-table-june17

https://www.microsemi.com/document-portal/doc_download/136931-mpf300t-mpf300ts-fcg784-package-pin-assignment-table-june17

https://www.microsemi.com/document-portal/doc_download/136932-mpf300t-mpf300ts-fcg1152-package-pin-assignment-table-june17










https://www.microsemi.com/document-portal/doc_download/136599-athena-terafire-cryptographic-algorithm-library-cal-user-s-guide



https://www.microsemi.com/document-portal/doc_download/136530-ug0725-polarfire-fpga-device-power-up-and-resets-user-guide

http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=136520

https://www.microsemi.com/document-portal/doc_download/136534-ug0753-polarfire-fpga-security-user-guide






https://www.microsemi.com/document-portal/doc_download/136766-dg0762-polarfire-fpga-dsp-fir-filter-demo-guide

https://coredocs.s3.amazonaws.com/Libero/pf_2_3_0/Tool/pf_des_flow_ug.pdf

http://coredocs.s3.amazonaws.com/Libero/pf_2_3_0/Tool/des_constraints_ug.pdf


Release Notes 1.1 5

UG0715: PolarFire FPGA PDC Commands User Guide

UG0730: PolarFire FPGA Timing Constraints User Guide

UG0750: PolarFire FPGA I/O Editor User Guide

UG0769: PolarFire FPGA Timing Constraints Editor User Guide

UG0773: PolarFire FPGA SmartDebug User Guide

PolarFire FPGA Macro Library Guide

PolarFire FPGA Tcl Commands Reference Guide

UG0738: Netlist Viewer Interface User Guide

UG0785: Netlist Viewer User Guide

SmartPower User Guide

SmartTime Static Timing Analyzer User Guide

Chip Planner User Guide

Verilog Simulation Guide

VHDL Simulation Guide

https://coredocs.s3.amazonaws.com/Libero/pf_2_3_0/Tool/pf_pdc_ug.pdf

https://coredocs.s3.amazonaws.com/Libero/pf_2_3_0/Tool/pf_timing_constr_flow_ug.pdf

https://coredocs.s3.amazonaws.com/Libero/pf_2_3_0/Tool/pf_io_editor_ug.pdf

https://coredocs.s3.amazonaws.com/Libero/pf_2_3_0/Tool/smarttime_ce_ug.pdf

https://coredocs.s3.amazonaws.com/Libero/pf_2_3_0/Tool/pf_smartdebug_ug.pdf

https://coredocs.s3.amazonaws.com/Libero/pf_2_3_0/Tool/pf_mlg.pdf

https://coredocs.s3.amazonaws.com/Libero/pf_2_3_0/Tool/pf_mlg.pdf

https://coredocs.s3.amazonaws.com/Libero/pf_2_3_0/Tool/pf_tcl_cmd_ug.pdf

https://coredocs.s3.amazonaws.com/Libero/pf_2_3_0/Tool/nlv_interface_ug.pdf

https://coredocs.s3.amazonaws.com/Libero/pf_2_3_0/Tool/stdalone_nlv_ug.pdf

https://coredocs.s3.amazonaws.com/Libero/pf_2_3_0/Tool/smartpower_ug.pdf

https://coredocs.s3.amazonaws.com/Libero/pf_2_3_0/Tool/pf_smarttime_sta_ug.pdf

https://coredocs.s3.amazonaws.com/Libero/pf_2_3_0/Tool/chipplanner_ug.pdf

https://coredocs.s3.amazonaws.com/Libero/pf_2_3_0/Tool/vlogsim_ug.pdf

https://coredocs.s3.amazonaws.com/Libero/pf_2_3_0/Tool/vlogsim_ug.pdf

https://coredocs.s3.amazonaws.com/Libero/pf_2_3_0/Tool/vhdlsim_ug.pdf


Release Notes 1.1 6

Contents

Revision History .............................................................................................................................. 3 Revision 1.1........................................................................................................................................................... 3 Revision 1.0........................................................................................................................................................... 3

1 Libero SoC PolarFire™ v2.3 Software Release Notes ............................................................... 8 Software Enhancements in Libero SoC PolarFire v2.3 ............................................................................... 8

1.1.1 Device Support ............................................................................................................................ 8 1.1.2 Place and Route Enhancements .................................................................................................. 8 1.1.3 Programming ............................................................................................................................... 8 1.1.4 Design Initialization ..................................................................................................................... 9 1.1.5 Pre-Layout IBIS Support ............................................................................................................... 9

Silicon Features .......................................................................................................................................... 9 1.2.1 I/O’s ............................................................................................................................................. 9 1.2.2 Memories .................................................................................................................................... 9 1.2.3 IOD Interfaces .............................................................................................................................. 9 1.2.4 Transceiver Interfaces ................................................................................................................ 10

2 Device Support ....................................................................................................................... 11 Pre-production devices ............................................................................................................................ 11 PolarFire Devices supported in Libero SoC PolarFire v2.3 ....................................................................... 11 PolarFire Devices’ Timing and Power Data State in Libero SoC PolarFire v2.3......................................... 13

3 Design Migration .................................................................................................................... 14 General Notes on Design Migration ......................................................................................................... 14

3.1.1 Tool Invalidation ........................................................................................................................ 14 3.1.2 Core Invalidation ........................................................................................................................ 14 3.1.3 Core Upgrade ............................................................................................................................. 14

Cores Supported in Libero SoC PolarFire v2.3 .......................................................................................... 15

4 Resolved Issues ...................................................................................................................... 17 List of Resolved Issues.............................................................................................................................. 17

5 Known Issues and Limitations ................................................................................................ 18 SPI Flash Programming ............................................................................................................................ 18 SPI-Slave Programming ............................................................................................................................ 18 Libero Programming ................................................................................................................................ 18 SmartDebug ............................................................................................................................................. 20 DDR3 and DDR4 and LPDDR3 Memories ................................................................................................. 21 DLL ........................................................................................................................................................... 21 PLL ............................................................................................................................................................ 22 PCIe .......................................................................................................................................................... 22 Transceiver ............................................................................................................................................... 22


Release Notes 1.1 7

IOD Receive Interfaces ............................................................................................................................. 22 PF_IOD_CDR ............................................................................................................................................ 23 Incomplete support for external timing of IOD Generic Interfaces ......................................................... 23 Synthesis .................................................................................................................................................. 23 Standalone Synthesis Flow ...................................................................................................................... 23 SynplifyPro crash if PAD pins of BIBUF drive internal logic ...................................................................... 23 SynplifyPro mapping of sequential-shift to uSRAM does not support initial values .............................. 24 Identify Debugger invoked through Libero opens an extra dialog box .................................................... 24 SynplifyPro version gives an error message for the Linux 7.4 platform ................................................... 24 PolarFire Core Generation Language ....................................................................................................... 24 SSTL15 ODT Values ................................................................................................................................... 24 SmartTime – Incorrect timing values in Max Timing Analysis Report ...................................................... 25 SmartPower - Theta JA value is incorrectly reported in SmartPower reports ......................................... 25 Post-layout simulation is not supported .................................................................................................. 25 sNVM write fails due to ROM client created by previous design ............................................................. 25 Installation on Local Drive Only ............................................................................................................... 25 Visual C++ Redistributable Installation Error ........................................................................................... 25 Modify Install option results in an error dialog........................................................................................ 25 64-bit Linux package containing libpng12.so 64-bit library may be missing ............................................ 26 Installation on Windows 7 ....................................................................................................................... 26 Antivirus Software Interaction ................................................................................................................. 26

6 System Requirements ............................................................................................................ 27

7 Download Libero SoC PolarFire v2.3 Software ...................................................................... 28


Release Notes 1.1 8

1 Libero SoC PolarFire™ v2.3 Software Release Notes

The Libero® system on chip (SoC) PolarFire™ v2.3 software is for designing with Microsemi PolarFire FPGAs. PolarFire FPGAs are the fifth generation nonvolatile FPGA devices from Microsemi, built on 28-nm flash technology. The PolarFire cost-optimized FPGAs deliver lowest power at mid-range densities.

For more information about PolarFire devices, see the Microsemi website.

Software Enhancements in Libero SoC PolarFire v2.3 The Libero SoC PolarFire v2.3 release includes the following new features and enhancements.

1.1.1 Device Support The Libero SoC PolarFire v2.3 release includes the following device support enhancements:

• Preliminary timing data for MPF100/T/TS/TLS and MPF200/T/TS/TLS • Updated timing data for MPF500/T/TS/TLS • Simultaneous Switching Noise (SSN) Analyzer support for FCG1152 and FCG484 packages for all

‘T/TS/TLS’ devices • IBIS-IO design specific export support for all ‘T/TS/TLS’ devices

1.1.2 Place and Route Enhancements The Place and Route tool has been enhanced to automatically mitigate several hold violation sources:

• Repair Minimum Delay Violations is now OFF by default. With RMDV OFF P&R will repair hold time violations on a single clock domain implemented on the global network. If your design continues to have internal hold violations with RMDV OFF, you may wish to rerun P&R with RMDV ON in conjunction with Incremental Layout.

• If external hold time violations are seen, Repair Minimum Delay Violations will now attempt to fix them by automatically adjusting programmable delays through I/Os. See the report <root>_mindelay_repair_report.rpt in the <project>/designer/<root>/ directory, which lists all paths that were considered.

• If all hold time violations get fixed for the “Fast process, High voltage and Low temperature” timing corner, Repair Minimum Delay Violations will now further detect hold time violations at the “Slow process, Low voltage and Low temperature” corner, and attempt to repair any remaining violating paths.

I/O Register Combining

• Automatic I/O Register Combining is available in this release. It can be selected in the Place and Route Layout Options dialog. The default is OFF.

1.1.3 Programming Libero SoC PolarFire v2.3 includes the following Programming features:

• Configure Permanent Locks for Production – Security settings can be made permanent for production programming. One-time programming support along with permanently disabling debug or any other security setting can be configured in a bitstream exported for production programming. Permanent lock settings are not applied to programming performed within Libero.

• Back level protection support has been enhanced in this release. The back level version configuration has been moved to the Configure Programming Options tool, allowing any exported bitstream to

http://www.microsemi.com/libero-soc-polarfire


Release Notes 1.1 9

update the back level version. The back level version can now be the same version as the design version being programmed.

o The option to bypass back level protection for Recovery/Golden Bitstreams has been moved to the Export Bitstream tool.

o The SPI Flash Memory configurator has been enhanced to only allow importing SPI Bitstream files that have the bypass back level version option set for Recovery/Golden bitstreams.

1.1.4 Design Initialization Libero SoC PolarFire v2.3 adds support for automatic initialization of RAM’s to zeroes at device power up.

Note: As of this release, 20 sNVM pages are now reserved for Design Initialization, for all Libero SoC PolarFire v2.3 designs.

1.1.5 Pre-Layout IBIS Support The Export IBIS feature is now available before the Place and Route step. To export the IBIS Model, the Libero project must have completed Synthesis (or Compile), and have I/O placement and configuration details specified in the I/O PDC files.

Silicon Features Libero SoC PolarFire v2.3 includes enhancements targeting Silicon Support.

1.2.1 I/O’s I/O Standards

The MIPI25 I/O Standard is now supported for MPF300ES and MPF300XT devices (and T/TS/TL/TLS variants).

1.2.2 Memories QDRII+ Support

Libero SoC PolarFire v2.3 supports a low latency implementation of QDRII+ memories.

DDR3, DDR4, LPDDR3 Enhancements

This release also includes the following enhancements for DDR3, DDR4, and LPDDR3:

• Additional pipeline option for DDR3, DDR4, and LPDDR3 to support improved flexibility for timing closure

• Fixed PARITY/ALERT pinout • Added Presets for PolarFire Evaluation and Splash kits

1.2.3 IOD Interfaces

• Libero SoC PolarFire v2.3 has essential changes to the IOD CDR Interfaces: functional failures found in silicon validation have been fixed, and the training algorithm has been enhanced to increase robustness at power up.

• A new “Fractional Aligned” clocking topology allows support for a source synchronous interface with the sampling clock running at a fraction (4/7/8/10) of the data rate.

• The IOD Generic Receive and Transmit Interface configurator user interface has been significantly enhanced to better guide users to create a valid configuration.


Release Notes 1.1 10

1.2.4 Transceiver Interfaces Libero SoC PolarFire v2.3 includes the following enhancements to the Transceiver Interfaces:

• SyncE support has been added in this release for additional data rates. 10G SyncE 64bit and 1G SyncE 10bit are the newly supported options in the latest version of the Transmit PLL core.

• The CDR lock mode ‘Burst Mode Receiver (BMR)’ is now fully supported. • The CDR lock mode ‘Lock to Reference’ is now fully supported. • TX_BYPASS_DATA and TX_ELEC_IDLE ports are now functionally supported in this release for all the

T/TS devices. New UI options have been added to the Transceiver Interface configurator UI to enable/disable these ports.

• Before Libero SoC PolarFire v2.3, when the Transceiver Interface was configured in Soft PIPE mode, extra ports LANE<n>_TXDATAVALID (for both Soft PCIe and SATA) and LANE<n>_ENCODEDECODEBYPASS (for Soft PCIe) were exposed unnecessarily. These ports are now removed on the Transceiver Interface in this release.



2 Device Support

Pre-production devices Programming support for the MPF100T/TS and MPF500T/TS pre-production devices has been enabled in the Libero SoC PolarFire v2.3 release. Programming support for MPF200T/TS and MPF300T/TS pre-production devices was enabled in the Libero SoC PolarFire v2.2 release.

PolarFire Devices supported in Libero SoC PolarFire v2.3

Device Package Speed Grade Core Voltage Range `License Required

MPF100T

FCSG325 -1, STD 1.0/1.05V EXT/IND Eval/Silver/Gold/Platinum

FCVG484 -1, STD 1.0/1.05V EXT/IND Eval/Silver/Gold/Platinum

FCG484 -1, STD 1.0/1.05V EXT/IND Eval/Silver/Gold/Platinum

MPF100TL

FCSG325 STD 1.0/1.05V EXT/IND Eval/Silver/Gold/Platinum

FCVG484 STD 1.0/1.05V EXT/IND Eval/Silver/Gold/Platinum

FCG484 STD 1.0/1.05V EXT/IND Eval/Silver/Gold/Platinum

MPF100TLS

FCSG325 STD 1.0/1.05V IND Eval/Platinum

FCVG484 STD 1.0/1.05V IND Eval/Platinum

FCG484 STD 1.0/1.05V IND Eval/Platinum

MPF100TS

FCSG325 -1, STD 1.0/1.05V IND Eval/Platinum

FCVG484 -1, STD 1.0/1.05V IND Eval/Platinum

FCG484 -1, STD 1.0/1.05V IND Eval/Platinum

MPF200T

FCSG325 -1, STD 1.0 /1.05V EXT/IND Eval/Gold/Platinum

FCSG536 -1, STD 1.0 /1.05V EXT/IND Eval/Gold/Platinum

FCVG484 -1, STD 1.0 /1.05V EXT/IND Eval/Gold/Platinum

FCG484 -1, STD 1.0 /1.05V EXT/IND Eval/Gold/Platinum


MPF200TL

FCSG325 STD 1.0 /1.05V EXT/IND Eval/Gold/Platinum

FCSG536 STD 1.0 /1.05V EXT/IND Eval/Gold/Platinum

FCVG484 STD 1.0 /1.05V EXT/IND Eval/Gold/Platinum

FCG484 STD 1.0 /1.05V EXT/IND Eval/Gold/Platinum

FCG784 STD 1.0 /1.05V EXT/IND Eval/Gold/Platinum

MPF200TLS

FCSG325 STD 1.0 /1.05V IND Eval/Platinum


FCVG484 STD 1.0 /1.05V IND Eval/Platinum

FCG484 STD 1.0 /1.05V IND Eval/Platinum


MPF200TS FCSG325 -1, STD 1.0/1.05V IND Eval/Platinum







MPF300T_ES

FCG484 -1, STD 1.0 /1.05V EXT/IND Eval/Platinum


FCSG536 -1, STD 1.0 /1.05V EXT/IND Eval/Platinum

FCVG484 -1, STD 1.0 /1.05V EXT/IND Eval/Platinum

FCG784 -1, STD 1.0/1.05V EXT/IND Eval/Platinum

MPF300TS_ES


FCG 1152

STD 1.0 /1.05V EXT/IND Eval/Platinum

-1 1.0 /1.05V EXT/IND Eval/Gold/Platinum




MPF300XT




MPF300T






MPF300TL

FCG484 STD 1.0 /1.05V EXT/IND Eval/Platinum

FCG1152 STD 1.0 /1.05V EXT/IND Eval/Platinum

FCSG536 STD 1.0 /1.05V EXT/IND Eval/Platinum

FCVG484 STD 1.0 /1.05V EXT/IND Eval/Platinum

FCG784 STD 1.0/1.05V EXT/IND Eval/Platinum

MPF300TLS




FCVG484 STD 1.0 /1.05V IND Eval/Platinum


MPF300TS

FCG484 -1, STD 1.0/1.05V IND Eval/Gold/Platinum


-1 1.0 /1.05V IND Eval/Gold/Platinum




MPF500T FCG784 -1, STD 1.0/1.05V EXT/IND Eval/Platinum


MPF500TL FCG784 STD 1.0/1.05V EXT/IND Eval/Platinum



FCG1152 STD 1.0/1.05V EXT/IND Eval/Platinum

MPF500TLS FCG784 STD 1.0/1.05V IND Eval/Platinum


MPF500TS FCG784 -1, STD 1.0 /1.05V IND Eval/Platinum

FCG1152 -1, STD 1.0 /1.05V IND Eval/Platinum

See the Licensing web page for licensing details.

PolarFire Devices’ Timing and Power Data State in Libero SoC PolarFire v2.3 In this release, the timing data state for the MPF100T/TS and MPF200T/TS devices has been upgraded to “Preliminary”. Timing data for the MPF500T/TS has been updated and is close to being Preliminary.

The table below summarizes timing and power data state for all PolarFire devices as of Libero SoC PolarFire v2.3.

Device Timing Data State Power Data State MPF100T/TS/TL/TLS Preliminary Advance

MPF200T/TS/TL/TLS Preliminary Advance

MPF300TES/TS_ES Advance Advance

MPF300XT Production Production

MPF300T/TS/TL/TLS Preliminary Preliminary

MPF500T/TS/TL/TLS Advance Advance

https://www.microsemi.com/products/fpga-soc/design-resources/licensing#overview



3 Design Migration

General Notes on Design Migration

3.1.1 Tool Invalidation Libero SoC PolarFire v2.3 is a major release milestone in the Microsemi® PolarFire FPGA program. Bug fixes and enhancements to some silicon features may require core upgrade and tool reruns for users migrating from Libero SoC PolarFire v2.2.

1. For MPF100T/TS, MPF200T/TS, and MPF500T/TS devices, after opening your project in this release, Verify Timing and Verify Power tools will be invalidated, and must be rerun to regenerate updated timing and power reports.

2. The 'Generate Design Initialization Data' step will be invalidated. Rerun this step before generating a programming file.

3. For MPF100T/TS, MPF200T/TS, MPF300T/TS, and MPF500T/TS designs containing the Transceiver Interface (including PCIe), Synthesize/Compile will be invalidated.

4. For designs containing an IO driving both FPGA fabric components and PLL/DLL reference clocks, Libero SoC PolarFire v2.2 may have generated an incorrect netlist. This has been fixed in Libero SoC PolarFire v2.3. If, upon opening your project with Libero SoC PolarFire v2.3, it is determined that the project is affected by this issue, Synthesize/Compile will be invalidated. Rerun the Synthesize/Compile step (and downstream tools) to generate a corrected bitstream.

3.1.2 Core Invalidation Designs containing the following cores will be invalidated upon migrating Libero SoC PolarFire v2.2 created projects to Libero SoC PolarFire v2.3:

• PolarFire System Services • PolarFire RGMII TO GMII • PolarFire IOD CDR • PCI Express*

* While the PCI Express core is not being invalidated, it is highly recommended to regenerate it with Libero SoC PolarFire v2.3; upon regeneration, new constraints will be created, which will help with timing closure of PCIe solutions. You must rerun the Derived Constraints step in the Constraints Manager for those constraints to be used by Libero.

For the above cores, you must do the following: 1. Download the latest version of the core into your vault. 2. Upgrade all instances of the core in your design to the latest version.

a. Resolve any dropped connections due to changed port interfaces. 3. Regenerate the design. 4. Rerun the Derive Constraints step. 5. Rerun the tool flow.

3.1.3 Core Upgrade If a Libero SoC PolarFire v2.2 created project contains the following cores, and the cores have been generated, they do not need to be upgraded upon migrating the project to the latest Libero SoC PolarFire v2.3. However, if the core needs to be generated again for any reason (e.g. change in parameters, instantiation of a new core, etc.), the latest version from the Catalog must be downloaded and used.



• CoreSmartBERT • Clock Conditioning Circuitry (CCC) • Clock Divider • DDR3 • DDR4 • LPDDR3 • QDR • PolarFire IOD Generic Receive Interfaces • PolarFire IOD Generic Transmit Interfaces • PolarFire 7:1 LVDS Receive Interface, and PolarFire 7:1 LVDS Transmit Interface: These cores are

obsolete as of Libero SoC PolarFire v2.3. The use models supported by these cores can now be accessed in the IOD Generic Receive and Transmit Interface cores.

• Tamper • Transmit PLL • Transceiver Interface

Cores Supported in Libero SoC PolarFire v2.3

Display Name Libero SoC PolarFire v2.3

Changes from Libero SoC PolarFire v2.2

Clock Conditioning Circuitry (CCC)

1.0.115 Added an internal option used by the CCC included in the IOD CDR core

Clock divider 1.0.103 Added generated clock constraint even when the divider is 1

CoreSmartBERT 2.2.101 Uses the latest Transceiver Interface core version

Crypto 1.0.105 None

DDR3 2.3.118 • See section 1.2.2

DDR4 2.3.118 • Defeatured the 2CK write preamble option

• See section 1.2.2

QDR 1.2.103 Added option for low latency

Glitchless clock mux 1.0.101 None

LPDDR3 2.2.109 • See section 1.2.2

PCI Express 1.0.242 Added false paths in the core-generated constraints for TL_CLK related arcs; users must regenerate the core and rerun the Derive Constraints step

PF Dual-Port Large SRAM 1.1.110 None

PF Micro SRAM 1.1.107 None



PF Two-Port Large SRAM 1.1.108 Generates logic that gates-off ECC flags for inactive RAM blocks and to ensure that simulation shows ECC flags as unknown when not in valid data out clock cycle or when BLK_EN is de-asserted

PF uPROM 1.1.108 None

PolarFire 7:1 LVDS Receive Interface

Obsolete No longer available in PF v2.3; use PolarFire IOD Generic Receive Interfaces instead

PolarFire 7:1 LVDS Transmit Interface

Obsolete No longer available in PF v2.3; use PolarFire IOD Generic Transmit Interfaces instead

PolarFire Dynamic Reconfiguration Interface

1.0.101 None

PolarFire IOD CDR 1.1.102 See section 1.2.3

PolarFire IOD Generic Receive Interfaces

1.1.109 See section 1.2.3

PolarFire IOD Generic Transmit Interfaces

1.1.106 See section 1.2.3

PolarFire Initialization Monitor 2.0.103 None

PolarFire RC Oscillators 1.0.102 None

PolarFire RGMII TO GMII 1.1.105 Fully validated and characterized on Silicon

PolarFire SRAM (AHBLite and AXI)

1.1.125 None

Tamper 1.0.107 Removed zeroization 'recoverable' option

Temperature and Voltage Sensor Interface

1.0.105 None

Transceiver Interface 1.0.233 See section 1.2.4

Transceiver Reference Clock 1.0.103 None

Transmit PLL 1.0.114 Added support for 10G SyncE 64bit and 1G SyncE 10bit

PolarFire System Services 2.2.107 • Fixed some functional failures • Removed support for Flash*Freeze



4 Resolved Issues

The following table lists the customer-reported SARs resolved in Libero SoC PolarFire v2.3. Resolution of previously reported “Known Issues and Limitations” is also noted in this table.

List of Resolved Issues Case Number Description 493642-2499023632 The "Generate FPGA Array Data" step crashes for a PolarFire design

493642-2496543854 When Libero is closed and opened after running Device and Memory Initialization, memory content is set to default

493642-2481086055 Firmware Catalog does not work 493642-2471364031 PTOLEMI EXCEPTION error appears upon running Verify Timing 493642-2470491282 IOD Generic Receive Interfaces: Add ports to control IO delay 493642-2470309662 IOD Generic Receive Interfaces: Error on generating a valid configuration 493642-2446710730, 493642-2480022115 DDR4: Parity port has no assignment available

493642-2498365977 IBIS models for DDR4 (North-East bank) do not correspond to Package Pin Assignment Table

493642-2389994047 DDR3: PolarFire Evaluation Kit Preset data width is incorrect

Transceiver Interface: Fixed an issue where imprecision in the RXPLL configuration would cause a slow shift between the data stream and clock generated by RXPLL (in the 12.5 Gbps serial data rate and 125 MHz CDR reference clock use case).



5 Known Issues and Limitations

SPI Flash Programming This release includes the following limitations:

• Libero SoC PolarFire v2.3 SPI Flash programming support is currently limited to the Micron 1Gb MT25Q SPI Flash devices, such as those on the PolarFire Eval Kit. Support for additional vendors and additional SPI Flash part numbers is planned for a future release.

• This tool erases the SPI Flash prior to programming. It is recommended to program the SPI Flash with Libero SoC PolarFire v2.3 prior to programming other data on the SPI Flash using non-Libero programming solutions.

• Partial update of the SPI Flash is currently not supported.

• It is not recommended to have huge gaps between clients in the SPI Flash, since gaps are currently programmed with 1’s and will increase programming times.

The following table lists the ERASE, PROGRAM, and VERIFY/READ times for different client sizes. All times are in hh:mm:ss.

Note: Depending on the SPI-Flash memory silicon version, you may observe a shorter erase time.

SPI Size ERASE PROGRAM VERIFY/READ TCK Programmer

1 MB 00:03:55 00:00:45 00:10:46 4MHz FP5

1 MB 00:03:55 00:00:28 00:10:05 15MHz FP5

9 MB 00:03:55 00:06:38 01:19:15 4MHz FP5

9 MB 00:03:55 00:04:26 01:08:49 10MHz FP5

18 MB 00:03:55 00:09:04 02:32:43 10MHz FP5

128 MB 00:03:55 00:58:38 22:07:55 15MHz FP5

SPI-Slave Programming Programming Libero SoC PolarFire v2.3 via SPI-Slave instead of JTAG is currently not supported. Support for this use model will be added in a future release.

Libero Programming

• The following error message is displayed when an sNVM client is not selected for programming: “Exit -22 Bitstream or data is corrupted or noisy”

Workaround: Enable all sNVM clients for programming.

• The following error message is displayed when an authenticated/encrypted sNVM client is programmed in Libero: “Exit -22: Bitstream or data is corrupted or noisy”

Workaround: Export a bitstream file or Export FlashPro Express Job and program the device outside of Libero using FlashPro Express, DirectC, or Auto Programming

• Updating the security or sNVM with a security-only bitstream or sNVM-only bitstream on a device that has the Fabric programmed will disable the Fabric.



If the Fabric has been disabled, you must reprogram the Fabric to enable it.



Workaround: 1. sNVM only bitstreams: Field update bitstream files should always program the Fabric

with sNVM.

2. Security only bitstreams: Security only bitstream should be used on a blank device only.

• When a device is programmed with a blank Silicon Signature field, it will not get erased.

Workaround: 1. Specify a Silicon Signature that is not blank and program the device to change value. 2. Perform Erase program action to erase it.

SmartDebug This release includes the following limitations:

• General Limitations • Standalone SmartDebug: Non Microsemi Devices in chain: Microsemi devices present in

chain along with non-Microsemi devices cannot be debugged using standalone SmartDebug. Workaround: Users should use SmartDebug through the Libero flow to debug Microsemi Devices.

• Standalone SmartDebug: ID Code of Microsemi device cannot be read when non-Microsemi device is connected in chain when using standalone SmartDebug. Workaround: Users should use SmartDebug through the Libero flow to perform this operation.

• Logical View: The logical view cannot be reconstructed for:

• LSRAM/uSRAM for port widths of x1 inferred through RTL.

• LSRAM/uSRAM configurations when a single net of output bus is used i.e. A_DOUT[0]/B_DOUT[0] for DPSRAM/uSRAM and RD[0] for TPSRAM and others are unused. The memories can be read/write using physical view.

• LSRAM/uSRAM configurations inferred using IP Cores CoreAHBLtoAXI (Verilog flow), CoreFIFO (Verilog and VHDL flow).

• HDL modules inferring RAM blocks that are instantiated in SmartDesign.

Workaround: There are no workarounds for the issues above at this time.

• Physical View: RAM content read using the Physical View of SmartDebug for LSRAM 1Kx18 configuration (which are inferred through RTL) is incorrect. This is due to improper pin assignments on A_DIN and A_DOUT ports. This will be fixed in upcoming Libero SoC PolarFire releases.

• The runtime to Generate SmartDebug FPGA Array Data for designs with a fully utilized MPF500T device is very large (100mns). This runtime issue will be addressed in the upcoming Libero SoC v12.0 release.

• Running Probe insertion from SmartDebug on a large MPF500T device results in SmartDebug tool crash. This issue will be fixed in the upcoming Libero SoC v12.0 release.

• Transceiver Limitations

• Plot Eye introduces a burst of errors in data traffic on XCVR lanes when started. This will be fixed in an upcoming Libero SoC PolarFire release.



Workaround: Enable Eye Monitor using the PowerOn Eye Monitor option before starting the traffic. This will power on the DFE and EM receivers in CDR mode and no errors will be seen during eye plot.

• The Custom DFE solution (using the Optimize DFE option in the Eye Monitor tab) does not work when the transceiver is configured in 8B10B PCS-PMA mode and the receiver is DFE. Workaround: Perform the following steps to obtain the expected eye output with PLOT_EYE.

1. Assert PCS RX RESET 2. Optimize DFE 3. Plot Eye 4. De-Assert PCS RX RESET

• SmartBERT IP does not work when lanes are configured at 250Mbps data rate. • SmartBERT IP PRBS tests take more time to start/stop/inject error on RHEL 7.x and Cent OS

7.x platforms as compared to RHEL 6.x and Windows OS. This issue is seen only with PRBS patterns from SmartBERT IP, and will be fixed in upcoming Libero SoC PolarFire releases.

• The Power ON eye monitor TCL command (eye_monitor_power) does not work correctly in Libero SoC PolarFire v2.3. RX PLL does not lock to the incoming data after this TCL command is run. This will be fixed in upcoming Libero SoC PolarFire releases.

Workaround: There are no workarounds for the issues above at this time.

• Signal Integrity Limitations

• The RX Polarity Signal Integrity parameter (Polarity P/N reversal) has no effect when a PDC file is imported using the Import option in SmartDebug. This flow works fine in GUI mode. This will be fixed in upcoming Libero SoC PolarFire releases.

• For specific settings of Signal Integrity in SmartDebug (in CDR or DFE mode), there is no matching RX_CTLE Libero name after Optimize Receiver.

Workaround: Currently, there is no workaround for this issue. The Optimize Receiver step runs successfully. However, the RX_CTLE value in the Signal Integrity pane of the SmartDebug GUI is not updated.

DDR3 and DDR4 and LPDDR3 Memories • The Constraints Coverage report indicates some missing constraints; this can be ignored. • The option “READ DBI enable” should be off for DDR4 and will be removed in future releases.

• The default values for ODT and output impedance of the DDR4 I/O’s have been changed in Libero SoC PolarFire v2.3; you must rerun the Synthesis or Compile tool for the new default values to take effect. Note that when opening a pre-Libero SoC PolarFire v2.3 design which is in post-synthesis state, the I/O editor tool incorrectly shows the new default values. Rerun synthesis or compile for the new default values to take effect.

DLL • Secondary Phase Restrictions Missing: Although the user can specify values for Primary and

Secondary phase with no restrictions, the Secondary Phase value cannot be lower than the Primary Phase value. Workaround: Do not set the Secondary Phase value lower than the Primary Phase value.

• In DLL Phase Generation Mode, the secondary output clocks are not producing the correct phase in pre-synth HDL simulations. Workaround: There is no workaround at this time.



PLL • Only the post-VCO feedback mode is available in this release. • Bypass option on output clocks is not available in this release. • The maximum PFD frequency (fractional mode) supported for MPF300T in Silicon is 225Mhz.

However, this maximum limit is not yet supported in the Libero configurators (maximum PFD frequency supported is 125 MHz). It will be supported in the upcoming Libero SoC v12.0 release.

PCIe • For BFM simulation of AXI master or slave, the simulator may print out a warning message about

AHB signals, such as “HRESP”. The warning message can be ignored. • When the PCI Express Interface is configured to use the "PCIe_1" controller in x4 lane mode,

DMA transfers may fail in RTL simulations (simulation may hang after configuring the PCIe DMA register space). There is no workaround identified for this issue.

Transceiver • For the MPF300XT, MPF300TES, and MPF300TSES devices, the TX_ELEC_IDLE and TX_BYPASS_DATA

signals are nonfunctional and must always be tied-off to “GND’. • For all PolarFire devices except MPF300XT, MPF300TES, and MPF300TSES devices, if the Transceiver

configuration in a pre-Libero SoC PolarFire v2.3 project uses one of the above parameters, the Transceiver core must be upgraded, and only one of the two parameters should be checked.

IOD Receive Interfaces The maximum data rate depends on the interface selected and the physical location where it is placed, as per the table below. This check will be added in the upcoming Libero SoC v12.0 release.

Max data rate (Mbps) per interface per location

Interface Bank 0/1/7 Bank 4/5 Bank 2/6

RX_DDR_G_A 670 630 620

RX_DDR_L_A 500 500 500

RX_DDR_R_A 500 500 500

RX_DDR_G_C 670 630 620

RX_DDR_L_C 500 500 500

RX_DDR_R_C 500 500 500

RX_DDRX_B_A 740 600 630

RX_DDRX_BL_A 440 410 440

RX_DDRX_B_C 740 600 630



RX_DDRX_BL_C 440 410 440

TX_DDR_G_A 1000 1000 1000

TX_DDR_G_C 1000 1000 1000

TX_DDRX_B_A 1600 1066 0

TX_DDRX_B_C 1600 1066 0

TX_DDRX_B 1600 1066 0

For details, refer to DS0141: PolarFire Datasheet.

PF_IOD_CDR The interface signals shown in the PF_IOD_CDR configurator GUI are inconsistent with the signals shown in SmartDesign. This issue will be fixed in the upcoming Libero SoC v12.1 release.

Incomplete support for external timing of IOD Generic Interfaces In this release, some IOD Generic Interfaces’ external timing arcs are not implemented. As a result, Static Timing Analysis results for external clock to out, setup, and hold for IOD Generic Interfaces may be incomplete, or the delay values may be incorrect. This will be addressed in the subsequent Libero SoC v12.0 release

Synthesis The Synplify Pro software that is bundled with Libero SoC PolarFire v2.3 is intended to be used only with PolarFire devices.

Standalone Synthesis Flow Libero SoC PolarFire v2.3 users may synthesize their design outside the PolarFire tool by using Synopsys SynplifyPro directly. When using this flow, the following additional steps are necessary to successfully synthesize and implement a design:

• Ensure that the <install location>/Designer/data/aPA5M/polarfire_syn_comps.v is passed to SynplifyPro. This file contains module declarations with timing information for PolarFire primitives not known to Synopsys.

• Many configured cores generate timing constraints. You must ensure that these constraint files are passed to synthesis for optimal results. These constraint files must also be imported into Libero along with the synthesis gate level netlist to get optimal place and route and timing analysis results. Core generate constraint files must be modified so that constraints are expressed using the proper hierarchical name of the configured cores in the top-level design.

SynplifyPro crash if PAD pins of BIBUF drive internal logic Correct your design so that PAD pins of I/O macros can only be connected to top level ports of the design.

https://www.microsemi.com/document-portal/doc_download/136519-ds0141-polarfire-fpga-datasheet



SynplifyPro mapping of sequential-shift to uSRAM does not support initial values PolarFire does not support initial values on registers (SLE) or Sequential-shift constructs mapped to uSRAM. If an initial value is specified for a register in the RTL code, the tool ignores the value and issues a warning.

Identify Debugger invoked through Libero opens an extra dialog box Invoking Identify Debugger through Libero opens an Open View dialog box.

Workaround: Ignore the dialog box and click No. This will open the correct project in Identify Debugger through Libero. Another option is to open SynplifyPro interactively, configure Identify Debugger, and open it through SynplifyPro.

SynplifyPro version gives an error message for the Linux 7.4 platform Checking the SynplifyPro version with following command returns an error message:

synplify_pro -version -batch

Error creating '"Internal Error: unsupported format used in message: '

Error creating '"Internal Error: unsupported format used in message: '

N-2017.09M-SP1-1

Note: In Libero, Add Profile -> Synthesis -> Version Name will display the same error message.

RHEL7.4 is supported and this message can be ignored.

PolarFire Core Generation Language With Libero SoC PolarFire v2.3, some PolarFire cores generate only Verilog files, regardless of the preferred HDL language selected. Affected cores include:

• Cores in the PolarFire Features list • Clocking: CCC, RC Oscillators, No-Glitch Mux • Memories: DDR3, DDR4, LPDDR3, Large SRAM, Micro SRAM

VHDL users desiring to simulate designs containing affected cores must use mixed-language simulation (available with ModelSim ME Pro, which is bundled with Libero SoC PolarFire releases, and requires a Gold, Platinum, or Eval license).

SSTL15 ODT Values In XT and ES devices, 20 Ohm and 30 Ohm terminations do not currently output the correct ODT value in SSTL15.

Workaround: Set 20 Ohm and 30 Ohm termination to the 40 Ohm termination value.



SmartTime – Incorrect timing values in Max Timing Analysis Report When an edge shift is specified on a generated clock, common clock period calculation for inter-clock domains with that clock may fail. In such cases, slack calculated for these inter-clock domains will be incorrect.

SmartPower - Theta JA value is incorrectly reported in SmartPower reports In SmartPower reports, the Theta JA value is always reported as "8" and is incorrect. Users should always use the value shown in the GUI, which is correct.

Post-layout simulation is not supported The Libero SoC PolarFire v2.3 release does not support post-layout simulation.

sNVM write fails due to ROM client created by previous design In the scenario where a PolarFire device is first programmed with a design with an sNVM client, and then reprogrammed with a (different) design without an sNVM client, upon completion of programming with the second design, the sNVM client will not be erased. In such a case, if there are sNVM pages that are locked, writes to those pages will fail.

There is no programming action to erase sNVM completely.

Workaround: Create a dummy sNVM client (filled with 0's) in the second design.

Installation on Local Drive Only This release is intended for installation only on a local drive. The Installer might report permission rights problems if the release is installed across a networked drive.

Visual C++ Redistributable Installation Error C++ installation error can be ignored. Required files will install successfully.

On some machines, the InstallShield Wizard displays a message stating:

The installation of Microsoft Visual C++ Redistributable Package (x86) appears to have failed. Do you want to continue the installation?

Click Yes and the software is installed successfully.

Modify Install option results in an error dialog After installation, if the Libero SoC PolarFire v2.3 installer is reinvoked, options are presented to Install a new instance, or Modify the existing Instance. Upon selecting the Modify option, an error dialog pops up with the message “Error while checking for instances”.

Workaround: To modify your installation, navigate to the following shortcut: Start Menu -> Microsemi Libero SoC PolarFire v2.3 -> Uninstall or Modify Libero SoC PolarFire v2.3.



64-bit Linux package containing libpng12.so 64-bit library may be missing In addition to the steps outlined in the Libero SoC Linux Environment Setup User Guide, Libero SoC Linux users must check to see if the 64-bit package containing the libpng12.so 64-bit library is installed. Follow the steps below to check/install the package on RHEL/CentOS 6 and RHEL/CentOS 7 systems.

RHEL/CentOS 6

1. Run the following command: yum provides libpng

2. Check the output and verify that libpng.*.el6_*.x86_64 is shown as installed. 3. If not installed, run the following command under root/sudo:

yum install libpng.x86_64

RHEL/CentOS 7

1. Run the following command: yum list installed | grep png12

2. Check the output and verify that libpng12.x86_64 is shown as installed. 3. If not installed, run the following command under root/sudo:

yum install libpng12.x86_64

Installation on Windows 7 During Libero SoC PolarFire v2.3 installation on Windows 7 machines, you may see pop-up warning messages about shortcuts toward the end of installation process.

These messages can be safely ignored. Click OK to close the pop-up windows and the installation will proceed and complete as expected. All Windows shortcuts will appear correctly.

Antivirus Software Interaction Many antivirus and HIPS (Host-based Intrusion Prevention System) tools will flag executables and prevent them from running. To eliminate this problem, users must modify their security setting by adding exceptions for specific executables. This is configured in the antivirus tool. Contact the tool provider for assistance.

Many users are running Libero SoC PolarFire successfully with no modification to their antivirus software. Microsemi is aware of issues for some antivirus tool settings that occur when using Symantec, McAfee, Avira, Sophos, and Avast tools. The combination of operating system, antivirus tool version, and security settings all contribute to the end result. Depending on the environment, the operation of Libero SoC PolarFire v2.3, ModelSim ME and/or Synplify Pro ME may or may not be affected.

All public releases of Libero software are tested with several antivirus tools before they are released to ensure that they are not infected. In addition, Microsemi’s software development and testing environment is also protected by antivirus tools and other security measures.

https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0ahUKEwiPyPfFy7PbAhWE4IMKHSHvAiIQFggpMAA&url=https%3A%2F%2Fwww.microsemi.com%2Fdocument-portal%2Fdoc_view%2F132361-how-to-set-up-your-linux-environment-for-libero&usg=AOvVaw3p0tvPCevPfeJ_wbx_51zu



6 System Requirements

The Libero SoC PolarFire v2.3 release has the following system requirements:

• 64-bit OS o Windows 7, Windows 8.1, or Windows 10 OS o RHEL 6.6 or later, RHEL 7, CentOS 6.6 or later, or CentOS 7

• A minimum of 32 GB RAM

Note: Setup instructions for using Libero SoC PolarFire v2.3 on Red Hat Enterprise Linux OS or CentOS are available here. As noted in that document, installation step 2 now includes running a shell script (bin/check_linux_req.sh) to confirm the presence of all required runtime packages.

https://www.microsemi.com/document-portal/doc_download/132361-how-to-set-up-your-linux-environment-for-libero



7 Download Libero SoC PolarFire v2.3 Software

The following are available for download:

• Libero SoC PolarFire v2.3 for Linux • Libero SoC PolarFire v2.3 for Windows • Libero SoC PolarFire v2.3 MegaVault

Note: Installation requires administrative privileges.

After successful installation, clicking Help-> About Libero will show Version: 12.200.35.9.

http://soc.microsemi.com/download/reg/default.aspx?f=LiberoSoC_PolarFire_v2_3_LIN

http://soc.microsemi.com/download/reg/default.aspx?f=LiberoSoC_PolarFire_v2_3_WIN

http://soc.microsemi.com/download/reg/default.aspx?f=LiberoSoC_PolarFire_v2_3_MEGA_VAULT

Date post:	19-Jul-2020
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