Linear Integrated Circuits Lab Manual

5/21/2018 Linear Integrated Circuits Lab Manual

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Linear and digital integrated circuits Lab

EC1262 LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

L T P C

0 0 3 2

1. Study of Basic Digital ICs. (Verication of truth table for AND !" #$!"

N!% N!"

NAND &' "S D )

*. I+,le+entation of Boolean unctions Adder- Subtractor circuits.

a) Code con/erters 0arity generator and ,arity checing #2cess 3 *s

Co+,le+ent Binary to 4ray code using suitable ICs.

b) #ncoders and Decoders.

5. Counters6 Design and i+,le+entation of 5 3 bit +odulo counters as

synchronous and

Asynchronous ty,es using ICs and s,ecic counter IC.

7 Shift "egisters6

Design and i+,le+entation of 5 3 bit shift registers in SIS! SI0! 0IS! 0I0!

+odes using suitable ICs.

8 9ulti,le2- De 3 +ulti,le26

Study of 561: ;61 +ulti,le2er and Study of 165: 16; de+ulti,le2er.

< %i+er IC a,,lication6

Study of N#-S# 777 ti+er in Astable 9onostable o,eration.

;. A,,lication of !, 3 A+,6

Sle= rate /erications in/erting and non 3 in/erting a+,lier

Adder co+,arator Integrater and Di>erentiator.

? Study of Analog to Digital Con/erter and Digital to Analog Con/erter6

Verication

of A-D con/ersion using dedicated ICs.


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Linear and digital integrated circuits Lab1@ Study of VC! and 0 ICs6

i. Voltage to freuency characteristics of N#- S# 788 IC.

ii. reuency +ulti,lication using N#-S# 787 0 IC.

LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB

MANUAL

PREPARED BY

R.PADMINI

ASST. PROF, EEE DEPT.


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DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

CONTENTS

SI.NO LIST OF EXPERIMENTS PAGE NO

1 Verification of Logic gates

2 Realization of Adder and Subtractor

a)Half/Full Adderb)Half/Full Subtractor

3 Code converters

a)C! to "#cess$3

b)"#cess$3 to C!

c)inar% to gra%

d)&ra% to inar%

' (arit% generators and (arit% cec*ers

+ ,ulti-le#er and !e .ulti-le#er

"ncoders and decoders

0 !esign and .-le.entation of

' bit As%ncronous counter

!esign and .-le.entation of

' bit s%ncronous counter

!esign and i.-le.entation of '$bit sift

register

14 !esign and testing of ,onostable and Astable

.ultivibrator using +++ ti.er C5

11 !esign of ntegrator and !ifferentiator circuit

using 6-$A.-s C 0'1


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12 Stud% of VC6 and (LL C7s

Expt.N!1

AIM!

8o stud% and verif% te trut table of Logic gates

APPARATUS RE"UIRED!

T#EORY!

Circuit tat ta*es te logical decision and te -rocess are called logic gates5 "ac gate as

one or .ore in-ut and onl% one out-ut5

6R9 A:! and :68 are basic gates5 :A:!9 :6R and ;$6R are *no


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OR GATE!

8e 6R gate -erfor.s a logical addition co..onl% *no


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AND GATE!

SYMBOL! PIN DIAGRAM!

OR GATE!


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NOT GATE!


X$OR GATE !

SYMBOL ! PIN DIAGRAM !


8/74


2$INPUT NAND GATE!


3$INPUT NAND GATE !


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NOR GATE!

R%&'(t!

8e different logic gates


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Expt.N!2

AIM!

8o design and construct alf adder9 full adder9 alf subtractor and full subtractor

circuits and verif% te trut table using ;6R and basic logic gates5

APPARATUS RE"UIRED!

S(.N. COMPONENT SPECIFICATION "TY.

15 A:! &A8" C 0'4 1

25 ;$6R &A8" C 0' 1

35 :68 &A8" C 0'4' 1

'5 6R &A8" C 0'32 1

35 C 8RA:"R =8 $ 1

'5 (A8CH C6R!S $ 23

T#EORY!

#ALF ADDER!

A alf adder as t


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FULL SUBTRACTOR!

8e full subtractor is a co.bination of ;$6R9 A:!9 6R9 :68 &ates5 n a full subtractor

te logic circuit sould ave tree in-uts and t


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LOGIC DIAGRAM!

FULL ADDER

FULL ADDER USING TO #ALF ADDER

TRUT# TABLE!

A B C CARRY SUM

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

0

0

1

0

1

1

1

0

1

1

0

1

0

0

1

)$M*p + SUM!

SUM - ABC / ABC / ABC / ABC

)$M*p + CARRY!


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CARRY - AB / BC / AC

LOGIC DIAGRAM!

#ALF SUBTRACTOR

TRUT# TABLE!

A B BORRO DIFFERENCE

0

0

1

1

0

1

0

1

0

1

0

0

0

1

1

0

)$M*p + DIFFERENCE!

DIFFERENCE - AB / AB

)$M*p + BORRO!


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BORRO - AB

LOGIC DIAGRAM!

FULL SUBTRACTOR

FULL SUBTRACTOR USING TO #ALF SUBTRACTOR!

TRUT# TABLE!

A B C BORRO DIFFERENCE

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

1

1

0

0

0

1

0

1

1

0

1

0

0

1

)$M*p + D++%%%!


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D++%%% - ABC / ABC / ABC / ABC

)$M*p + B4!

B4 - AB / BC / AC

PROCEDURE!

Verif% te gates

Connections


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Expt.N!3

AIM!

8o design and i.-le.ent '$bit

@i) inar% to gra% code converter

@ii) &ra% to binar% code converter

@iii) C! to e#cess$3 code converter

@iv) "#cess$3 to C! code converter

APPARATUS RE"UIRED!

Sl5:o5 C6,(6:":8 S("CFCA86: 8B515 ;$6R &A8" C 0' 1

25 A:! &A8" C 0'4 1

35 6R &A8" C 0'32 1

'5 :68 &A8" C 0'4' 1

+5 C 8RA:"R =8 $ 1

5 (A8CH C6R!S $ 3+

T#EORY!

8e availabilit% of large variet% of codes for te sa.e discrete ele.ents of infor.ation

results in te use of different codes b% different s%ste.s5 A conversion circuit .ust be inserted

bet


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A t


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)$M*p + G1!

)$M*p + G0!

TRUT# TABLE!


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B*7 p't G*7 8% 'tp't

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

00

0

0

0

1

1

1

1

1

1

11

0

0

0

01

1

1

1

0

0

0

0

1

1

11

0

0

1

10

0

1

1

0

0

1

1

0

0

11

0

1

0

10

1

0

1

0

1

0

1

0

1

01

0

0

0

00

0

0

0

1

1

1

1

1

1

11

0

0

0

01

1

1

1

1

1

1

1

0

0

00

0

0

1

11

1

0

0

0

0

1

1

1

1

00

0

1

1

00

1

1

0

0

1

1

0

0

1

10

LOGIC DIAGRAM!

GRAY CODE TO BINARY CON5ERTOR


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)$M*p + B3!

B3 - G3

)$M*p + B2!

)$M*p + B1!

)$M*p + B0!


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TRUT# TABLE!

G*7 C8% B*7 C8%

G3 G2 G1 G0 B3 B2 B1 B0

0

0

0

0

00

0

0

1

1

1

1

1

1

1

1

0

0

0

0

11

1

1

1

1

1

1

0

0

0

0

0

0

1

1

11

0

0

0

0

1

1

1

1

0

0

0

1

1

0

01

1

0

0

1

1

0

0

1

1

0

0

0

0

0

00

0

0

1

1

1

1

1

1

1

1

0

0

0

0

11

1

1

0

0

0

0

1

1

1

1

0

0

1

1

00

1

1

0

0

1

1

0

0

1

1

0

1

0

1

01

0

1

0

1

0

1

0

1

0

1


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LOGIC DIAGRAM!

BCD TO EXCESS$3 CON5ERTOR

)$M*p + E3!

E3 - B3 / B2 9B0 / B1:


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)$M*p + E2!

)$M*p + E1!


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)$M*p + E0!

TRUT# TABLE!

BCD p't Ex%&& 3 'tp't

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

1

1

1

1

1

x

x

x

x

x

x

0

1

1

1

1

0

0

0

0

1

x

x

x

x

x

x

1

0

0

1

1

0

0

1

1

0

x

x

x

x

x

x

1

0

1

0

1

0

1

0

1

0

x

x

x

x

x

x


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LOGIC DIAGRAM!

EXCESS$3 TO BCD CON5ERTER

)$M*p + A!

A - X1 X2 / X3 X; X1


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)$M*p + B!

)$M*p + C!


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)$M*p + D!

TRUT# TABLE!

Ex%&& 3 Ip't BCD O'tp't

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

1

1

11

1

0

1

1

1

1

0

0

00

1

1

0

0

1

1

0

0

11

0

1

0

1

0

1

0

1

01

0

0

0

0

0

0

0

0

01

1

0

0

0

0

1

1

1

10

0

0

0

1

1

0

0

1

10

0

0

1

0

1

0

1

0

10

1


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PROCEDURE!

Verif% te gates

Connections


29/74


Expt.N!;

AIM!

8o i.-le.ent te odd and even -arit% cec*ers using te logic gates and also to generate

te odd -arit% and even -arit% nu.bers using te generators5

APPARATUS RE"UIRED!

T


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E>% p*t7 % p*t7 ?%%*t

A

B

BA

C

C

D

D

P A R I T Y B I T7 4 L S 8 6 A

1

2

3

7 4 L S 8 6 A

4

5

6

7 4 L S 8 6 A

1 0

9

8

P%8'%!

15 8e circuit is i.-le.ented using logic gates5

25 8e in-uts are given as -er te trut table535 8e corres-onding out-uts are noted5

'5 8e teoretical and -ractical values


31/74


TRUT# TABLE!

n-ut Cec*er out-ut &enerator out-ut

A C ! odd even odd even4 4 4 4 4 1 44441 44444

4 4 1 1 4 44414 44411

4 4 1 4 1 4 44144 44141

4 4 1 1 4 1 44111 44114

4 1 4 4 1 4 41444 41441

4 1 4 1 4 1 41411 41414

4 1 1 4 4 1 41141 41144

4 1 1 1 1 4 41114 41111

1 4 4 4 1 4 14444 14441

1 4 4 1 4 1 14411 14414

1 4 1 4 4 1 14141 14144

1 4 1 1 1 4 14114 14111

1 1 4 4 4 1 11441 11444

1 1 4 1 1 4 11414 11411

1 1 1 4 1 4 11144 11141

1 1 1 1 4 1 11111 11114

RESULT!

8e odd and even -arit% cec*ers are i.-le.ented using te logic gates and te odd

-arit% and even -arit% nu.bers are generated using te corres-onding generators5


32/74


Expt.N!

AIM!

8o design and realize a '$bit s%nscronous counter

APPARATUS RE"UIRED!

C 0'49 C 0'09 C 0'449 C 0'32 etc5

P%8'%! $

15 Connections are .ade as -er circuit diagra.5

25 Cloc* -ulses are a--lied one b% one at te cloc* /( and te 6/( is

observed at A9 C for C 0'05

35 Verif% te 8rut table 5


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Binary 4-bit Synchronous Counter

T't< T*(% + ) +(p$+(p!

G = n14

4

1

1

4

1

4

1

n4

1

n


34/74


P 8*?*@!

4-bit Synchronous Counter Waveform Timing Diagram.

T#EORY!

t can be seen tat te e#ternal cloc* -ulses @-ulses to be counted) are fed directl% to eac J-K

flip-flopn te counter cain and tat bot te G and = in-uts are all tied togeter in toggle .ode9

but onl% in te first fli-$flo-9 fli-$flo- A @LS) are te% connected H&H9 logic 1 allo


35/74


8e G and = in-uts of fli-$flo- are connected to te out-ut of fli-$flo- A9 but te G and =

in-uts of fli-$flo-s C and ! are driven fro. A:! gates


36/74


8o design and realize a '$bit As%nscronous counter

APPARATUS RE"UIRED!

Sl5:o5 C6,(6:":8 S("CFCA86: 8B5

15 G= FL( FL6( C 0'0 225 :A:! &A8" C 0'44 1

35 C 8RA:"R =8 $ 1

'5 (A8CH C6R!S $ 34

T#EORY!

A counter is a register ca-able of counting nu.ber of cloc* -ulse arriving at its cloc* in-ut5

Counter re-resents te nu.ber of cloc* -ulses arrived5 A s-ecified seEuence of states a--ears as counterout-ut5 8is is te .ain difference bet


37/74


LOGIC DIAGRAM FOR ; BIT RIPPLE COUNTER!


38/74


TRUT# TABLE!

CL) "A "B "C "D

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 0

; 0 0 1 0

1 0 1 0

6 0 1 1 0

1 1 1 0

0 0 0 1 1 0 0 1

10 0 1 0 1

11 1 1 0 1

12 0 0 1 1

13 1 0 1 1

1; 0 1 1 1

1 1 1 1 1

RESULT!

8e '$bit As%ncronous counter


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AIM!

A@!

8o realize te "ncoder and !ecoder circuit using logic gates and to verif% te trut table5

App**t'& R%'%8!

ENCODER!9!3:

T


40/74


B

A

C

D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7

7 4 L S 3 2

1 3

1 2

1 1

7 4 L S 3 2

1 0

9

8

7 4 L S 3 2

1 3

1 2

1 1

7 4 L S 3 2

4

5

6

7 4 L S 3 2

1

2

3

7 4 L S 3 2

1

2

3

7 4 L S 3 2

4

5

6

7 4 L S 3 2

1 0

9

8

7 4 L S 3 2

1

2

3

DECODER !9 2!;:

Tn7 in-ut lines

to a .a#i.u. of 2nuniEue out-ut lines5 t -erfor.s te reverse o-eration of te encoder5 f te

n$bit decoded infor.ation as unused or don7t$care co.binations9 te decoder out-ut


41/74


YD IN

D 0

D 1

D 2

D 3

7 4 L S 1 1

1 0

89

1 1

7 4 L S 1 1

3

64

5

7 4 L S 0 4

1

2

7 4 L S 1 1

1

1 22

1 3

7 4 L S 1 1

1

1 22

1 3

7 4 L S 0 4

1

2

P%8'%!

15 8e "ncoder and !ecoder circuit is designed and te oolean function is found out525 8e Lo< level in-ut is &rounded and te H&H level in-ut is connected to te +V

su--l%5

35 Connections are .ade as -er te circuit given5'5 6bserve te out-ut for various co.binations of in-uts5

+5 8us te trut table is verified5

R%&'(t!

8us te "ncoder and !ecoder circuit


42/74


Expt.N!

DESIGN AND IMPLEMENTATION OF S#IFT REGISTER

AIM!

8o design and i.-le.ent

@i) Serial in serial out

@ii) Serial in -arallel out

@iii) (arallel in serial out

@iv) (arallel in -arallel out

APPARATUS RE"UIRED!

Sl5:o5 C6,(6:":8 S("CFCA86: 8B5

15 ! FL( FL6( C 0'0' 225 6R &A8" C 0'32 1

35 C 8RA:"R =8 $ 1

'5 (A8CH C6R!S $ 3+

T#EORY!

A register is ca-able of sifting its binar% infor.ation in one or bot directions is *no


43/74


be 14415 8e least significant bit of te data as to be sifted troug te register fro. FF4 toFF35

S%*( I $ P**((%( O't S


44/74


LOGIC DIAGRAM!

SERIAL IN SERIAL OUT!

TRUT# TABLE!

CL)

S%*( S%*( 't

1 1 0

2 0 0

3 0 0

; 1 1

X 0

6 X 0

X 1

LOGIC DIAGRAM!

SERIAL IN PARALLEL OUT!


45/74


TRUT# TABLE!

CL) DATA

OUTPUT

"A "B "C "D

1 1 1 0 0 0

2 0 0 1 0 0

3 0 0 0 1 1

; 1 1 0 0 1

LOGIC DIAGRAM!

PARALLEL IN SERIAL OUT!

TRUT# TABLE!

CL) "3 "2 "1 "0 OHP

0 1 0 0 1 1

1 0 0 0 0 0

2 0 0 0 0 0

3 0 0 0 0 1


46/74


LOGIC DIAGRAM!

PARALLEL IN PARALLEL OUT!

TRUT# TABLE!

CL)

DATA INPUT OUTPUT

DA DB DC DD "A "B "C "D

1 1 0 0 1 1 0 0 1

2 1 0 1 0 1 0 1 0

PROCEDURE!

@i) Verif% te gates5

@ii) Connections are given as -er circuit diagra.5

@iii) Logical in-uts are given as -er circuit diagra.5

@iv) 6bserve te out-ut and verif% te trut table5

RESULT!

8e Sift Registers


47/74


"#-t5:oD

MULTIPLEXER AND DEMULTIPLEXER

AIM!8o construct and verif% te trut table of .ulti-le#er and

de.ulti-le#er circuits

APPARATUS RE"UIRED!

S.NOP*t'(* N*@% SPECIFICATION "UANTITY

1

2

3

D?t*( IC t*% =t

IC;0;, IC;32 IC;11

C%t? %&

$$$$

$$$$

1

1 %**t!

8eoritical (ractical

6: ti.e

6FF ti.e

Q !ut% c%cle


59/74


FreEuenc%

R"SML8D

8us .ultivibrators


60/74


05Connecting


61/74


n tis circuit


62/74


D++%%t*t!

8e circuit to te rigt so


63/74


freEuenc% gain is still set b% Rfand C9 as before5 8e cutoff freEuenc%9


64/74


P%8'%!

a) (ut te o- a.- in te breadboard and connect Vccand $Vccto te ci-5 Set te

.agnitude of Vccto 12 volts @%ou


65/74


ResultD

8e

"#-t5:o 12

STUDY OF 5CO AND PLL

It8't t PLL P


66/74


P


67/74


causes variation in te dc voltage to te VC65 Jitin a ca-ture$and$oc* freEuenc% range9 te dcvoltage


68/74


5(t*?% t((%8 &((*t

n .ost cases9 te freEuenc% of an oscillator is deter.ined b% te ti.e constant RC5 Ho


69/74


8e freEuenc% of te out-ut


70/74


MULTI5IBRATOR USING TIMER

AIMD

8o design and construct te astable and .ono stable .ultivibrator using +++ ti.er5 !ra*t!A .onostable .ultivibrator is a -ulse$generating circuit aving one stable and one Euasi$stable

state5 Since tere is onl% one stable state9 te circuit is *no.onostable .ultivibrator75 8e

duration of te out-ut -ulse is deter.ined b% te RC net*t!

8eoritical (ractical

6: ti.e

6FF ti.e

Q !ut% c%cle

FreEuenc%

RESULT!

8e astable and .ono stable .ultivibrator using +++ ti.er are designed and te

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Linear Integrated Circuits Lab Manual

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