76 Sudhanshi Shakya, Owais Shah International Journal of Computer & Mathematical Sciences IJCMS ISSN 2347 – 8527 Volume 4, Issue 7 July 2015 Low Power 5T SRAM Design in 90NM Technology Sudhans hi Shakya M.Tech.(VLSI) Department of Electronics & Comm. Engg. Noida International University G.B.Nagar (U.P.) India. Owais Shah (Project Guide) Department of Electronics & Comm. Engg. Noida International University G.B.Nagar (U.P.) India. Abstract—Due to the increased demand of SRAM with largeuse of SRAM in System On-Chip, the power consumption has become a tough challenge in CMOS technology. The oxide thickness also affects the chip design process. Speed of SRAM and Area overhead are also taken care of for designing a chip. This article represents the simulation of 6T SRAM; Asymmetric Dynamic Threshold Gated SRAM; Asymmetric High threshold 10T SRAM; 5T SRAMusing low power reduction techniques. All the simulations have been carried out on 90nm at Tanner EDA tool. In this article, we will modify 5T SRAM cell with the use of high threshold PMOS Devices that results in decrease in the leakage that reduces power dissipation. The circuit designing and simulation is done on the Tanner tool, Schematic of the SRAM cell is designed on the S-Edit and net list simulation done by using T-spice and waveforms are analyzed through the W-edit. Keywords—Low Power; 5T SRAM Cell; 6T SRAM; Cell delay; Cell leakage; Cell area; Power consumption I. INTRODUCTION Static random access memory (SRAM), the most widely used embedded memory, typically occupies the largest portion of SoC die area, and often dominates the total chip power. In order to maintain performance, however, this has required a corresponding reduction in the transistor oxide thickness to provide sufficient current drive at the reduced supply voltages. To further reduce the leakage current,we can use high threshold transistors. The transistors have been lowered which also contributes to reduced leakage currents and hence reduces the power consumption. The low power reduction techniques based on the dependencies of the tunneling currents on the terminal voltages, the gate oxide thickness, and the type of the transistor. Various efficient techniques which gives overall best performance over existing SRAM design approaches that allow the analysis and simulations of different parameters at 90nm technology successfully on the basis of the power dissipation, speed and area efficiency of the circuit. II. LITERATURE REVIEW OF DIFFERENT SRAM CELLS A. 6T SRAM CELL Fig.1. Schematic Diagram of 6T SRAM The schematic diagram of 6T SRAM cell is shown in Fig.1. In this technique, access to the cell is enabled by the word line (WL) which controls the two access transistors, in turn, control whether the cell should be connected to the bit lines: BL and BLB. They are used to transfer data for both read and write operations. While it's not strictly necessary to have two bit lines, both the signal and its inverse are typically provided since it improves noise margins. During read, the WL voltage VWL is raised, and the memory cell discharges either BL (bit line true) or BLB (bit line complement), depending on the stored data on nodes Q and BQ. A sense amplifier converts the differential signal to a logic- level output. Then, at the end of the read cycle, the BLs returns to the positive supply rail. During write, VWL is raised and the BLs are forced to either VDD (depending on the data), overpowering the contents of the memory cell. During hold, VWL is held low and the BLs are left floating or driven to VDD. Each bit in an SRAM is stored on four transistors that form two cross-coupled.
Transcript
76 Sudhanshi Shakya, Owais Shah
International Journal of Computer & Mathematical Sciences
IJCMS
ISSN 2347 – 8527
Volume 4, Issue 7
July 2015
Low Power 5T SRAM Design in 90NM Technology
Sudhanshi Shakya M.Tech.(VLSI)
Department of Electronics & Comm. Engg. Noida International University
G.B.Nagar (U.P.) India.
Owais Shah (Project Guide)
Department of Electronics & Comm. Engg. Noida International University
G.B.Nagar (U.P.) India.
Abstract—Due to the increased demand of SRAM with
largeuse of SRAM in System On-Chip, the power
consumption has become a tough challenge in CMOS
technology. The oxide thickness also affects the chip
design process. Speed of SRAM and Area overhead are
also taken care of for designing a chip. This article
represents the simulation of 6T SRAM; Asymmetric
Dynamic Threshold Gated SRAM; Asymmetric High
threshold 10T SRAM; 5T SRAMusing low power
reduction techniques. All the simulations have been
carried out on 90nm at Tanner EDA tool. In this article,
we will modify 5T SRAM cell with the use of high
threshold PMOS Devices that results in decrease in the
leakage that reduces power dissipation. The circuit
designing and simulation is done on the Tanner tool,
Schematic of the SRAM cell is designed on the S-Edit and
net list simulation done by using T-spice and waveforms
are analyzed through the W-edit.
Keywords—Low Power; 5T SRAM Cell; 6T SRAM; Cell
delay; Cell leakage; Cell area; Power consumption
I. INTRODUCTION Static random access memory (SRAM), the most widely used embedded memory, typically occupies the largest portion of SoC die area, and often dominates the total chip power. In order to maintain performance, however, this has required a corresponding reduction in the transistor oxide thickness to provide sufficient current drive at the reduced supply voltages. To further reduce the leakage current,we can use high threshold transistors. The transistors have been lowered which also contributes to reduced leakage currents and hence reduces the power consumption. The low power reduction techniques based on the dependencies of the tunneling currents on the terminal voltages, the gate oxide thickness, and the type of the transistor. Various efficient techniques which gives overall best performance over existing SRAM design approaches that allow the analysis and simulations of different parameters at 90nm technology successfully on the basis of the power dissipation, speed and area efficiency of the circuit.
II. LITERATURE REVIEW OF DIFFERENT
SRAM CELLS A. 6T SRAM CELL
Fig.1. Schematic Diagram of 6T SRAM
The schematic diagram of 6T SRAM cell is shown in Fig.1. In this technique, access to the cell is enabled by the word line (WL) which controls the two access transistors, in turn, control whether the cell should be connected to the bit lines: BL and BLB. They are used to transfer data for both read and write operations. While it's not strictly necessary to have two bit lines, both the signal and its inverse are typically provided since it improves noise margins. During read, the WL voltage VWL is raised, and the memory cell discharges either BL (bit line true) or BLB (bit line complement), depending on the stored data on nodes Q and BQ. A sense amplifier converts the differential signal to a logic-level output. Then, at the end of the read cycle, the BLs returns to the positive supply rail. During write, VWL is raised and the BLs are forced to either VDD (depending on the data), overpowering the contents of the memory cell. During hold, VWL is held low and the BLs are left floating or driven to VDD. Each bit in an SRAM is stored on four transistors that form two cross-coupled.
77 Sudhanshi Shakya, Owais Shah
International Journal of Computer & Mathematical Sciences
IJCMS
ISSN 2347 – 8527
Volume 4, Issue 7
July 2015
B.Asymmetric Dynamic Threshold Gated SRAM
Fig.2. Schematic Diagram of Asymmetric Dynamic
Threshold Gated SRAM In this technique, during the Read operation, we raise the WL at logic “1”. If logic “0” exists on the internal node „Q‟, a logic “1” exists on the complimentary node „QB‟. The threshold voltages of both the access transistors NMOS3 and NMOS4 are lowered since the bodies are high.As a result, the conductance of transistors NMOS3 and NMOS4 will be increased and the BL will be discharged faster than in the conventional case. The sense amplifier will sense quickly which transistor is discharging. Hence the read time will be reduced[4]. During the write “1” operation, we set logic “1” at BL and logic “0”at BLB. When we raise WL at logic “1”,NMOS3 ,NMOS4,NMOS5, PMOS1,NMOS2 will operate at reduced threshold voltage Vt. In hold mode, WL will be set to logic “0”. Hence the DTNMOS sleep transistor(NMOS5) will be OFF. So it will reduce the leakage current due to stacking effect. B. Asymmetric High threshold 10T SRAM
Fig.3. Schematic Diagram of Asymmetric High
threshold 10T SRAM
Figure 3 shows the schematic diagram of asymmetric10T SRAM cell. In this technique, we propose an asymmetricSRAM cells that use a mix of regular- and high-Vttransistors[2][10]. C. 5T SRAM
Fig.4. Schematic Diagram of 5T SRAM
In this technique, during idle mode of cell (when read and write operation don‟t perform on cell) the feedback cutting transistor (PMOS1) is ON and N node pulled to VDD by this transistor. When ‟1‟ stored in cell, NMOS1 and PMOS3 are ON and there is positive feedback between QB node and Q node, therefore QB node pulled to VDD by PMOS3 and Q node pulled to GND by NMOS1. When ‟0‟ stored in cell,PMOS2 is ON and since N node maintained at VDD by PMOS1,the Q pulled to VDD, also PMOS3 and NMOS1 are OFF[1].
III. PROPOSED DESIGN In this design, we are proposing the 5T SRAM cell with the mix of regular and high threshold voltages.
Fig.5. Schematic Diagram of 5T Modified SRAM In this technique, we start by reviewing the conventional regular-Vttransistor cell and focus on where leakage power is dissipated. We then explain how we can reduce leakage power with no or little impact on accesslatency by selectively “weakening”
78 Sudhanshi Shakya, Owais Shah
International Journal of Computer & Mathematical Sciences
IJCMS
ISSN 2347 – 8527
Volume 4, Issue 7
July 2015
some of the transistors (i.e., replacing some transistors with high-Vtones) [11]. One way of reducing leakage power would be to use an high-Vtcell where 2 transistors are replaced with high-Vtones. High-Vttransistors are not as strong and hence require a lot more time to discharge the relatively large capacitance of the bit lines. Following are the parameters that needs to be defined are- A. Cell Area The 6T SRAM cell has the conventional layout topology and is as compact as possible. The 6T SRAM cell requires 6 transistors, whereas 5T SRAM cell requires 5 transistors.These numbers take into account the potential area reduction obtained by sharing with neighboring cells. Therefore the new cell size is comparatively smaller than a conventional six-transistor cell using same design rules. B. Cell Delay The propagation delay [3] timesPHL and
PLHdetermine the input-to-outputsignal delay during the high-to-low and low-to-high transitions of the output, respectively.
By definition, PHL is the time delay between the V50% transition of the rising input voltage and the V50% transition of the falling output voltage.
Similarly, PLHis defined as the time delay between the V50% transition of the falling input voltage and the V50% transition of the rising output voltage. To simplify the analysis and the derivation of delay expressions, the input voltage waveform is usually assumed to be an ideal step pulse with zero rise and
fall times. Under this assumption, PHL becomes the time required for the output voltage to fall from
VOH to the V50%level, and PLHbecomes the time required for the output voltage to rise from VOLto the V50% level. The voltage point V50% is defined as follows- V50% = VOL + 1/2(VOH-VOL) = 1/2(VOH+VOL) (1)
Fig. 6.Input and output voltage waveforms of a
typical inverter, and the definitions of propagation delay times. The input voltage waveform is idealized
as a step pulse for simplicity.
Thus, the propagation delay timesPHL and
PLHare found:
PHL = t1 – t0, PLH= t3 – t2.
The average propagation delay pof the inverter characterizes the average time required for the input signal to propagate through the inverter-
p= ½ (PHL +PLH) (2) The delay will be calculated [7] by using the basic idea which is shown in Fig. 6. Delay of the cell depends on the consumption of time between the cells from input (BL) to output [8]. Comparison of the cell delay between 5T & 6T shows in Table 1.
Table 1.Comparison between 5T Modified& 6T cell delay
No. Parameters Delay of
5T
Modified
Delay
of 6T
Better
Performance
1. Delay at Q 16.42ns 15.51ns 6T
2. Delay at
QB
14.60ns 16.52ns 5T Modified
C. Power Consumption Power consumption in SRAMs, for a normal read cycle, is given by- P = Vdd× Idd (3)
Idd= (m Iactt + CPT VINT )f + IDCP (4) where, Vdd is an external supply voltage, Iddis the total current, Iact is the effective active current, VINT is an internal supply voltage, CPTis the total capacitance of the peripheral circuits, IDCPis the total static current, m is the number of columns and f is the operation frequency. This equation is based on the fact that in SRAMs, holding current is very small [6] and decoder charging current is negligible because of NAND decoders [6] [9]. To reduce the total power consumption, active current should be reduced as it dominates. Hence , we are using the TANNER EDA Tool here, so we can directly calculate the power consumed of the circuit.
Table 2.Comparison between Power Consumption by different SRAM Cells
SRAM POWER
CALCULATED(Watts) (at VDD=5V)
% REDUCTION
IN 5T MODIFIED
6T 2.171001e-004 70.179
5T 7.232533e-005 10.4863
5T Modified 6.474102e-005 -
Dynamic
Gated
1.008130e-004 35.78
Asymmetric
High
Threshold
1.802572e-004 64.084
79 Sudhanshi Shakya, Owais Shah
International Journal of Computer & Mathematical Sciences
IJCMS
ISSN 2347 – 8527
Volume 4, Issue 7
July 2015
Hence, we can conclude from the Table.2. that the maximum power is reduced in case of 5T Modified SRAM Cell in comparison to other SRAM cells and the area overhead is also reduced due to 5T structure except 5T cell.
IV. SIMULATION RESULTS Figure 7 to 8 shows the output waveforms of different SRAM cell structures at 90nm technology.
Fig.7. Output Waveform of 6T SRAM
Fig.8. Output Waveform of 5T Modified SRAM
V. CONCLUSION With the aim of achieving a high density and low power consumption by memory cell, we developed a 5T SRAM cell with high thresholds. The key observations behind our design are that the power is reduced by reducing the leakage current by using high threshold transistors that will lower or weaken the bodies of the transistors. In same design rules proposed cell area is comparatively smaller than 6T SRAM cell with speed improvement. The power consumption of thenew cell is 70.18% lesser than 6T SRAM cell.
Acknowledgments. This work was supported by Noida International University,G.B.Nagar(U.P.). The author would also like to thank to Assistant Professor Owais Shah for their enlightening technical advice. REFERENCES 1. S.Akashe, S.Bhushan, S.Sharma ,“High Density and
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