ISSN 2322-0929

Vol.03, Issue.06,

August-2015,

Pages:0785-0790

www.ijvdcs.org

Copyright @ 2015 IJVDCS. All rights reserved.

Low Power Area Efficient ROM Embedded SRAM Cache M. SWATHI

1, D. NAGESHWAR RAO

2, D. SUDHAKAR

3

1PG Scholar, Dept of ECE, TKR College of Engineering & Technology, TS, India, E-mail: swathi.swathi349@gmail.com.

2Professor & HOD, Dept of ECE, TKR College of Engineering & Technology, TS, India.

3Associate Professor, Dept of ECE, TKR College of Engineering & Technology, TS, India.

Abstract: In a VLSI design contains area, power, speed, system performance all these are the features along with there are many

important applications, such as math function evaluation, digital signal processing, and built in self-test, whose implementations

can be faster and simpler if it have large on-chip tables stored as read-only memories (ROMs). But on-chip ROM’S are limited

in size in order ti increase ROM’S memory size, the conventional de fact standard 6T and 8T static random access memory

(SRAM) bit cell can embed ROM data without area overhead or performance degradation on the bit cells. Just by adding an

extra word line (WL) and connecting the WL to selected access transistor of the bit cell (based on whether a 0 or 1 is to be stored

as ROM data in that location). The bit cell can work both in the SRAM mode and in the ROM mode. In standard 6T&8T SRAM

having mainly a drawback i.e data lost whenever power not present, to overcome these problems & increase performance we

deal with ROM-embedded SRAM cache. In the proposed ROM-embedded SRAM (R-SRAM), during SRAM operations, ROM

data is not available. To retrieve the ROM data, special write steps associated with proper via connections load ROM data into

the SRAM array. The ROM data is read by conventional load instructions with unique virtual address space assigned to the data.

It allows the ROM-embedded cache (R-cache) to bypass tag arrays and translation look-aside buffers, leading to fast ROM

operations. Here example applications to illustrate how the R-cache can lead to low-cost logic testing and faster evaluation of

mathematical functions.

Keywords: Cache Design, Random Access Memory (RAM), Read-Only Memory (ROM), ROM-Embedded Static RAM

(SRAM), SRAM Design.

I. INTRODUCTION

CMOS devices have been scaled down for about 40 years

to achieve better performance, higher speed, Area reduction

and Low power consumption. Due to high speed and low

power and area efficient SRAM based memories are used

compared to DRAM cells. Although technology scaling has

led to integration of large number of transistors into a chip,

large on-chip read only memory (ROM) is not suitable choice

for designer. Most of the designers choose a suitable size of

on chip Read Only Memories (ROM). Large dedicated

ROM‟s increase Area, Cost and Power, but also impair chip

floor plan and results interconnect delay. Let us consider a

few examples where on-chip ROMs can be effectively used

as “accelerators.” Coefficients for fast Fourier transform

library are stored in external nonvolatile memory instead of

on-chip ROMs. Coefficients for fast Fourier transform library

are stored in external nonvolatile memory instead of on-chip

ROMs. Note that on-chip ROMs can significantly improve

the performance of such applications. The interweaver for

Turbo codes is designed by a dedicated logic to generate

addresses on the fly, instead of dedicated on-chip ROMs.

Pseudo-random-pattern generators (PRPGs) produce test data

to avoid storing test data in on-chip ROMs for built-in self-

test (BIST). Note that on-chip ROMs can significantly

improve the performance of such applications. For evaluation

of math functions, math libraries are used. Such libraries are

usually stored off-chip, leading to degradation in

performance. The speed gap between a processor and an

external memory grows with every technology generation,

resulting in major roadblocks to high-performance system

design. In this paper, we organized as follows. Section 2

deals with existing method i.e. 6 Transistor SRAM cell

design. 6 Transistor SRAM cell Write operation and Read

operation. Section 3 describes the proposed ROM Embedded

SRAM cell operation, i.e. SRAM mode operation and ROM

mode operation based on word line connection. Section 4

describes 8 Transistor RSARM cell how to storing “0” and

“1”. Section 5 describes Simulation results of 6 Transistor

SRAM cell and 6 Transistor RSRAM cell. Section 6

describes the Conclusion of the project.

II. EXSISTING METHOD

A. Conventional 6t SRAM Cell

The most commonly used SRAM type is the 6T SRAM

which offers better electrical performances from all aspects

(speed, noise immunity, standby current). The smallest 6T

SRAM cell that has been fabricated till today has an area of

0.08μm2 and it was fabricated in the 22nm process using

immersion and EUV lithography. Conventional SRAM cell is

implements with six transistors. In these SRAM cell two

M. SWATHI, D. NAGESHWAR RAO, D. SUDHAKAR

International Journal of VLSI System Design and Communication Systems

Volume.03, IssueNo.06, August-2015, Pages: 0785-0790

cross coupled inverter are used to store one bit of data. Word

line is used to enabling the process of conventional SRAM

cell and two access transistors are used to perform read and

write operations. An SRAM cell is the key SRAM

component storing binary information. A typical SRAM cell

uses two cross-coupled inverters forming a latch and access

transistors. Access transistors enable access to the cell during

read and write operation. An SRAM cell is designed to

provide non-destructive read access, write capability and data

storage (or data retention) for as long as cell is powered. In

general, the cell design must strike a balance between cell

area, robustness, speed, leakage and yield. Power reduction is

one of the most important design objectives. However, the

power cannot be reduced indefinitely without compromising

the other parameters. Low-power can compromise the cell

area also speed of operation. The mainstream six-transistor

(6T) CMOS SRAM cell is shown in Fig.1, four transistors

(Q1−Q4) comprise cross-coupled CMOS inverters and two

NMOS transistors Q5 and Q6 provide read and write access

to the cell. A 6T CMOS SRAM cell is the most popular

SRAM cell due to its superior robustness, low power and

low-voltage operation connected to the input of inverter

Q2−Q4 (Figure -1). Sizing of Q1 and Q5 should ensure that

inverter Q2−Q4 do not switch causing a destructive read.

B. Write Operation of Conventional 6t SRAM Cell

Fig.1. Conventional 6T SRAM cell.

Fig. 1 describes the schematic of conventional 6T SRAM

bit cell. Note that the thin-cell layout topology is a de facto

standard in the industry because of its compact area, better

tolerance to variability, and high performance. Also, note that

the contact for WL signals is shared by two neighboring

SRAM bit cells. For each row, there is one metal line of WL.

Hence, gate signals of all the access transistors in the same

row are turned on and off simultaneously.

C. Read Operations of Conventional 6t SRAM Cell

In this read operation, the bit lines are pre-charged to

VDD. The read operation is initiated by enabling the word

line (WL) and connecting the pre-charged bit lines, BL and

BLB, to the internal nodes of the cell. The bit line voltage

VBL remains at the pre-charge level. The complementary bit

line voltage VBLB is discharged through transistors Q1 and

Q5 connected in series. Effectively, transistors Q1 and Q5

form a voltage divider whose output is now no longer at zero

volts. During write operation one of the bit lines; BL is

driven from pre-charged value (VDD) to the ground potential

by a write driver through transistor Q6. If transistors Q4 and

Q6 are properly sized, then the cell is flipped and its data is

effectively overwritten. A statistical measure of SRAM cell

write ability is defined as write margin. Write margin is

defined as the minimum bit line voltage required flipping the

state of an SRAM cell. The write margin value and variation

is a function of the cell design, SRAM array size and process

variation. A cell is considered not writeable if the worst-case

write margin becomes lower than the ground potential.

Note that the write operation is applied to the node

storing a “1”. This is necessitated by the non-destructive read

constraint that ensures that a “0” node does not exceed the

switching threshold of inverter Q2−Q4. The function of the

pull-up transistors is only to maintain the high level on the

“1” storage node and prevent its discharge by the off-state

leakage current of the driver transistor during data retention

and to provide the low-to-high transition during overwriting.

Fig.2.Schematic of 6 Transistor ROM Embedded SRAM

cell.

III. PROPOSED METHOD

A. Rom Embedded 6t SRAM Cell The proposed ROM embedded SRAM cell is implement

with four NMOS transistors and two PMOS transistors and

two word lines and bit lines. Proposed ROM Embedded

SRAM cell working in two modes, i.e. SRAM mode

operation and ROM mode operation existing 6T SRAM cell

consumes more power and also volatile property i.e. when

the power is off total data will be erase. These disadvantages

overcome by the proposed ROM Embedded SRAM cell.

ROM mode, to retrieve ROM data from R-SRAM, we

perform following two steps shown in below:

Write '1' to all the bit cells with Word Line1 and Word

Line2 are turned on (BL=1, BLB=0,

WL1=onWL2=on).

Write '0' to all the bit cells with Word Line1 turned off

and WL2 turned on (BL=0, BLB=1, WL1=OFF,

WL2=ON).

Low Power Area Efficient ROM Embedded SRAM Cache

International Journal of VLSI System Design and Communication Systems

Volume.03, IssueNo.06, August-2015, Pages: 0785-0790

The schematic of 6 Transistor ROM Embedded SRAM cell

is shown in Fig. 2. Compared to conventional 6T SRAMs, 6T

R-SRAM bit cells have an extra WL. Depending on the ROM

data to be embedded into the R-SRAM, the gate of an access

transistor is connected to WL1 or WL2. Since the R-SRAM

is based on the thin-cell layout topology of the SRAM, two

neighboring access transistors should be connected to the

same WL, as shown in Fig. 2. If an R-SRAM bit cell stores

“0” (“1”), the left access transistor (AXL) is connected to

WL2 (WL1). The right access transistor (AXR) of an R-

SRAM bit cell follows the connectivity of the AXL of the

right-side neighboring bit cell. Connectivity of the AXR of

the end cell, which resides at the end of a row, is determined

by the connectivity of the AXL of the end cell. 6 Transistor

ROM Embedded SRAM cell working in two modes, i.e.

Normal SRAM mode and ROM mode in the proposed ROM

Embedded SRAM cell, during the normal SRAM mode, two

WLs are always turned on and off at the same time so as to

operate conventional 6T SRAM functions. During Normal

SRAM mode, ROM data is not available. During the ROM

mode operation, SRAM data is temporally stored in buffer

after Step I Row stores all ones, i.e. “1111”.

That means each bit cell stores “1”, after first step left

access transistors of cell 1 and cell 2 connected to word line

2, that means in step 2 cell 1 and cell 2 storing “0” value.

After the above two steps, we can read retrieved ROM data

from R-SRAM bit cells using the conventional SRAM read

operation (WL1 and WL2 are turned on). Note that the ROM

data to be embedded is determined by the connectivity of the

access transistors, as shown in Fig. 2. The proposed ROM

embedded SRAM cell increase the Speed and Performance

without Area penalty. Note that two write steps of ROM data

retrieval destroy the corresponding SRAM content. Hence,

before ROM data retrieval, SRAM data of the corresponding

block is written into a buffer (that takes an area of a block).

The proposed 6 Transistor SRAM cell have two write

operations in ROM mode operation, for these two steps write

stability problem occur. In step2 of ROM mode write

stability problem occur, because two neighboring cells

storing different data. i.e it acts like a five transistor SRAM

cell.

IV. 8T ROM EMBEDDED SRAM DESIGN

The proposed SRAM cell implement with six NMOS

transistors and two PMOS transistor. 6 Transistor ROM

embedded SRAM cell having the write stability problem, this

disadvantage overcome by the 8 Transistor SRAM cell. The

8T SRAM cells isolate read and write operations using two

additional transistors. The read and the write operations can

be separately optimized for improved read and write

stabilities, and the 8T SRAM is suitable for process variation

tolerance and low-voltage operation in scaled technologies.

Below figure shows the Schematic of 8 Transistor ROM

embedded SRAM cell. 8 Transistor RSRAM cell has two

separate word lines for read and write operations. RCON is

the ROM control signal, Transistor RD of the 8T RSRAM

can be connected to either ground or ROM control signal. In

standard 8T SRAM mode operation Transistor RD is always

connected to ground, during normal SRAM operation of 8T

RSRAM ROM control signal (RCON) is connected to

ground. Two additional transistors in 8T RSRAM layout

create enough routing space for RCON metal layer. To

perform ROM data retrieval from the 8T R-SRAM, we write

“0”s to all bit cells, similar to the 6T R-SRAM. Then, all RD

transistors of the 8T R-SRAM are turned on when we read

ROM data after write “0”s, RCON is driven by the supply

voltage. If RD is connected to the ground, we can read “0”

through read bit line (RBL) [Fig. 3] on the other hand, if RD

is connected to RCON (supply voltage), the RBL maintains

the pre-charged voltage level, and we can read “1” [Fig. 3].

Compared to the two write steps of the 6T R-SRAM (during

the ROM data retrieval), the 8T RSRAM requires only one

write step.

Fig.3. Schematic of 8 Transistor ROM Embedded SRAM

storing “0”.

Fig.4. Schematic of 8 Transistor ROM Embedded SRAM

storing “1”.

M. SWATHI, D. NAGESHWAR RAO, D. SUDHAKAR

International Journal of VLSI System Design and Communication Systems

Volume.03, IssueNo.06, August-2015, Pages: 0785-0790

V. SIMULATION RESULTS

Simulation results of this paper is shown in bellow Figs.5

to 17.

Fig.5. Inverter Symbol.

Fig.6. Inverter Schematic.

Fig.7. Inverter Output.

Fig.8. 6T-SRAM.

Fig.9. 6T-SRAM Symbol.

Fig.10.6T –SRAM Output.

Low Power Area Efficient ROM Embedded SRAM Cache

International Journal of VLSI System Design and Communication Systems

Volume.03, IssueNo.06, August-2015, Pages: 0785-0790

Fig.11. 6T R-SRAM.

Fig.12. 6T R-SRAM WRITES’1’.

Fig.13. R-SRAM write’1’ output.

Fig.14. 6T R-SRAM WRITE’0’.

Fig.15. 6T R-SRAM WRITE’0’ output.

Fig.16. ROM data storing “101”.

M. SWATHI, D. NAGESHWAR RAO, D. SUDHAKAR

International Journal of VLSI System Design and Communication Systems

Volume.03, IssueNo.06, August-2015, Pages: 0785-0790

Fig.17. 8T R-SRAM.

VI. CONCLUSION

A new R-cache architecture, in the R-cache does not

include area/performance penalty on the SRAM bit cells. The

R-cache for the 6T configuration uses one additional WL,

and the SRAM access transistors are connected to one of the

two WLs depending on the data to be stored in the ROM. For

the 8TR-SRAM configuration, the R-cache connects the read

transistor to either ground or RCON, depending on the data

to be stored in the ROM. The analyzed both SRAM and

ROM stability in scaled technologies and presented

techniques to improve the yield. It considered possible

applications of the R-cache. To improve evaluation

time/accuracy of complex math functions, the R-cache can

store large table’s on-chip (while still being able to perform

standard SRAM operations). The size of the tables is limited

only by the size of on-chip caches. The proposed

methodology improved evaluation latency for double-

precision elementary mathematical functions by 30%

compared to conventional evaluation techniques.

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Author’s Profile:

M. SWATHI, PG Scholar, Dept of ECE,

TKR College of Engineering &

Technology, TS, India,

E-mail: swathi.swathi349@gmail.com.

D. NAGESHWAR RAO, Professor & HOD, Dept of ECE, TKR

College of Engineering & Technology, TS, India.

D. SUDHAKAR, Associate Professor, Dept of ECE, TKR

College of Engineering & Technology, TS, India.