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ASIC Tutorial Intro.ASIC Tutorial Intro.11Low Power Design for Low Power Design for SoCsSoCs ©©M.J. Irwin, PSU, 1999M.J. Irwin, PSU, 1999

Low Power Design for

Systems on a Chip

Mary Jane IrwinDept of CSE

Penn State University (www.cse.psu.edu/~mji)

ASIC Tutorial Intro.ASIC Tutorial Intro.22Low Power Design for Low Power Design for SoCsSoCs ©©M.J. Irwin, PSU, 1999M.J. Irwin, PSU, 1999

Tutorial Outline

l Introduction and motivationlProcessor core power reduction

techniqueslMemory system power reduction

techniqueslSoC clock power reduction techniqueslSoC bus power reduction techniqueslFuture challenges

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ASIC Tutorial Intro.ASIC Tutorial Intro.33Low Power Design for Low Power Design for SoCsSoCs ©©M.J. Irwin, PSU, 1999M.J. Irwin, PSU, 1999

Power

lPower is the rate at which energy is delivered or exchanged» electrical energy is converted to heat energy

during operation

lPower Dissipation - rate at which energy is taken from the source (Vdd) and converted into heat

ASIC Tutorial Intro.ASIC Tutorial Intro.44Low Power Design for Low Power Design for SoCsSoCs ©©M.J. Irwin, PSU, 1999M.J. Irwin, PSU, 1999

Why Power Matters

lPackaging costs; cooling costslPower supply rail designlDigital noise immunitylBattery life (in portable systems)lEnvironmental concerns

» Office equipment accounted for 5% of total US commercial energy usage in 1993

» Energy Star compliant systems

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ASIC Tutorial Intro.ASIC Tutorial Intro.55Low Power Design for Low Power Design for SoCsSoCs ©©M.J. Irwin, PSU, 1999M.J. Irwin, PSU, 1999

Technology Directions: SIA Roadmap

Year 1999 2002 2005 2008 2011 2014 Feature size (nm) 180 130 100 70 50 35 Logic trans/cm2 6.2M 18M 39M 84M 180M 390M Cost/trans (mc) 1.735 .580 .255 .110 .049 .022 #pads/chip 1867 2553 3492 4776 6532 8935 Clock (MHz) 1250 2100 3500 6000 10000 16900 Chip size (mm2) 340 430 520 620 750 900 Wiring levels 6-7 7 7-8 8-9 9 10 Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.5 High-perf pow (W) 90 130 160 170 175 183 Battery pow (W) 1.4 2 2.4 2.8 3.2 3.7

ASIC Tutorial Intro.ASIC Tutorial Intro.66Low Power Design for Low Power Design for SoCsSoCs ©©M.J. Irwin, PSU, 1999M.J. Irwin, PSU, 1999

Chip Power Densities

0

10

20

30

40

50

60

1.5 1 0.8 0.6 0.35 0.25 0.18 0.13 0.1 0.07

Process (microns)

W/c

m2

Hot plate

From From BorkarBorkar, 1999, 1999

4

ASIC Tutorial Intro.ASIC Tutorial Intro.77Low Power Design for Low Power Design for SoCsSoCs ©©M.J. Irwin, PSU, 1999M.J. Irwin, PSU, 1999

Battery Technology Improvements

BATTERY(40+ lbs)

Year

No m

i nal

Cap

a ci ty

(Wat

t-hou

rs/l

b)Nickel-Cadium

Ni-Metal Hydride

65 70 75 80 85 90 95 0

10

20

30

40

50 Rechargable Lithium

Expected battery lifetime increaseover next 5 years: 30-40% From From RabaeyRabaey, 1995, 1995

ASIC Tutorial Intro.ASIC Tutorial Intro.88Low Power Design for Low Power Design for SoCsSoCs ©©M.J. Irwin, PSU, 1999M.J. Irwin, PSU, 1999

Where Does Power Go in CMOS?

lDynamic Power Consumption» charging and discharging capacitors

lShort Circuit Currents» short circuit path between supply rails

during switchinglLeakage Current

» leaking diodes and transistorslStatic Currents

» design styles such as pseudo NMOS

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ASIC Tutorial Intro.ASIC Tutorial Intro.99Low Power Design for Low Power Design for SoCsSoCs ©©M.J. Irwin, PSU, 1999M.J. Irwin, PSU, 1999

CMOS Gate Energy/Power Equations

E = 1/2 CL Vdd2 + (tr + tf)/2 Vdd Ipeak

+ Vdd Ileakage

P = CL Vdd2 f + (tr + tf)/2 Vdd Ipeak f+ Vdd Ileakage

ASIC Tutorial Intro.ASIC Tutorial Intro.1010Low Power Design for Low Power Design for SoCsSoCs ©©M.J. Irwin, PSU, 1999M.J. Irwin, PSU, 1999

Dynamic Power Consumption

Energy/transition = CL P0→ 1 * Vdd2

Power = Energy/transition * transition rate = CL P0→ 1 * Vdd2 * f

Not a function of transistor sizes!Data dependent - a function of switching activity!

Vin Vout

CL

Vdd

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ASIC Tutorial Intro.ASIC Tutorial Intro.1111Low Power Design for Low Power Design for SoCsSoCs ©©M.J. Irwin, PSU, 1999M.J. Irwin, PSU, 1999

Short Circuit Currents Determinates

lDuration and slope of the input signall I-V curves of the P and N transistors

which depend on their sizes, process technology, temperature, etc.

lOutput loading capacitance

(tr + tf)/2 Vdd Ipeak

ASIC Tutorial Intro.ASIC Tutorial Intro.1212Low Power Design for Low Power Design for SoCsSoCs ©©M.J. Irwin, PSU, 1999M.J. Irwin, PSU, 1999

Short-Circuit Current Variation with Input Signal Slope

V

t

1ns 2ns 4ns

t

I(sc)

1ns 2ns 4ns

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ASIC Tutorial Intro.ASIC Tutorial Intro.1313Low Power Design for Low Power Design for SoCsSoCs ©©M.J. Irwin, PSU, 1999M.J. Irwin, PSU, 1999

Leakage Currents

Vout

Vdd

Sub-threshold current is the dominant factor.Increases exponentially with temperature!

Sub-threshold current

Drain junction leakage

Vdd Ileakage

ASIC Tutorial Intro.ASIC Tutorial Intro.1414Low Power Design for Low Power Design for SoCsSoCs ©©M.J. Irwin, PSU, 1999M.J. Irwin, PSU, 1999

Sub-Threshold in MOS

VT=0.6VT=0.2

√ID

VGS

Lower bound on threshold voltage to prevent leakage

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ASIC Tutorial Intro.ASIC Tutorial Intro.1515Low Power Design for Low Power Design for SoCsSoCs ©©M.J. Irwin, PSU, 1999M.J. Irwin, PSU, 1999

Glitching in Static CMOS

ABC

X

Z

101 000

Unit Delay

AB

X

Z

ASIC Tutorial Intro.ASIC Tutorial Intro.1616Low Power Design for Low Power Design for SoCsSoCs ©©M.J. Irwin, PSU, 1999M.J. Irwin, PSU, 1999

Glitching in an RCA

0 5 100.0

2.0

4.0

Time, ns

Sum

Out

put V

olta

ge, V

olts

Cin

S15

S10

6

5

4

3

2S1

Add0 Add1 Add2 Add14 Add15

S0 S1 S2 S14 S15

Cin

From From RabaeyRabaey, 1995, 1995

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ASIC Tutorial Intro.ASIC Tutorial Intro.1717Low Power Design for Low Power Design for SoCsSoCs ©©M.J. Irwin, PSU, 1999M.J. Irwin, PSU, 1999

Basic Principles of Low Power Design

lReduce switching (supply) voltage» quadratic effect -> dramatic savings» negative effect on performance

lReduce capacitancelReduce switching frequencylReduce glitchinglReduce leakage and static currents

P = CL Vdd2 f + (tr + tf)/2 Vdd Ipeak f + Vdd Ileakage

ASIC Tutorial Intro.ASIC Tutorial Intro.1818Low Power Design for Low Power Design for SoCsSoCs ©©M.J. Irwin, PSU, 1999M.J. Irwin, PSU, 1999

Reducing Vdd Lowers Energy

P x td = Et = CL * Vdd2

E(Vdd=2)=

(CL) * (2)2

(CL) * (5)2E(Vdd=5)

Strong function of voltage (V2 dependence).

Relatively independent of logic function and style.

E(Vdd=2) ≈ 0.16 E(Vdd =5)

0.03

0.05

0.07

0.1

0.15

0.20

0.30

0.50

0.70

1.00

1.5

1 2 5

51 stage ring oscillator

8-bit adder

Vdd (volts)

quadratic dependence

NO

RM

ALI

ZED

PO

WE

R-D

EL

AY

PR

OD

UC

T

Power Delay Product Improves with lowering VDD.From From RabaeyRabaey, 1995, 1995

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ASIC Tutorial Intro.ASIC Tutorial Intro.1919Low Power Design for Low Power Design for SoCsSoCs ©©M.J. Irwin, PSU, 1999M.J. Irwin, PSU, 1999

Reducing Vdd Increases Delay

CL * Vdd

I=Td

Td(Vdd=5)

Td(Vdd=2)=

(2) * (5 - 0.7)2

(5) * (2 - 0.7)2

≈ 4

I ~ (Vdd - Vt)2

Relatively independent of logic function and style.

1.001.502.002.503.003.504.004.505.005.506.006.507.007.50

2.00 4.00 6.00Vdd (volts)

NO

RM

AL

IZED

DE

LA

Y

adder (SPICE)

microcoded DSP chip

multiplier

adder

ring oscillator

clock generator2.0µm technology

From From RabaeyRabaey, 1995, 1995

ASIC Tutorial Intro.ASIC Tutorial Intro.2020Low Power Design for Low Power Design for SoCsSoCs ©©M.J. Irwin, PSU, 1999M.J. Irwin, PSU, 1999

Figures of Meritl Power consumption in Watts

» packaging consideration and cooling requirements» system power supply

l Peak power» power ground wiring designs» signal noise margin and reliability analysis

l Power (energy) efficiency of a circuit in Joules» rate at which energy is consumed over time» energy dissipation per clock cycle» lower energy number means less power to perform a

computation at the same frequencyl Energy-delay or power-delay product (PDP)

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ASIC Tutorial Intro.ASIC Tutorial Intro.2121Low Power Design for Low Power Design for SoCsSoCs ©©M.J. Irwin, PSU, 1999M.J. Irwin, PSU, 1999

Design LevelsAbstraction Power Analysis AnalysisLevel Savings Resources Accuracy

Most Least Worst

AlgorithmSoftware/systemArchitectureFunctional unitGateCircuit

Least Most Best

ASIC Tutorial Intro.ASIC Tutorial Intro.2222Low Power Design for Low Power Design for SoCsSoCs ©©M.J. Irwin, PSU, 1999M.J. Irwin, PSU, 1999

Analysis Techniquesl Simulation techniques

» characterization - using lower level analysis tools to construct higher level models

– very computationally intensive– can be very accurate– gives cycle accurate numbers

l Probabilistic techniques» signals are viewed as random zero-one processes

with certain statistical characteristics– computationally efficient– accuracy depends on input statistics assumptions– gives average value for a sequence of cycles

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ASIC Tutorial Intro.ASIC Tutorial Intro.2323Low Power Design for Low Power Design for SoCsSoCs ©©M.J. Irwin, PSU, 1999M.J. Irwin, PSU, 1999

Key ReferencesBorkar, Design Challenges of Technology Scaling, IEEE Micro, pp. 23-29,

Aug 1999.Chandrakasan, Broderson, Low Power Digital CMOS Design, KAP, 1995.Najm, A survey of power estimation techniques in VLSI circuits, IEEE

Trans. on VLSI Systems, 2(4):446-455, 1994.Pedram, Power minimization in IC design, ACM TODAES, 1(1):3-56, 1996.Proceedings of ACM/IEEE Symposium on Low Power Electronics and

Design (SLPED), 1995 - 1999.Rabaey, Digital Integrated Circuits, Prentice-Hall, 1996.Rabaey, Pedram, Low Power Design Methodologies, KAP, 1996.SIA Roadmap, notes.sematech.org/ntrs/PubINTRS.nsfTiwari, Reducing power in high-performance microprocessors, Proc. of

DAC, pp. 732-737, 1998.Yeap, Practical Low Power Digital VLSI Design, KAP, 1998.