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Low power ldpc decoder implementation using layer decoding

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LOW-POWER LDPC DECODER IMPLEMENTATION USING LAYER DECODING AJITH.C 212111419001 Guide BY M.E VLSI Design Mr.P Kabilamani,Lecturer,ECE
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Page 1: Low power ldpc decoder implementation using layer decoding

LOW-POWER LDPC DECODER IMPLEMENTATION USING

LAYER DECODING

AJITH.C 212111419001 Guide BYM.E VLSI Design Mr.P Kabilamani,Lecturer,ECE

Page 2: Low power ldpc decoder implementation using layer decoding

Abstract Method for creating LDPC codes which are

specifically designed to be hardware friendly. Layer decoding is the one of the efficient

approach to decode the LDPC code with good error rate performance.

Proposed approach will efficiently decrease the power.

Page 3: Low power ldpc decoder implementation using layer decoding

INTRODUCTION LDPC Code is a Linear Error Correcting Code. LDPC codes are finding increasing use

◦ 1. reliable and highly efficient information transfer over bandwidth

◦ 2. return channel–constrained links in the presence of data-corrupting noise.

Error correcting code in the new DVB-S2

Page 4: Low power ldpc decoder implementation using layer decoding

Cont… Representations for LDPC Codes

Matrix and Graphical

Representations

Page 5: Low power ldpc decoder implementation using layer decoding

Existing Method Layered Decoding

Page 6: Low power ldpc decoder implementation using layer decoding

Cont… Most Practical LDPC Codes are structured to support layered decoders in hardware. This concept is usually generalized by dividing the H-Matrix into Layers. Only one CN can access a given VN memory at a specific time. In a layered decoder,one CN processor can be designed to serially process the

different rows of the H-Matrix.

Page 7: Low power ldpc decoder implementation using layer decoding

Proposed Method Vectored Layer Decoding

Page 8: Low power ldpc decoder implementation using layer decoding

Cont… Vector Decoder Architecture

overcomes the limitation of the layered decoder by packing multiple messages in the same memory unit.

Throughput of a vector decoder can be times that of a scalar decoder.

Page 9: Low power ldpc decoder implementation using layer decoding

Phase I LDPC Encoding

Page 10: Low power ldpc decoder implementation using layer decoding

Phase II LDPC Decoding using Layer

Decoding.

Vectored Layer Decoding.

Page 11: Low power ldpc decoder implementation using layer decoding

LDPC Encoding Generator Matrix from Parity

Check Matrix. Encoding Technique.

Page 12: Low power ldpc decoder implementation using layer decoding

Generator Matrix from Parity Check Matrix Parity Check Matrix(H)

H(qxn)=[Pqxk : Iq ]. Generator Matrix(G)

G(kxn) =[Ik:Pkxq].

Page 13: Low power ldpc decoder implementation using layer decoding

Encoding Technique Encoding by Matrix Multiplication Systematic codeword Generation codeword,X=axGT

a=(a1,a2,……ak),k information bits to be encoded.

GT=Generator Matrix Transpose

Page 14: Low power ldpc decoder implementation using layer decoding

Software Used

Simulation : Xilinx ISE 9.1i

Page 15: Low power ldpc decoder implementation using layer decoding

Simulation For H Matrix To G Matrix Generation

Page 16: Low power ldpc decoder implementation using layer decoding

Cont..

Page 17: Low power ldpc decoder implementation using layer decoding

Simulation For LDPC Encoding

Page 18: Low power ldpc decoder implementation using layer decoding

References R. Gallager, “Low-density parity-check codes,”

IEEE Trans. Inf. Theory, vol. IT-8, no. 1, pp. 21–28, Jan. 1962.

Z. Li, L. Chen, L. Zeng, S. Lin, and W. Fong, “Efficient encoding of quasi-cyclic low-density parity-check codes,” IEEE Trans. Commun.,vol. 53, no. 11, p. 1973, Nov. 2005.

E. Yeo, P. Pakzad, B. Nikolic, and V. Anantharam, “High throughput low-density parity-check decoder architectures,” in Proc. IEEE Global Telecommun. Conf., 2001, vol. 5, pp. 3019–3024.

Page 19: Low power ldpc decoder implementation using layer decoding

THANK YOU


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