IOP PUBLISHING JOURNAL OF PHYSICS D: APPLIED PHYSICS
J. Phys. D: Appl. Phys. 46 (2013) 074003 (10pp) doi:10.1088/0022-3727/46/7/074003
Low-power non-volatile spintronicmemory: STT-RAM and beyondK L Wang, J G Alzate and P Khalili Amiri
Electrical Engineering Department, University of California, Los Angeles, CA 90095, USA
Received 15 August 2012, in final form 18 October 2012Published 31 January 2013Online at stacks.iop.org/JPhysD/46/074003
AbstractThe quest for novel low-dissipation devices is one of the most critical for the future ofsemiconductor technology and nano-systems. The development of a low-power, universalmemory will enable a new paradigm of non-volatile computation. Here we considerSTT-RAM as one of the emerging candidates for low-power non-volatile memory. We showdifferent configurations for STT memory and demonstrate strategies to optimize keyperformance parameters such as switching current and energy. The energy and scaling limitsof STT-RAM are discussed, leading us to argue that alternative writing mechanisms may berequired to achieve ultralow power dissipation, a necessary condition for direct integrationwith CMOS at the gate level for non-volatile logic purposes. As an example, we discuss theuse of the giant spin Hall effect as a possible alternative to induce magnetization reversal inmagnetic tunnel junctions using pure spin currents. Further, we concentrate onmagnetoelectric effects, where electric fields are used instead of spin-polarized currents tomanipulate the nanomagnets, as another candidate solution to address the challenges of energyefficiency and density. The possibility of an electric-field-controlled magnetoelectric RAM asa promising candidate for ultralow-power non-volatile memory is discussed in the light ofexperimental data demonstrating voltage-induced switching of the magnetization andreorientation of the magnetic easy axis by electric fields in nanomagnets.
(Some figures may appear in colour only in the online journal)
1. Introduction
The continuous scaling and development of CMOS has spurreda technological revolution, allowing for faster and morepowerful microprocessors and electronics with an increasednumber of functionalities [1, 2]. CMOS is currently thedominating technology for logic circuits, but is quicklyapproaching its scaling limits due to increased problems withpower dissipation at scaled technology nodes. The increasein power dissipation results from the increase in static leakage(standby) power, as well as from the increase in density as thedevice size is scaled down. The integration of a fast, energy-efficient non-volatile memory technology with CMOS can helpalleviate this problem. Non-volatile logic circuits consistingof volatile CMOS, combined with non-volatile memory, canmake electronic products non-volatile at the device, gate,circuit and system levels, hence allowing for continued scalingwith improved energy efficiency by eliminating static powerdissipation.
In the memory hierarchy, typically the information istemporally stored in static random access memories (SRAMs)
as cache memory next to the CMOS logic, and in dynamicrandom access memories (DRAMs) as the principal workingmemory, and then permanently stored in Flash or hard drives,used as non-volatile memories for long-term retention. Table 1shows the most important metrics for SRAM, DRAM andNOR Flash. SRAM is the fastest of the three (operating in theGHz range), needs little dynamic power (∼100 fJ per switch),has unlimited endurance, and can be incorporated directly onthe logic chip. However, SRAM is volatile, has a very lowdensity (resulting in a higher cost per bit) and the standby powerconsumption becomes a problem as the transistor dimensionsare scaled down, leading to higher leakage currents. DRAMhas a higher density compared with SRAM, but it is alsovolatile and needs a periodic refresh, which results in powerconsumption for maintaining the memory state. Also, theconventional DRAM fabrication process is not compatiblewith standard CMOS logic. The NOR flash memories havethe highest density among the three, and are non-volatile.However, they have very slow write speed and very limitedendurance. They also use high power for writing data andhigh internal voltages are needed for their operation.
J. Phys. D: Appl. Phys. 46 (2013) 074003 K L Wang et al
Table 1. Comparison of existing non-spintronic and emerging spintronic memory technologies, highlighting STT-RAM (current-inducedswitching) and MeRAM (voltage-controlled switching).
Production processes In development
Technology SRAM DRAM NOR Flash STT-RAM MeRAM
Energy/bit (fJ) 100 1000 106 100 <10Write speed (ns) 1 20 1000 1–10 1–10Read speed (ns) 1 30 10 1–10 1–10Density (area in F2) >30 6–10 4–8 10–30 4–8Endurance (cycles) Very High Very High Low Very High Very HighNon-volatile No No Yes Yes YesStandby power Leakage Current Refresh Current None None NoneCost overhead versus CMOS Large area (6T) Separate process Separate process Back-end (BEOL) process Back-end (BEOL)
processNon-volatile logic capability No No No Very limited due to power Yes
Spintronic devices, i.e. those which exploit the exchangeinteraction of the electron spins, where magnetic and transportproperties are coupled, are strong candidates for non-volatilememory due to the inherent hysteresis in ferromagneticmaterials, and the compatibility of some of these materials withthe standard CMOS process [3–5]. In fact, magnetoresistiveRAM (MRAM) has exhibited significant advantages as afast, fairly low-power, high-endurance, radiation-resistantnon-volatile memory, which can be integrated to the CMOSas a back-end of line (BEOL) process [6]. Usually, theread-out of the MRAM bits is reliably performed via thetunnelling magnetoresistance (TMR) [7, 8] effect in magnetictunnel junctions (MTJs). As for the writing process, the firstgenerations of MRAM utilized the Oersted fields generatedby running currents in adjacent conducting lines of memorycells to switch the magnetization. However, this strategyhas proven to be highly inconvenient in terms of energyefficiency, scalability and density. Therefore, the manipulationof the magnetic moments by currents or electric voltagesis required to overcome the shortcomings of Oersted-field-switched MRAM.
In this work, we will first concentrate on the switching ofmagnetization of MRAM bits using spin-polarized currentsvia the spin transfer torque (STT) effect [7, 9, 10] in orderto achieve low power operation. As observed in table 1,the use of spin-polarized currents instead of Oersted fieldsallows for switching energies and speed close to SRAM,while the density can be better than SRAM and potentiallyapproach close to DRAM levels, making STT-RAM asuitable candidate for embedded as well as potentially stand-alone applications. More importantly, STT-RAM has betterscalability as compared with Oersted-field-switched MRAM,where the switching current increases as the MTJ dimensionsare reduced. We will examine strategies to optimize theperformance for STT-RAM devices in this paper.
In the second part of this paper, we will study beyondSTT mechanisms, targeting for ultralow power performance(switching energies <1 fJ). This is a critical challenge sincethe switching energies of STT-RAM are still around twoorders of magnitude higher compared with CMOS switchingenergy (∼1 fJ for the 32 nm node), limiting the possibility ofintegration of MTJ devices at the gate level with CMOS logicfor non-volatile logic architectures [11]. Additionally, the
ultralow power MTJs could be used to relieve the increasingstatic leakage power, as the transistors are scaled, due to thecontinuous energy that needs to be delivered to retain theinformation in the volatile CMOS [12]. Hence, ultralow-powervoltage-controlled MRAM could impart a significant overallenergy advantage over STT-RAM based circuits.
For ultra-low power spin-based memories beyondSTT-RAM, this paper will discuss two approaches: first, wewill consider magnetoelectric effects which manipulate themagnetization by electric fields (or voltages) instead of thecurrent-driven mechanisms [13, 14]. In particular, the ultimatescalability of STT-RAM in terms of density and energy maybe limited by the large currents needed to switch the device;thus, a voltage control scheme is expected to translate into areduction in the switching energy and increased densities ina future magnetoelectric RAM (MeRAM), while keeping theadvantages of STT-RAM (See table 1) [15]. Finally, we willdiscuss the giant spin Hall effect as an alternative mechanismto reduce the switching currents for STT-RAM by driving purespin currents through MTJ devices [16].
2. STT as switching mechanism for MTJs
The discovery of the possibility to manipulate and induceswitching of the magnetization by spin-polarized currentsvia the STT effect [9, 10] in nanomagnets has been the keymotivating force behind the recent rise of interest in MRAM,and particularly STT-RAM [17, 18]. STT-RAM conserves theadvantages of Oersted-field-switched (toggle) MRAM (highspeed, very high endurance, non-volatility), but the current-driven switching mechanism makes STT-RAM more scalableand allows for smaller switching energies (on the order of∼100 fJ) compared with Oersted-field-switched MRAM, aswill be discussed later.
A typical simplified STT-RAM structure is shown infigure 1: it consists of a free layer which can take two states(parallel or antiparallel) to a pinned (fixed) layer, both ofthe layers separated by a tunnelling oxide, which is usuallyMgO to allow for read-out via the TMR (tunnelling magneto-resistance) effect [6, 19]. The writing process is performedby passing a spin-polarized current, which transfers some ofits momentum to the nanomagnet, inducing a torque that canresult in switching depending on the direction of the current.
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Figure 1. Typical architecture for a 1 transistor—1 MTJ (1T-1R)memory cell. The MTJ is composed of a bi-stable free layer and apinned layer separated by a tunnelling oxide. The device isfabricated as part of the back-end (BEOL) process, compatible withCMOS logic processes.
Therefore, the combination of STT and TMR gives rise to thememory loops observed in the quasi-static I–V relation as wellas the pulsed R–V characteristics of figure 2 (left) and (right),respectively.
In this section we will consider three different designs forSTT-RAM devices (referred to as I-STT, C-STT and P-STTstanding for in-plane, combined and perpendicular), whichoffer different characteristics and performances due to theirconfiguration of magnetization direction and anisotropies ofthe free and fixed layers. In our discussion, we will considerMTJ devices due to their high magnetoresistance ratio andthe possibility of tuning the MgO thickness for impedanceoptimization for energy efficiency and compatibility with theaccess transistors used in a memory implementation. Wewill particularly emphasize strategies to increase speed andenhance energy efficiency during switching.
2.1. In-plane free layers
Two of the device configurations where the magnetizationof the free layer lies in the plane of the thin film (in-plane configuration) are shown in figures 3(a) and (b). Theequilibrium states are determined by the shape anisotropyalong the long (easy) axis of the nanopillar. In the I-STT (in-plane STT) configuration, the polarizer (pinned layer) will be inthe same plane as the free layer, while the C-STT (combination-STT) structure (also referred to as orthogonal STT-RAM)includes an additional polarizer for reasons to be discussedlater in this section.
The simplest MTJ structure to realize is I-STT, and hasbeen thus studied the most over the past years. In I-STTdevices, one of the key challenges is to reduce the switchingcurrent density Jc0 while keeping a reasonable thermal stabilityfactor � for non-volatility. The value of � defines themagnetic bit’s stability against false switching events due tothermal activation (i.e. retention time); for example, a thermal
stability factor of � = 40 translates into a mean retentiontime ∼10 years for a discrete device. Specifically, the thermalstability factor is given by � = MsHkV/2kT , where Ms is thesaturation magnetization, Hk is the magnetic anisotropy field,V is the volume of the free layer, k is the Boltzmann constantand T is the temperature. For I-STT and C-STT devices, Hk
is mainly determined by the in-plane shape anisotropy (i.e.the energetic preference for the magnetization to align along apreferred direction as determined by the shape of the magneticbit). Therefore, as the volume of the MTJ is decreased in I-STTand C-STT devices, Hk needs to be increased, for example, byincreasing the aspect ratio of the ellipses or the thickness ofthe free layer to retain stability. For the I-STT configuration,the switching current density is given by [20]
Jc0 = (2eαMst/h̄η)(Hk + Hd/2), (1)
where α is the free layer damping factor, η is the spin-transferefficiency, Ms and t are the free layer saturation magnetizationand thickness, Hk is the in-plane shape-induced anisotropyfield and Hd ≈ 4πMs � Hk is the out-of-plane demagnetizingfield. Scaling of I-STT devices generally requires a trade-off between the switching current density Jc0 and the thermalstability factor �, where the goal is to minimize the ratio Jc0/�
while preserving a given goal for the thermal stability factor.I-STT suffers from a small spin torque during the initial
incubation stage of magnetization switching, a consequenceof its parallel-magnetized equilibrium states. Its switchingspeed is generally limited to ∼1 ns [21, 22]. Figure 4 showsthe typical switching voltage and energy dependence on pulsewidth in an I-STT device for pulses >1 ns. An alternative toeliminate the initial incubation of I-STT devices is to includean additional out-of-plane polarizer (see figures 3(c) and (d))[21–23]. This C-STT configuration uses a combination of in-plane and perpendicular polarizers, where only the in-planepolarizer provides TMR for read-out of the in-plane free layerstate. In C-STT devices, spin torque from the perpendicularpolarizer causes the free layer magnetization to go out-of-plane, where it precesses around the demagnetizing field [24,25], allowing for ultrafast precessional switching limited onlyby the ferromagnetic resonance (FMR) frequency of the bit. Asobserved in the macrospin simulations of figures 3(c) and (d),the torque provided by the out-of-plane polarizer eliminatesthe initial incubation resulting in precessional switching onthe order of ∼100 ps. Further, switching with pulses down to50 ps has been demonstrated also in spin-valve structures [26].Note that the in-plane polarizer is still required for read-outand also provides additional torque. If we take into accountthat the write energy is given by E = V 2t/R, the reductionin the required pulse time t outpaces the potential increasein the required voltage for C-STT, resulting in a reduction inthe switching energy larger than 50% as compared with anI-STT device with an otherwise similar layered structure (seefigure 4).
To further reduce the write energy in STT-RAM, one canperform further optimization on both the free layer as wellas the MgO barrier. If the switching energy is written asE = V 2t/R = J 2
CA2Rt , it is evident that it can be furtherdecreased in I-STT devices by (1) reducing the resistance
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Figure 2. (Left) Example of current-induced switching results in STT-RAM. Quasi-static V –I curves show the existence of two availableresistance states, defining the memory window for STT-RAM devices. The free layer of the MTJ can be switched parallel or anti-parallel tothe pinned layer depending on the direction of the current. (Right) The pulsed R–V curve demonstrates switching of the MTJ with voltagepulses of 1 ns with voltages ∼0.5 V. The read-out of the state is performed via the TMR effect with a typical TMR ratio >100%. (Reprintedwith permission from [27]. Copyright 2011, American Institute of Physics.)
Figure 3. (a) The layered structure for I-STT (IST) device, including a synthetic antiferromagnet (SAF) to compensate for the dipole fieldsfrom the pinned layer acting on the free layer. (b) The inclusion of an additional perpendicular polarizer results in a C-STT (OST)configuration, where the additional polarizer exerts a large initial torque for the free layer switching. (c) Macrospin simulations showing theintrinsic limitation of I-STT (IST) due to the incubation time required for a switching event. (d) The perpendicular polarizer in C-STT(OST) results in precessional switching, hence eliminating the initial incubation, allowing for switching with pulses of the order of 100 ps.(Reprinted with permission from [22]. Copyright 2011, American Institute of Physics.)
R of the MTJ, or by (2) decreasing the switching currentdensity. The first strategy is limited by practical reasons,since reducing the resistance of the MTJ requires thinnerMgO barriers, which may result in reduction in the TMRratio, endurance or breakdown voltage, as well as increases inundesired device-to-device variability. Furthermore, scaling ofSTT-RAM generally requires moving to thinner MgO barriersto maintain CMOS-compatible voltage levels (i.e. reducingthe RA product to prevent R from increasing), and henceMgO thickness is generally set by considerations other thanenergy. Figure 5 (left) shows the dependences of resistance–area (RA) product and TMR on the MgO barrier thicknessin CoFeB–MgO MTJs, measured on a single wafer with
varying MgO thicknesses [27, 28]. It is observed that the TMRrapidly decreases when the thickness of the MgO becomesless than 0.8 nm, whereas the variability of the RA productincreases for the same range of tunnelling barrier thicknesses.Figure 5 (right) shows the write energy and switching currentdensity as a function of RA product in an optimized I-STTCoFeB/MgO/CoFeB tunnel junction. Although the expectedreduction in the switching energy with decreasing RA productis observed, the switching current also increases (possibly asa result of higher effective damping in the free layer due to thereduced MgO quality for low RA devices), further limiting thestrategy of reducing the resistance of the MTJ to obtain smallerswitching energies.
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Figure 4. (a) I-STT switching is limited to pulses above ∼1 ns. TheC-STT configuration allows for switching on the timescales <1 ns.(b) Although larger voltages are needed for C-STT switching in thisexperiment due to the second MgO barrier, the energy per switch atthe bit level can still be lowered compared with I-STT due to the useof ultra fast (∼ hundreds of ps) pulses. (Reprinted with permissionfrom [22]. Copyright 2011, American Institute of Physics.)
Another strategy to decrease the switching energy requiresthe reduction in the switching current of the I-STT devices.Specifically, the switching current to thermal stability figureof merit is given by
Ic0
�= (4eαkT /h̄η)(1 + Hd/2Hk), (2)
where it can be observed that the switching current isdominated by the out-of-plane demagnetizing field Hd, whichtypically does not determine the thermal stability, given thatHk � Hd. Hence, a promising method to decrease theswitching current without sacrificing the thermal stability isto decrease the demagnetizing field Hd by the introduction ofperpendicular anisotropy in the free layer [6, 29, 30]. If theperpendicular anisotropy creates an anisotropy field Hk⊥, theswitching current over thermal stability ratio can become muchsmaller
Ic0
�= (4eαkT /h̄η)(1 + (Hd − Hk⊥)/2Hk). (3)
A significant interface-induced perpendicular anisotropyhas been observed in Fe-rich CoFeB/MgO junctions [31],while keeping large TMR values. Using Co20Fe60B20 freelayers, our recent work [30] has demonstrated the reduction inthe average quasi-static switching current density by >40%(from ∼2.8 to ∼1.6 MA cm−2) due to the presence of theperpendicular anisotropy. Figure 6 (left) shows the dependenceof the switching current (at 10 ns) on perpendicular anisotropy,where the fast decrease in switching current with thickness fitswith the interfacial origin of the anisotropy.
2.2. Perpendicular free layers
If the perpendicular anisotropy of the free and fixed layersare large enough to overcome their respective demagnetizingfields (i.e. Hk⊥ > Hd), the magnetizations of the layersbecome perpendicular, giving rise to a fully perpendicular(P-STT) configuration [31]. Given that the thermal stabilityin P-STT is determined by the perpendicular anisotropy ofthe free layer (and not by the elliptical shape as in I-STT),the P-STT structures can be made in circular shape [32, 33].In the P-STT configuration, the demagnetizing field is fully
cancelled and therefore, the switching current density wouldbe given by Jc0 = 2eαMsHkt/h̄η, while the switching currentover thermal stability figure of merit will be given by
Ic0
�= 4eαkT /h̄η. (4)
It can be noted that the elimination of the demagnetizingfield leads to a potentially smaller switching current overthermal stability ratio, if damping can be controlled. Severalworks have recently demonstrated P-STT structures utilizingthe interfacial perpendicular anisotropy of Fe-rich CoFeBlayers in MgO MTJs [31, 34, 35], with switching currentsas low as <2 MA cm−2 [34]. Figure 6 (right) shows thedependence of the switching current on the thickness of the freelayer, where it can be clearly observed that, as the free layerbecomes thinner, the increase in the perpendicular anisotropyin the free layer leads to a larger switching current despite itsreduced volume.
Finally, it is worth mentioning that there are on-goingefforts to reduce the switching current in STT-RAM bits byother approaches such as bias-assisted [36] and thermallyassisted switching [37, 38]. In the latter scenario, it hasbeen experimentally demonstrated that the temperature riseof the MTJ while the current pulse is applied can reduce theperpendicular anisotropy in P-STT bits to assist the reversalprocess, resulting in a reduction in the required switchingcurrent without sacrificing the thermal stability of the memorycell in the idle state [38].
3. Beyond STT-RAM: magnetoelectric memory
Despite the promising advantages of STT-RAM over othercompeting volatile and non-volatile technologies, it faces anumber of fundamental and technological challenges to beaddressed. In particular, the scaling of the MTJ dimensionswill be limited by the super-paramagnetic limit for the in-plane configuration, while the development of materials withstronger perpendicular anisotropies is required to maintainthe stability in smaller P-STT MTJs [39]. But even forP-STT, the ratio of switching current to thermal stability (henceretention time) is determined by fundamental constants andparameters with a limited tuning range (i.e. damping and spintransfer efficiency in equation (4)). Therefore, if we assume aconstant thermal stability scaling rule with small variations inα and η, the switching current will remain constant across thedifferent technology nodes, independent of the MTJ size, andconsequently, the STT-RAM memory cell size will be mostlylimited by the size of the transistor required to drive the currentand not by the MTJ itself. In addition to scalability issues,the switching energy will also not scale proportionally if theresistance of the MTJ is kept constant (by decreasing the RAproduct as the MTJ size is scaled down). Considering thatthe STT-RAM switching energy is still close to two ordersof magnitude larger than CMOS switching energies (∼100 fJfor STT-RAM, compared with 1 fJ for the 32 nm CMOS noderespectively), the range of applications for hybrid CMOS-MTJ circuits would be limited by the relatively large energy
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Figure 5. (Left) Dependence of MTJ resistance–area (RA) product and TMR ratio on the MgO barrier thickness in a CoFeB–MgO MTJwith RA = 3.5 � µm2. For MgO thicknesses below 0.8 nm, a noticeable increase on the spread of the RA product and a decrease in theTMR ratio is observed. (Reprinted with permission from [28]. Copyright 2011, Institute of Electrical and Electronics Engineers.) (Right)The reduction in the RA product is shown to decrease the write energy in an in-plane MTJ. However, as the RA product is reduced, theswitching current also increases, limiting this strategy for decreasing write energy. (Reprinted with permission from [27]. Copyright 2011,American Institute of Physics.)
Figure 6. (Left) The interfacial anisotropy in Fe-rich CoFeB can be exploited to reduce the switching current in I-STT devices. As the freelayer thickness is decreased, the perpendicular anisotropy increases due to the interfacial origin of the anisotropy. When the switchingcurrent density at 10 ns is measured as a function of free layer thickness, we observe a noticeable reduction, much larger than what would beexpected from the reduction in the free layer volume alone. (Reprinted with permission from [30]. Copyright 2011, American Institute ofPhysics.) (Right) When the free layer thickness is reduced further, the perpendicular anisotropy surpasses the demagnetizing field and thefree layer becomes perpendicular. In the P-STT configuration, we observe the inverse effect, where decreasing the free layer thicknessincreases Hk⊥, resulting in larger current densities. (Reprinted with permission from [34]. Copyright 2012, American Institute of Physics.)
dissipation of the memory elements, even when scaling is takeninto consideration.
In order to reach or surpass the energy efficiency ofCMOS, leading to an ultra low-power non-volatile memorywith switching energies ∼1 fJ or below at the bit level, wewill consider in this section (1) magnetoelectric effects, inwhich voltage, instead of current, is used to manipulate themagnetization of the memory device [13, 14, 40–42, 45–47],and (2) the possibility of exploiting the giant spin Hall effectto switch the magnetization in MTJs [16].
3.1. Magnetoelectric MTJ devices
A possible approach for developing an ultra-low-power spin-based memory is replacing the spin-polarized currents used tomanipulate and switch the magnetization by voltage-driveneffects [13, 14, 40, 41]. A particularly interesting approachfor the realization of a magnetoelectric memory is based onthe observation that the interfacial perpendicular anisotropy inFe-rich CoFeB/MgO junctions can be modulated by voltage[13, 43, 44]. When a bias voltage is applied, the accumulated
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Figure 7. Voltage-induced switching of high resistance MTJ with 70 nm × 180 nm dimensions for AP to P (top) and P to AP(bottom) [42, 47]. The switching process is assisted by a small magnetic field HBias, which determines the switching direction. Note that thesame voltage polarity was used in both cases, confirming the voltage-induced mechanism. The switching mechanism can be described asfollows: due to the voltage-controlled interfacial anisotropy, the coercivity in the hysteresis loops is reduced. Therefore, the initialequilibrium states (A,D) are forced to relax to the only available state (B,E) with the voltage pulse applied.
charge near the CoFeB/MgO interface can modify the orbitaloccupancies of different symmetries, which at the same timecontrol the surface anisotropy due to spin–orbit coupling.Therefore, the interface anisotropy can be controlled by theamount of charges accumulated at the interface, i.e. the electricfield applied to the junction.
The voltage control of the perpendicular anisotropy hasbeen exploited to induce switching in MTJ devices [42, 45–47]. When ultra-fast (<1 ns) voltage pulses are applied,the voltage-induced magnetization dynamics can be used togenerate toggle switching of the MTJ by proper timing ofthe pulse [45, 48, 49], in an analogous fashion to the C-STTswitching discussed previously. In a second approach, thevoltage control of the interfacial anisotropy has been usedto modulate the coercivity of the MTJ devices, allowing forelectric-field-assisted switching [46, 47]. As demonstrated infigure 7, the applied voltage induces a reduction in coercivitydue to the modification of the interface anisotropy, translatinginto a single available state where the system is forced tothermally relax for a given applied bias magnetic field HBias.Once the voltage pulse is released, the system will thus haveswitched to the opposite direction. Note that the directionof the switching therefore will be determined by the effectivefield HBias, while the switching is obtained for the same voltagepolarity in both directions (see figure 7).
We have recently demonstrated that this approach allowsfor purely voltage induced (non-STT) switching with voltagepulses of ∼1 V in amplitude and down to t = 10 ns in duration
[42, 47]. In this experiment, MTJs with high resistance(>100 k�) were used, leading to leakage currents below10 µA. This leads to a small energy dissipation V 2t/R (due tothe leakage current) which is already one order of magnitudelower compared with STT-RAM. If the leakage current isfurther decreased, the energy per switch will eventually belimited to ∼CV 2, where C is the cell capacitance. This wouldbe a clear path towards reaching switching energies ∼10 aJwhile keeping the non-volatility of the memory elements.
One of the parameters relevant to the characterizationof a magnetoelectric-based memory (e.g. MeRAM) is theamount of effective magnetic field Heff generated per unit ofapplied voltage V or electric field E. Obviously, a largermagnetoelectric coefficient Heff/V or Heff/E could resultin smaller switching voltage and energy for the memorycell. In addition, the voltage required for switching in aMeRAM architecture should be small enough compared withthe breakdown voltage of the junction for reliable operation.Currently, devices with an RA product of 3.5 � µm2 havebeen measured to sustain >1016 pulses ∼0.5 V at 5 ns [28].Although the RA product to be used in MeRAM cells wouldbe orders of magnitude larger (with increased breakdownvoltage of the junction), further increase in the magnetoelectriccoefficient is desirable to reduce the switching voltage (tobelow 0.5 V) and thus, improve the endurance of the memorybits, as well as ensuring their compatibility with scaled CMOSlogic voltage levels. Finally, as the MeRAM bits are scaleddown, Hk will have to be increased to keep the thermal stability
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� constant. Therefore, a larger modulation of the effectivefields, comparable to Hk , would be required to switch thescaled bits.
In our MTJ devices with Fe-rich CoFeB free layer, thevoltage-controlled interfacial effect can generate effectivefields as large as 600 Oe per volt [43]. A magnetoelectriccoefficient close to the one observed in CoFeB/MgOsystems has also been observed for the FePt/MgO interfaceexperimentally [50]; however, this is still half of thetheoretically expected values for this system. Enhancementof the magnetoelectric coefficient has been demonstrated bystacking MgO next to a high-k dielectric [51, 52]. Theobserved enhancement is shown to be proportional to theincrease in the effective dielectric constant of the stack,as expected (i.e. ∼30% in MgO/HfO2Al2/O3 stacks [51]).Further, a 6.5 times enhancement of the magnetoelectriccoefficient, compared with Fe-rich CoFeB/MgO systems, hasbeen obtained recently in experiments using FePd next toMgO [53]. Finally, modulation of anisotropy by electricfields has also been observed in GdOx [54], AlOx andTaOx [55], the latter with a magnetoelectric coefficientsimilar to Fe-rich CoFeB/MgO. The challenge of finding aferromagnet material (FM)/oxide system with an enhancedvoltage-controlled magnetic anisotropy (VCMA) effect andsimultaneously large magnetoresistance is an important topicof research in this area.
A second possible route to realize magnetoelectric effectsfor MeRAM is to use single or multi-phase (artificialheterostructure) multiferroic materials [14, 41]. In the case ofmultiferroic heterostructures, a voltage applied to the materialgenerates a mechanical strain in a piezoelectric material. Ifthe ferromagnetic phase has a magnetostrictive property, thestrain will result in an effective magnetic field, which can thenbe exploited to induce switching.
It has been reported that multiferroic heterostructuresoffer larger magnetoelectric coefficients as compared withsingle phase materials. Figure 8 shows an experimentaldemonstration of this principle, where an electric field as smallas ∼0.14 MV m−1 (or 1.4 kV cm−1 applied across a PMT-PTsubstrate) can generate a 90◦ reorientation of a Ni film easyaxis (see figure 8). This experiment demonstrates voltage-controlled reorientation of magnetization, as well as non-volatility—requiring no continuously applied voltage to keepthe magnetization in the reoriented state, thus demonstratingan electric field controlled non-volatile magnetic memoryoperation. The read-out operation of this kind of memoriescould still be performed via the GMR or TMR effects, asproposed in [14, 56]. However, implementation of MeRAMarrays based on this device will require addressing challengesin terms of integration of multiferroic materials and oxideswith CMOS processing. Moreover, the energy dissipation inthis scenario also includes the piezoelectric hysteresis (poling)energy loss, as well as the large capacitance due to the increaseddielectric constant of the piezoelectric.
3.2. Giant spin Hall-based MTJ devices
Recently, it was demonstrated that a current flowing througha metallic layer with large spin–orbit coupling, such as Ta
Figure 8. Experimental evidence of voltage control ofmagnetization for a 30 nm magnetostrictive Ni film deposited on apiezoelectric PMN-PT substrate. By measuring the state of themagnetic film using the magneto-optical Kerr effect (MOKE), it isshown that a 90◦ reorientation of the easy axis can be observed withfields ∼0.14 MV m−1 (or 1.4 kV cm−1). This experimentdemonstrates voltage-controlled reorientation of magnetization, aswell as non-volatility—requiring no continuously applied voltage tokeep the magnetization in the reoriented state, thus demonstrating anelectric field controlled non-volatile magnetic memory operation.(Reprinted with permission from [14]. Copyright 2011, AmericanInstitute of Physics.)
adjacent to a CoFeB free layer, can generate a spin currentthrough the MTJ (via the giant spin Hall effect), which is largeenough to induce switching in the device [16]. The devicestructure is shown in figure 9, where the electrical current JC
flowing between terminals A and C induces a spin currentJS = θSHJC through the MTJ device, where θSH is referred toas the spin Hall angle. Note that the direction of the currentJC will also control the spin polarization of JS and therefore,the switching direction will be determined by the sign of JC.Using the β-phase of Ta, the spin Hall angle θSH can be aslarge as ∼12% without further increase in the damping of theadjacent CoFeB free layer [16]. However, it has also beendemonstrated that the spin Hall angle can be as large as 30%in tungsten [57], comparable to the spin-current-efficiency forregular two terminal MTJ devices (η ∼ 60%).
Although this three-terminal device potentially resultsin a penalty in terms of density as compared with a two-terminal MTJ, it also offers advantages, which address specificchallenges of STT-RAM. First, the switching current densityrequired to switch the MTJ can be tuned by engineering thedimensions of the metal (e.g. Ta) wire, without disturbing the
8
J. Phys. D: Appl. Phys. 46 (2013) 074003 K L Wang et al
Figure 9. Three-terminal device configuration exploiting the giantspin Hall effect in β-Ta/CoFeB [16]. By running a current JC
through the tantalum wire (between terminals A and C), a pure spincurrent JS through the MTJ is induced, which can be used forswitching the free layer. The spin polarization of the spin current JS
will depend on the direction of JC. One of the advantages of thisthree-terminal configuration is that the required current density canbe tuned by engineering the lateral area of the wire ATa, while AMTJ
can be designed to account for a given thermal stability factor.
thermal stability of the MTJ. In particular, the ratio of theswitching current due to spin Hall (ISH) to the required currentfor STT (ISTT) can be approximated by
ISH
ISTT≈ η
θSH
ATa
AMTJ, (5)
where ATa and AMTJ are the cross-sectional area of theunderlying metal layer, and the MTJ device, respectively (seefigure 9). Thus, considering that the area of the metal layer(interconnect) ATa could be engineered to be as much as oneorder of magnitude smaller as compared with AMTJ by reducingits thickness to <5 nm, the switching current can be loweredby nearly one order of magnitude compared with STT-basedswitching. Second, the read (terminal B to A or C in figure 9)and write paths (A to C) would be separated, allowing disturb-free read operations. Finally, in terms of switching energy,the smaller switching current would flow through a lowerresistance metallic wire (e.g. ∼0.3 � µm2 for a L = 200 nm Tawire as compared with an MTJ), leading to switching energylevels on the order of CMOS devices (∼1 fJ). However, theneed for ultrathin metal interconnects can limit the overall sizeof memory arrays in this approach, given the high resistanceassociated with them.
4. Conclusions
The intrinsic properties of spin-based systems make themadvantageous as a prospective candidate for fast, dense andenergy efficient non-volatile memory devices. STT-RAM,where a spin-polarized current is used to manipulate themagnetization state of an MTJ, has become one of the emergingcandidates particularly for embedded memory, since it can bedirectly integrated with CMOS, matching or outperformingSRAM, DRAM or Flash in most respects (except for density).The compatibility of CMOS and STT-RAM could spur
new paradigms for non-volatile computation. Even so, thefuture scalability of STT-RAM is limited by its current-based mechanism and also relies on the development of novelmaterials with higher perpendicular anisotropies and lowerdamping. However, the recent demonstration of the giantspin Hall effect in Ta/CoFeB interfaces provides an attractivealternative for reduction in the switching current, opening apossible path for lowering the energies required for current-based switching.
Alternative voltage-based writing mechanisms for MTJsmay also provide a viable route towards switching energiesclose to or smaller compared with CMOS (∼1 fJ). Replacingthe STT-based manipulation of magnetization with voltage-based mechanisms has been predicted to take the switchingenergies to the sub-femto-Joule regime. Two differentprinciples of electric field control of magnetism werediscussed, namely, voltage control of interface anisotropy(VCMA) and multiferroic heterostructures, along withmemory devices based on them, demonstrating magneticswitching and reorientation of the easy axis by electric fields.So far, voltage-induced switching assisted by a magnetic fieldin the thermally activated regime and electric field basedtoggle switching have been demonstrated. Voltage-induced,magnetic field independent switching with improved energyefficiency and similar reliability and read-out characteristicsas compared with STT-RAM, is still to be demonstrated.However, it is expected that these novel mechanisms could leadto a MeRAM, with dramatically higher energy efficiency andscalability than those of purely current-controlled memoriessuch as STT-RAM.
Acknowledgments
This work was supported by the DARPA STT-RAM and NVLogic programs under program manager Dr D Shenoy, and bythe Nanoelectronics Research Initiative through the WesternInstitute of Nanoelectronics.
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