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• Power is dissipation of energy over time
• A device consuming lots of power over a long period of time will dissipate lots of heat
• A device using lots of energy decreases the battery life
Power vs. Energy
2 [Brehob]
About Power:
• High power draws for extended periods of time can produce a lot of heat
• Lots of heat cano melt componentso cause faulty behavioro harm the user
About Energy
• High energy consumption will decrease battery life
• Good battery life will increase portability
Why Do We Care?
3
What Can I Power?
Device/Reference Average Power Consumption
Light Bulb 20-75 Watts [1]
Smartphone (CPU) 50-400 mW (12-60 mW) [2]
Hearing Aid, Calculator Microwatts [3]
2 AA batteries can power a cheap calculator for several years
[1] My House[2] "An Analysis of Power Consumption in a Smartphone". Aaron Carroll, Gernot Heiser. NICTA, University of New South Wales, Open Kernel Labs[3] http://en.wikipedia.org/wiki/Watt#Multiples
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• Increase functionality, decrease power consumption
o Performance increases -> increase power
o Nvidia Tegra (Kal-El)
o University of Michigan's Phoenix processor
Challenge in Industry
5
• Nvidia Kal-El, also known as the Tegra processor is a quad core system on a chip developed for mobile applications
• Multicores excel inachieving betterpower toperformance than single cores
Nvidia Kal-El
6
[C]
• Kal El runs a companion core that runs background processes at low frequency and power
• Extends battery life!
Background Processes
7
[E]
• Main cores (fast ARMCoretex A9s) are enabled one by one for highperformance applications
• Core switchinginvisible to apps
• Disabling coreswhen not neededsaves energy
Nvidia Kal-El
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[E]
• Designated cores for media processing can also be disabled when not needed to save power
• Each media core is designed to do only one task as efficiently as possible
Nvidia Kal-El
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[E]
• How does a slower core save power?
• Narrower Gates =
o Less gate capacitance
o Lower saturation current
• Architects make atrade off between thetwo to achieve the clock speed andpower consumptiondesired from the device
EECS 312 Mumble Mumble....
10
[Sylvester]
• Stage Skip Pipeline
• Used during loops to skip instruction fetched and decodes by using a Decoded Instruction Buffer (DIB)
EECS 370 Mumble Mumble...
11
[B]
• Collapsable Pipelines
• High performance = shorter stages, faster clock
• Lower power = longer stages, slower clock
EECS 370 Mumble Mumble...
12
[A]
• Companion Core - Low Leakage Current
• Main Cores - Higher Leakage Current, Power Gated
• Cores switch at optimal time
Nvidia Kal-El Power / Performance
13
[E]
• Developed by PhD students at University of Michigan as an embedded systems processor specializing in extremely low standby powero Mingoo Seok, Scott Hanson, Yu-Shiang Lin, Zhiyoong Lee,
Nurrachman Liu, with Dennis Sylvester and David Blaauw
• Goal was to build a very small processor with a very long battery life
• Relies on aggressive power gatingto minimize sleep power
Phoenix: a 30 pW Processor
[h]
14
• Phoenix uses ~300nW in
active mode and 29.6 pW
in sleep mode
• Meant for embedded
systems that spend most of
their time in sleep mode
• ~20ms of active time vs.
10 minutes of sleep time
Phoenix: a 30 pW Processor
[h][MS Paint]
15
• Essentially, you use a transistor as a switch, cutting off sections you aren't using
• Sizing is very important to consider....
Power Gating
[j]
16
• Can power gate: o ROMo Arithmetic unitso Logic unitso Non-volatile RAM
• Cannot power gate: o Volatile RAMo Timerso Anything that needs to
preserve state
So what can you power gate?
[h]
17
• Certain processors are better for some systems than for otherso You would never put
this in a phone!
• Note that as you deal
with very low power,
weird things become
importanto In Phoenix, instruction
ROM is used to
supplement now dominant instruction memory
Situational Awareness
[h]
18
•[A]"Stage-Skip pipeline: A Low Power Processor Architecture Using a Decoded Instruction Buffer". 1996. Mitsuri Hiraki, Raminder S. Bajwa, Hirotsuga Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Katsuro Sasaki, Koichi Seki.
•[B]"A Low-Power Processor Architecture Optimized for Wireless Devices". 2005. Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou.
•[C]“The New Era of Tera-Scale Computing” 2009, Shu-ling Garver, Bob Crepps.
•[D] “The Benefits of Quad Core CPUs in Mobile Devices” Nvidia 2011 http://www.nvidia.com/content/PDF/tegra_white_papers/tegra-whitepaper-0911a.pdf
• [E]“Variable SMP –A Multi-Core CPU Architecture for Low Power and High Performance” Nvidia 2011http://www.nvidia.com/content/PDF/tegra_white_papers/tegra-whitepaper-0911b.pdf
References (1)
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Phoenix Processor:
• [h] "The Phoenix Processor: A 30pW Platform for Sensor Applications". 2008. Mingoo Seok, Scott Hanson, Yu-Shiang Lin, Zhiyoong Lee, Nurrachman Liu, Dennis Sylvester, David Blaauw
• [j] "A Low-Voltage Processor for Sensing Applications With Picowatt Standby Mode". 2009. Scott Hanson, Mingoo Seok, Yu-Shiang Lin, Zhiyoong Lee, Nurrachman Liu, Dennis Sylvester, David Blaauw
Power Gating:
• [k] "Power Gating Implementation in SoCs". Charwak Apte. http://nanocad.ee.ucla.edu/pub/Main/SnippetTutorial/PG.pdf
References (2)
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