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SRAM ARCHITECTURE:

ORGANISATION OF STATIC RAM

MOS STATIC RAM MEMORY CELL

BANKED ORGANISATION OF SRAMS

REDUCING VOLTAGE SWINGS ON BIT LINES

REDUCING POWER IN WRITE DIVIDERCIRCUITS

REDUCING POWER IN SENSE AMPLIFIERCIRCUITS

METHOD FOR ACHIEVING LOW COREVOLTAGES FROM A SINGLE SUPPLY

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PULSED WORD LINES

To limit the bit line voltage discharge, it is

sufficient to enable word lines for precisely the

time needed to develop the bit cell voltage

discharge. A circuit that accomplishes this using a pulse

generator is shown in the below fig.

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This circuit gates the word line and the sense

amplifiers by a pulse generated using delay cells .

While the technique is fairly simple, it has the

disadvantage that it does not track the actual

operation of the sense amplifiers.

A designer needs to estimate the actual access

time of the RAM and insert a sufficient margin todetermine the worst-case pulse width.

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SELF TIMING THE RAM CORE

In general, the speed of access to various rows is

not identical.

Clearly the rows closest to the sense amplifiers

should give the fastest access times. Similarly columns closest to the word line drivers

are enabled first.

To utilize a pulsed word line to its best

advantage, we should tailor the width of thepulse according to the access time of the RAM.

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The technique for achieving this uses a "dummy

column" in the RAM to time the flow of signalsthrough the core.

A dummy column is an additional column of bit

cells, sense amplifier, and support circuit placed

at the side farthest from the word drivers.

Bit cells in the dummy column are forced to a

known state by shorting one of the internal nodes

to a given voltage.

The circuit that accomplishes the pulse

generation is shown in the below fig.

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CIRCUIT THAT ACCOMPLISHES THE

PULSE GENERATION

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The sequence of operations that occurs is as

follows: The SR flip-flop is set and the word line is

triggered. Cells along the row are enabled with

the dummy column being the last cell enabled.

By the time the sense amplifier corresponding to

the dummy cell generates a high signal, the rest

of the columns would have been sensed.

The high signal from the sense amplifier resets

the SR flip-flop and turns off the word line.

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This method handles the case of non uniform

access time across rows

The dummy column often adds insignificant

overhead to the entire RAM.

Consequently it is often a preferred technique

for pulsing the word line.

This circuitry is also at time termed word line kill

circuitry.

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PRECHARGE VOLTAGE FOR BIT

LINES

SRAMs employ one of two forms of precharge

techniques.

The first technique uses a static load formed by a

MOS device functioning as a resistive load cell.Enhancement mode NMOS devices operating in

their active region, depletion mode NMOS, or

standard PMOS devices operating in the

saturation region are employed.

The second technique clocks the precharge cir-

cuitry to ensure that precharge occurs when the

core is not being accessed.

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It should be apparent that the clocked technique

avoids static power consumption at the expense

of power required to drive the clocked precharge.

Which method is more advantageous can only be

determined on a case-by- case basis.

Reducing the precharge voltage clearly reduces

the power consumption, since the effective

voltage swings on bit lines is reduced. We wouldexpect precharge through enhancement mode

NMOS devices to be more effective from a power

viewpoint, since the bit line voltage rises to at

most Vcc Vtn.

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While it would be reasonable to assume that

setting the precharge voltage to Vcc/2 would be

optimal, since the voltage swings would beminimal, it may not be practically feasible

because of the structure of the bit cell.

We should remember that a read operation

activates the access transistors of the SRAM cell,

which leads to the internal nodes of the bit cell

being forced toward the bit line voltage.

The relatively large NMOS in the cell prevents

the internal nodes from rising high.

However, a bit line precharged to a low enoughvoltage (lower than Vcc Vtp) forces internal

nodes of the cell low.

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This is counteracted by the PMOS in the cell,

whose drive is very small .

We can then foresee a situation where the readoperation destroys the old data held in the CELL.

It is this factor that limits the reduction of the

precharge voltage.

A reduced aspect ratio may be used due to the

reduced precharge voltage

This results in cell size reduction. It is possible to

get over the above problem of reads corrupting

the cell state by employing different voltages on

the word line for read and write.

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REDUCING POWER IN THE WRITE

DRIVER CIRCUITS

In this section we shall tackle the problem of reducing

power consumption of write driver circuitry, namely,

(1) the word line drivers and

(2) word line decoders. The write driver, being large, because of the need for

driving long, heavily loaded word lines, contributes to

the overall power to a small extent, since at most one

of the drivers is activated at a time.

As opposed to power reduction techniques describedpreviously, which attempt to reduce voltage, write

circuits often have supply voltages determined by

other factors.

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Word line drivers are usually simple buffers

designed to fit in the row pitch of a memory cell.

Little opportunity for power optimization ispresent in these circuits.

In general, we would prefer row decoding to be as

fast as possible, since it directly affects access

time for a RAM.

While there exists a huge variety of row decoder

structures, we shall restrict our attention to two

of the most common forms,

(1)the NOR-type decoder and

(2)the NAND-type row decoder.

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DOMINO NAND DECODER

A NAND decoder changes the output of the decoder along one row.

Its structure is shown in the below fig

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NOR DECODER

A NOR decoder activates the outputs of all but one row.

Its structure is shown in the below figure

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REDUCING POWER IN SENSE AMPLIFIER

The function of the sense amplifier is to amplify

small differential bit line voltages into logic

levels.

This operation should be performed as fast aspossible.

While numerous sense amplifiers exist, some of

the common forms employed for SRAMs are

either

(1)simple differential amplifiers or

(2) charge amplifiers that are similar to bit cells.

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Sense amplifiers are enabled by a sense amplifier

enable signal.

Schemes employed for reducing the power

requirements of sense amplifiers can be

differentiated based upon the point at which they

are activated. The first form limits sense amplifier currents by

precisely timing the activation of the sense

amplifier for just the period required.

The second scheme employs sense amplifiers thatautomatically cut off after the sense operation.

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The enable sense amplifier signal is used to set

up an SR flip-flop in the set state. Once the dummy sense amplifier has finished

sensing, it resets the SR flip-flop, which in turn

disables the enable for the sense amplifiers.

We rely on every sense amplifier havingcompleted the sense action before the dummy

sense amplifier.

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MULTI STAGE DECODER