Low Power VLSI Circuit Synthesis: Introduction and …apal/LPC_2009/lpc1.pdf · Low Power VLSI...

Low Power VLSI Circuit Synthesis: Introduction and Course Outline

Ajit Pal

ProfessorDepartment of Computer Science and

EngineeringIndian Institute of Technology Kharagpur

INDIA -721302

Ajit Pal IIT Kharagpur

Agenda

Why Low Power?Low Power Design methodologyCourse Outline


Why Low-power?Until recently performance has been synonymous with circuit speed or processing power, e.g. MIPS or MFLOPS.Implementation involved Area-Time tradeoff. Power Consumption = k.A.f, where k= 0.063 W/cm2.MHz, A is the area in cm2 and f is the frequency in MHz.Power consumption were of secondary concern.

Why Low-power?Contemporary high performance processors consume heavy powerCost associated with packaging and cooling such devices is prohibitiveLow-power methodology to be used to reduce cost of packaging and cooling

ProcessorClock(MHz)

Technology(mm)

Vdd(Volt)

Peak Power(Watt)

Ultra Sparc 167 0.45 3.3 30

Intel Pentium 200 0.50 3.3 26

Alpha 21064 200 0.50 3.3 30

Alpha 21164 300 0.45 3.3 50

Alpha 21264 667 0.35 2.0 72

Alpha 21364 1000 0.25 1.5 100


Processor Power


Why Low-power?


Why Low-power?Emergence of portable computing and communication equipment, such as laptops, palmtops, cell-phones, etc. Growth rate of these portable equipment are very high.As these devices are battery operated, battery life is of primary concern. Unfortunately, the battery technology has not kept up with the energy requirement of the portable equipment.Commercial success of these products depend on weight, cost and battery life.Low power design methodology is very important to make them commercially viable.


Why Low-power?Reliability is closely related to power dissipation – Every 10ºC rise in temperature roughly doubles the failure rate

0 100 200 300

Thermal runway

Silicon interconnect fatiguePackage related failure

Electrical parameter shiftElectromigration diffusion

Junction diffusionGate dielectric

oC above normal operating temperature

Onset temperatures of various failure mechanism


Why Low-power?According to an estimate of the U.S. Environmental Protection Agency (EPA), 80% of the power consumption by office equipment are due to computing equipment and a large part from unused equipmentPower is dissipated mostly in the form of heat. The cooling techniques, such as AC transfer the heat to the environment.To reduce adverse effect on environment efforts such as EPA’s Energy Star program leading to power management standard for desktops and laptops has emerged.Drive towards Green PC


Low-Power Design MethodologyLow-power design methodologies are to be applied throughout the design process from system-level to layout-level, gradually refining or detailing the abstract specification or model of the design. Starting with the system specification the following steps are performed to get the layout:

System Specification =>System-level DesignBehavioral Description => High-level SynthesisStructural RTL Description => Logic SynthesisLogic-level netlist => Layout Synthesis => Layout


Example: Bar Code ScannerSystem specification

Behavioraldescription

Structural RTLdescription

SYSTEM-LEVEL DESIGNHW/SW allocation/partitioning

Selection of processor(s)Communication mechanism

HIGH-LEVEL SYNTHESISTransformations

SchedulingModule selectionClock selection

Resource sharingRTL optimizations

ARCHITECTURE algorithm OF barcode IS Pre_proc:PROCESS BEGIN . . . . . . LOOP IF video = wh THEN white := white + 1; IF falg = bl THEN . . . . . . flag = wh; black := 0; data <= white; ELSE black := black + 1; . . . . . flag := bl; white := 0; data <= black; END IF; addr <= actnum; EXIT WHEN (white = limit) OR (black = limit) END LOOP; . . . . . . END algorithm;

Camera Pre-processor

Memory

Microprocessor

Scan

Video

eoc

Start

Addr

Data

Mem_read

addr

data

BARCODE SCANNERMem_write


Example: Bar Code Scanner

0 1

0 1

white

incre2

0 1 0 1

0 1

data

0 1

= = =

0 1 0 1

Next StageLogic

DecodeLogic

m2 m1

m1

m6

m12m13

m21

m22

m14

flagblack

black

zero zerozero

zerolimitlimit

white

white

whitewh bl

m24

Structural RTLdescription

Logic levelnetlist

Layout

LOGIC-SYNTHESISTwo-level, multi-level synthesis

State assignmentRetiming

Technology mapping

LAYOUT-SYNTHESISPlacement. RoutingGate and wire sizing

Clock distributionPower supplydistribution


System-level DesignAt the system level, the design may be modeled as a set of abstract communicating processes or tasksThe tasks may be implemented either in hardware or compiled into software running on an embedded processorSystem-level synthesis involved partitioning the tasks into hardware and software, choosing the processors that will execute the software, determining the hardware/software communication mechanism, etc. This step will involve hardware/software tradeoff. Example: Use of VLIW Architecture instead of Superscalar ArchitectureThe software component go through the software implementation steps, not to be covered in this courseDynamic voltage scaling


Architecture-level SynthesisThe hardware part to be implemented is represented by behavioral or algorithmic descriptionsHigh-level synthesis converts a behavioral description into a structural RTL implementation, which is represented as an interconnection of macroblocks and random logic.This step involves scheduling of operations to different cycles of execution and allocation to the available hardware resources.Low-power design methodologies, such as power management, parallelism, pipelining, reduction of the number of global busses, etc can be adopted.Techniques like loop unrolling, loop folding are used to reduce energy requirements


Logic SynthesisThe macroblocks can be directly fed to the logic synthesis step, where as the random logic part is converted into logic-level netlist by the logic synthesis phase in two steps.The first step transforms into technology-independent logic-level netlist, which is mapped into a semi-custom technology library.At this level, low-power techniques, such as reduction of switching activity, use of suitable logic family, use of multiple power supply, use of multiple threshold voltages, use of encoding for sequential circuits, clock gating, etc are used.


Layout SynthesisLayout synthesis is also carried out in a hierarchical framework, each stage is optimized, while making the problem manageable to the subsequent steps.Typically the following substages are involved:

Partitioning: It divides a circuit in smaller stepsFlooreplanning: It determines the approximate location of each module in a rectangular chip areaPlacement: It determines the best position of each moduleRouting: To provide interconnections among various modules. It is usually done in two steps; global routing followed by detailed routing



Course Outline: Background Material1. Basics of MOS Transistors (3):

Fabrication steps of a MOS TransistorStructure of MOS TransistorsThe Fluid ModelMOS Capacitor modelMOS Transistor modelElectrical Characteristics of MOS transistors Threshold VoltageBody EffectChannel Length ModulationTransistor TransconductancenMOS Transistor as a switchpMOS Transistor as a switch Transmission gateTransmission gate driving a large capacitive loadTransmission gate driving a small capacitive load


Course Outline: Background Material2. MOS Inverters (5):

Generic MOS inverterTransfer CharacteristicsNoise marginPassive resistor as pull-up devicenMOS depletion mode transistor as pull-upnMOS enhancement mode transistor as pull-uppMOS transistor as pull-upCMOS inverterVoltage-current characteristicsTransfer CharacteristicsNoise margin of CMOS inverterSwitching characteristics of CMOS inverterDriving Large Capacitive Loads

Super buffersBiCMOS Inverter

Buffer Sizing


Course Outline: Background Material

3. MOS Combinational Circuits (4)Pass transistor LogicGate Logic CMOS Circuit Realization Switching characteristics CMOS complex logic gatesMOS Dynamic Circuits Example Combinational circuits


Course Outline: Background Material4. Sources of Power dissipation (2):

Static Power Dissipationi. Diode Leakage Powerii. Subthreshold Leakage Poweriii. Leakage power DSM circuits

Dynamic Power Dissipationi. Short Circuit Powerii. Switching Poweriii. Glitching Power

Degrees of Freedom


Course Outline: Low-Power Techniques

5. Supply Voltage Scaling Approaches (5):Device feature size scalingMulti-Vdd CircuitsArchitectural level approaches: Parallelism, PipeliningVoltage scaling using high-level transformationsDynamic voltage scalingPower Management



6. Switched Capacitance Minimization Approaches (5):

Hardware Software TradeoffBus Encoding

Two’s complement Vs Sign MagnitudeArchitectural optimization TechniquesClock GatingPossible Logic styles


7. Leakage Power minimization Approaches (4) :Realization of Multithreshold CircuitsVariable-threshold-voltage CMOS (VTCMOS) approach Multi-threshold-voltage CMOS (MTCMOS) approach Dual-Vt assignment approach (DTCMOS)Transistor stacking

8. Special Topics: Adiabatic Switching Circuits (1)Battery-aware Synthesis (1)Variation Tolerant Design (1)



ReferencesText/Reference Books:

T1: Sung_Mo Kang, Yusuf Leblebici, CMOS Digital Integrated Circuits, Tata Mcgrag Hill T2: Neil H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design, 2nd Edition, Addison Wesley (Indian reprint).T3: A. Bellamour, and M. I. Elmasri, Low Power VLSI CMOS Circuit Design, KluwerAcademic Press, 1995R1: Anantha P. Chandrakasan and Robert W. Brodersen, Low Power Digital CMOS Design, Kluwer Academic Publishers, 1995R2: Christian Piguet (Ed.), Low-Power CMOS Circuits: Technology, Logic Design and CAD Tools, Tayler and Francis (CRC), 2006


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