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TRENDSIN LOW

POWER VLSI DESIGN

Under the Guidance of

Ms.P.Anitha

G.Shruthi

(12N31D6811)

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OUTLINE

Importance of Low Power VLSI Design

Sources of Power Consumption in CMOS

Power Consumption Considerations

Optimization Metrics Techniques for Power Reduction

Conclusion

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ROAD MAPFOR FEATURE SIZEOF

TRANSISTORS

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IMPORTANCEOF LOW POWER VLSI DESIGN

The potential increase in packing densities as

the feature size of the MOS devices shrinks.

Logic density for the Intel microprocessors doubles

every process generation.

The frequency of operation has dramatically

increased due to the device scaling

Introduction of performance boosting techniques,

such as pipelining, and parallel architectures.

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SOURCESOF POWER CONSUMPTIONIN CMOS

Dynamic Power Dissipation

Short Circuit Power Dissipation Static Power Dissipation

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DYNAMIC POWER DISSIPATION

The Dynamic power dissipation is the power

required for the circuit to perform its anticipated

tasks.

Dynamic Power dominates the total power

consumption.

Pdynamic = CL * Vdd Vdd *

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DYNAMIC POWER DISSIPATION

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SHORT CIRCUIT POWER DISSIPATION

Direct current from Vdd to GND when both

transistors on.

In this PMOS and NMOS devices are

simultaneously Conducting.

Pshort circuit = Isc * Vdd

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STATIC POWER DISSIPATION

The Static power is when input is not switching.

In static power dissipation is very small and can be

ignored.

Pstatic = Istatic * Vdd

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POWER CONSUMPTION CONSIDERATIONS

Supply Voltage level

Device Threshold Voltage

Physical capacitance

Switching Frequency

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OPTIMIZATION METRICS

Performance degradation is acceptable to a

given bound that is represented by performance or

timing constraints.

Thus, power minimization requires optimalexploitation of the slack on performance

constraints.

Besides power versus performance, another key

trade-off in VLSI design involves power versus

flexibility Power minimization

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TECHNIQUESFOR POWER REDUCTION

System Level

Architectural level

Logic Gate Level

Circuit Level Physical level

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SYSTEM LEVEL

System level is the highest level of abstraction

It consist of Hardware infrastructure executing

software programs

Hardware Platform consist ofExecution unit

Storage Unit

Communication interface Network

Software consist ofapplication &system software

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ARCHITECTURALLEVEL

Architectural level is the structural view of data path

and logical view of control Unit.

It consist of parallelism and pipelining Exploitation

In this level when the supply voltage is less theperformance is reduced by half.

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LOGIC GATE LEVEL

The RTL or Behavioral design is transformed into a

logic gate level using predefined technology.

In this technique we are using

CAD toolsPath equalization Technique

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CIRCUIT LEVEL

The low power cell design lies at the heart of the

circuit level technique to reduce the power

consumption.

In this technique we consider

transistor sizing

circuit design style

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POWER CONSUMPTIONREDUCTIONAT

CIRCUITLEVEL

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POWER CONSUMPTIONREDUCTIONATCIRCUIT

LEVELCONTD.

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POWER CONSUMPTIONREDUCTIONAT

CIRCUITLEVELCONTD.

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CONCLUSION

\advances in technology and fabrication, the integration ensities and

the rate at which chips operate have increased drastically, causing

power consumption to be of primary concern. In addition, the new

requirements set by device portability, reliability, and costs have helped in

alleviating the power consumption threat in CMOS circuits. Because the power problem is getting more concerning, very large-

scale integrated circuit (VLSI) designers

need to develop new efficient techniques to reduce the power

dissipation in current and future technologies, a task that is full of

challenges but yet exciting to explore.