Low Resistance Strip Sensors – RD50 Common Project –

RD50/2011-05

CNM (Barcelona), SCIPP (Santa Cruz), IFIC (Valencia)

Contact person: Miguel Ullán

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov 2011 2

Outline

Motivation

Technological challenges

Preliminary experiments

Designs

Status and plan

Summary

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov 2011 3

Motivation In the scenario of a beam loss, a large charge deposition in the

sensor bulk can lead to a local field collapse. A conducting path to backplane is created and implant strip potential

could reach a significant voltage.

Coupling capacitors can get damaged by the voltage difference between the implant and the readout strip They are typically qualified to 100 V

Punch-Through Protection (PTP) structures used at strip end to develop low impedance to

the bias line

Reduce distance from implant to bias ring

Placement of the resistor between the implant and bias rail (“transistor effect”).

Micron

HPK

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov 2011 4

PTP effectiveness at ‘far’ end Measurements with a large charge injected by a

laser pulse showed that the strips can still be damaged

The voltages on the opposite end of the strip keep rising well above the 100V objective

The large value of the implant resistance effectively isolates the “far” end of the strip from the PT structure leading to the large voltages

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Near end, plateaufor PT structures

Opposite end, no plateau.

C. Betancourt, et al. “Updates on Punch-through Protection” ATLAS Upgrade week, Oxford, March 31, 2011.

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov 2011 5

Proposed solution To reduce the resistance of the strips on the silicon sensor.

A desired target value is 1.5 kOhm/cm (~ 1 order of magnitude reduction)

Not possible to increase implant doping to significantly lower the

resistance. Solid solubility limit of the dopant in silicon + practical

technological limits (~ 1 x 1020 cm-3)

Alternative: deposition of Aluminum on top of the implant:

R□(Al) ~ 0.04 /□ 20 /cm

Cross section

Longitudinal section

Top view

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov 2011 6

Technological challenges Metal layer deposition before the coupling capacitance is

defined 2 metals processing

A layer of high-quality oxide/nitride with metal strips on top to

implement the AC-coupled sensor readout (MIM cap).

Deposited (not grown)

Low temperature processing

PTP structure Not tried before at CNM

Very dependent on surface effects (difficult to simulate)

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov 2011 7

Metal on strip Metal layer deposition on top of the implant before the

coupling capacitance is defined.

MIM capacitors Low temperature deposited isolation

– PECVD (300-400 ºC)

– Risk of pinholes (Yield, Breakdown)

– > 50 pF ~ 3000 Å

Alternatives (for high T deposition)

– Polysilicon + TaSi (tantalum silicide)

– Tungsten

Experiments already performed at CNM on smaller

dimensions. More experiments needed.

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov 2011 8

Preliminary experiments 6 wafers batch of MIM capacitors

Different sizes– C1: 1100 x 1100 m2 = 1.20 mm2

– C2: 600 x 600 m2 = 0.36 mm2 – C3: 300 x 300 m2 = 0.09 mm2

– …(short strips ~ 0.5 mm2)

Low-temperature deposited isolation PECVD (300-400 ºC)

Use of a multi-layer to avoid pinholes

3 technological options:

Op1: 3000 Å of SiH4-based silicon oxide (SiO2) deposited in 2 steps

Op2: 3000 Å of TEOS-based oxide deposited in 2 steps (Tetra-Etil Orto-Silicate)

Op3: 1200 Å + 1200 Å + 1200 Å of TEOS-based ox. + Si3N4 + SiH4-based ox.

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov 2011 9

MIM results All 3 options give good MIM capacitors Yield is high even for the largest caps (> 1 mm2)

(Not yet large statistics from all the wafers)

I-V meas: ILEAK < 3 pA @ 20 V for the largest cap (C1)

Capacitance: C(op1) = 122 pF/mm2

C(op2) = 120 pF/mm2

C(op3) = 110 pF/mm2

Breakdown: VBD(op1)|C1 = 170 V

VBD(op2)|C1 = 150 V (low statistics)

VBD(op3)|C1 = 210 V (low statistics)

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov 2011 10

PTP design Reduce implant distance to bias ring to favor punch-through

effect at low voltages

Placement of the resistor between the implant and bias rail

(“transistor effect”).

Compromise between PT effect and breakdown

Design of experiments varying d, p, n (2 indep. variables) Simulations ?

dsp

Bias rail

Polysilicon “bridge/gate”

Implant

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov 2011 11

Test structures Test structure to measure voltage in the implant under laser

injection at different strip distances

Laser tests (SCIPP-Santa Cruz)

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov 2011 12

Wafer mask design DOE for the PT structure Control structures with standard resistive implant structure Test structures Extra structures for “slim edges”

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov 2011 13

Status and Plan Final measurements (more statistics) on MIM experiement

wafers

DOE being planned and test structures designed

Final technological options being defined

Finish designs by end of January 2012

Fabrication (4-5 months): June 2012

Device electrical characterization, PTP validation, laser tests,

Irradiation, re-characterization, post-irrad laser tests…

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov 2011 14

Summary

RD50 Common Project: Low Resistance Strip Sensors (June 2011)

CNM-Barcelona, SCIPP-Santa Cruz, IFIC-Valencia

Reduced resistivity of the strip:

Proposed metal layer on top of the strip implant

MiM coupling capacitor

PTP structures implemented

Preliminary experiments on MIM coupling capacitors:

Good results (yield, large area, ILEAK, C, VBD). More statistics needed

Options to be chosen

DOE on PT structures implemented

Final designs, start fabrication ~January 2012 Samples ~June 2012

This could be a very innovative solution for new generations of long-strip

detectors and with great applications in future HEP experiments.

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