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L.ROYER – TWEPP 2012 @ Oxford – Sept. 2012
The chip
Signal processing for High Granularity Calorimeter
(Si-W Ecal @ ILC)
L.Royer, J.Bonnard, S.Manen, X.Soumpholphakdy
Microelectronics Rhône-Auvergne Group – IN2P3
L.ROYER – TWEPP 2012 @ Oxford – Sept. 20122
The International Linear Collider
(Credit: Greg Stewart, SLAC)
Time structure of the ILC: Bunchtrains of 2820 bunches spaced 337 ns Each bunch train is about 1 ms long No beam during about 199 ms
Activity of the Very Front End Electronics: During the beam activity:
analog signal processing (1ms) A the end of the beam activity:
A-to-D signal conversion (.5ms max) data transfer (.5ms max)
Idle mode during 198ms
about 99% of the time with no activity for electronics on detectors
ILC BEAM STRUCTURE
ILC “could be the next big adventure in particle physics”“It would complement the LHC at CERN and shed more light on the discoveries scientists are likely to make there in the coming years.”
[http://www.linearcollider.org/]
Analog electronics busy
1ms (.5%)
A/D conv..5ms (.25%)
DAQ.5ms (.25%)
IDLE MODE198ms (99%)
L.ROYER – TWEPP 2012 @ Oxford – Sept. 20123
Challenges for the Si-W Ecal
Sandwich structure of thin wafers of silicon diodes & tungsten layers Embedded Very Front End (VFE) electronics
Deeply integrated electronics Minimal cooling available
High granularity : diode pad size of 5x5 mm2
High segmentation : ≈ 30 layers
≈ 100.106 channels
Large dynamic range of the input signal (≈ 15 bits)
« Tracker electronics withcalorimetric performance »
ILC
Cal
orim
eter
s
L.ROYER – TWEPP 2012 @ Oxford – Sept. 2012
Readout Electronics for the Si-W Ecal
4
Specifications of the readout electronics of Ecal:
Dynamic range of the signal delivered by a Si-diode : from MIP (4 fC) to 2500 MIPs (10 pC)
Level of noise limited to 1/10 MIP SNR ≈ 10
Error of Linearity:
< 0.1 % up to 10 % of the dynamic range (1 pC)
< 1% from 10 % and 100 % of the dynamic range (10 pC)
Power budget limited to 25µW per channel
Power Pulsing must be implemented
L.ROYER – TWEPP 2012 @ Oxford – Sept. 2012
First prototype readout channel
5
Some results:
Global Linearity better than 0.1 % (10 bits) up to 9.5 pC
(2375 MIP).
ENC = 1.8 fC (0.5 MIP) with a single gain stage
Power consumption with power pulsing estimated to 25µW
Results published in IEEE TNS (ISSN : 0018-9499)
CSA
Axes of development @ MicRhAu:
Synchronous/clocked (with beam) analog signal processing: reseted-CSA, shaping with Gated
Integrators including the analog memory, latched comparators
Fully differential architecture, except for the Charge Sensitive Amplifier (CSA)
One low-power ADC attached to each channel (12-bit cyclic ADC)
Use of a pure CMOS technology, no bipolar transistors (low cost AMS CMOS 0.35 techno.)
Cyclic ADC
L.ROYER – TWEPP 2012 @ Oxford – Sept. 2012
The CALOrimetry Readout Integrated Circuit (1/4)
6
Low noise CSA Low-gain shaper 12-bits cyclic ADC
ADC4
Based on the previous validated prototype, a new chip designed
Technology AMS CMOS 0.35 µm
Architecture of CALORIC based on the previous channel tested, with some improvements:
Reduction of the power consumption of the CSA
Reduction of the noise of the amplifier of the Gated Integrator
Increase of the analog memory depth to 16
Chip fully power pulsed
L.ROYER – TWEPP 2012 @ Oxford – Sept. 20127
A High-Gain (about x 20) channel added to improve the SNR at low energy
A discriminator indicates the dynamic range of the signal select the signal to be converted
Low noise CSA Low-gain shaper 12-bits cyclic ADC
ADC4
x16
The CALOrimetry Readout Integrated Circuit (2/4)
High-gain shaper
Gain discri.x16
Threshold
L.ROYER – TWEPP 2012 @ Oxford – Sept. 20128
Low noise CSA Low-gain shaper 12-bits cyclic ADC
ADC
High-gain shaper
4
Gain discri.
Analog part
High-gain shaperAmplifier
x5
Trigger discri.
x16
x16
A Trigger channel added to auto-select events over the MIP
The trigger signal determinates if the active memory cell is reset or the signal kept into memory
The CALOrimetry Readout Integrated Circuit (3/4)
Threshold
L.ROYER – TWEPP 2012 @ Oxford – Sept. 20129
Digital Block(State Machine)
12
Outputdata
Control of the channel
Low noise CSA Low-gain shaper 12-bits cyclic ADC
ADC
High-gain shaper
4
High-gain shaperAmplifier
x5
Gain discri.
Trigger discri.
Thresholds
Analog part
x16
x16
A digital block controls the chip
The CALOrimetry Readout Integrated Circuit (4/4)
L.ROYER – TWEPP 2012 @ Oxford – Sept. 2012
Global State Machine
10
IDLE
Analog signalprocessing
WAIT for 198 msNo power
1 ms max.Up to 16 events stored
Time conversion < 1 msA/D conversion
x events stored
End of the bunch trains
DAQ(not implemented)
All events converted
Bunch Crossing
Wake Up
Master clock of 20 MHz (period of 50 ns)
At the end of idle time, digital state machine wakes up and is ready to manage new events.
Analog electronics busy
1ms (.5%)
A/D conv..5ms (.25%)
DAQ.5ms (.25%)
IDLE MODE198ms (99%)
L.ROYER – TWEPP 2012 @ Oxford – Sept. 2012+ 350 ns: ready to process next event11
Timing of the analog processing
t = 0 ns: bunch crossing (event synchronous w/ beam)
+ 200 ns: activation of the trigger comparator
+ 250 ns: activation of the gain comparator
+ 300 ns: end of integration: reset or memorization
Output signal of the CSA
Output signal of the trigger channel
Output signal of high-gain channel
Output signal of the low-gain channel
Signal delivered by the Si-diodeBunch period = 350 ns
L.ROYER – TWEPP 2012 @ Oxford – Sept. 2012
Layout of CALORIC_1ch
12
Gated Integrator and the 2x16 memory
cells
CSA, trigger channel and comparators
The cyclic ADCThe digital block
Channel area in AMS 350nm : 1.2 mm²
L.ROYER – TWEPP 2012 @ Oxford – Sept. 201213
Main Performance of Caloric_1ch
Most functionalities are validated: charge is
collected, converted to voltage, amplified,
filtered, memorized and digitally converted; the
digital block manages well the sequencing of the
signal processing
Trigger channel non-functional signal
dominated by noise (digital signals) and too large
offset
Bug on the routing of power pulsing signal
ENC (rms value) with CD=30 pF: 0.6 fC (3750 e-)
MIP-to-noise ratio 6
Integral Non-Linearity:
< 0.2% up to 0.4 pC
< 1% from 1 pC to 6 pC
Gain dispersion for 16 memory cells :
1.5% (rms value) the low-gain
2.5% for the high-gain
Results published in IEEE TNS (ISSN : 0018-
9499)
ENC= 0.6 fC
L.ROYER – TWEPP 2012 @ Oxford – Sept. 2012
Power consumption of Caloric_1ch
14
CSA
Trigger channel
Low Gain channel
High Gain channel
Evaluation using power pulsing with the ILC duty cycle: 43 µW/channel
L.ROYER – TWEPP 2012 @ Oxford – Sept. 201215
4-channel chip designed Power pulsing bug corrected New amplifier for the trigger channel less sensitive to process& mismatch
fluctuations Gated integrator: Time-variant system Noise simulations performs both with
transient noise and periodic noise tools from Cadence Results in accordance (difference < 10%)
MIP/noise=10 for trigger channel
Caloric_4ch (1/3)
Threshold voltage
Simulated noise: MIP/10Output signal of the trigger channel on MIP event vs process/mismatch fluctuation
Spectral density of the noise for the trigger channel
L.ROYER – TWEPP 2012 @ Oxford – Sept. 201216
Shapers & ADC fully differential to reduce sensitivity to common-mode noise
Few “common sense rules” implemented for the layout to minimize noise coupling:
Analog and digital blocks isolated from one another with free-space and p+ guard rings
Analog and digital blocks with own independent power supply
Complementary signals for clock to minimize injection to analog signals
Several Pads per each power supply to reduce the inductance of bounding wiring
On-chip decoupling capacitors
Sensitive analog signal lines far away from perturbing lines
Digital pads with high toggle rate placed far from analog domain
Package have to be carefully chosen
Minimizing noise coupling from the digital part to the analog part
MIP/10 = 0.4fC equivalent to a voltage step of 3.3V on a 0.12 fF capacitor !!
Caloric_4ch (2/3)
L.ROYER – TWEPP 2012 @ Oxford – Sept. 201217
(2.7 x 2.7) mm2
Submission to the next AMS run in November
Channel 1
Channel 4
Channel 2
Channel 3
Decoupling capacitors
Caloric_4ch (3/3)
L.ROYER – TWEPP 2012 @ Oxford – Sept. 2012
Conclusion
We have designed a pure CMOS–differential-synchronous readout electronics dedicated to the Si-W
Ecal of ILC.
All the functionalities have been tested and most are validated: amplification, filtering, memorizing, A-to-D
conversion, global state machine for sequencing.
But two main functionalities are missing: the auto-triggering and the power pulsing. They will be tested
with Caloric-4ch.
This work shows the difficulties to detect and process very small charge (<1fC) inside a mixed
analog/digital chip. A technology with higher resistivity substrate (BFMOAT with 130nm IBM RF
technology) should be better suited for mixed-signal design.
Power consumption must be divided by a factor 2 to reach requirements of ILC. It is not a trivial issue but
improvements must be focused on the amplifiers.
This development provides us successful experiences in the design of low noise CSA, time-variant
filtering, A-to-D converters, mixed chip, ….
This experience will be useful for the present and future projects @ MicRhAu.
18THANK YOU !