LTC5584
15584f
Typical applicaTion
FeaTures DescripTion
30MHz to 1.4GHz IQ Demodulator with IIP2 and
DC Offset Control
The LTC®5584 is a direct conversion quadrature demodu-lator optimized for high linearity receiver applications in the 30MHz to 1.4GHz frequency range. It is also usable in the 10MHz to 30MHz and 1.4GHz to 2GHz ranges with reduced performance. It is suitable for communications receivers where an RF signal is directly converted into I and Q baseband signals with bandwidth of 530MHz or higher. The LTC5584 incorporates balanced I and Q mix-ers, LO buffer amplifiers and a precision, high frequency quadrature phase shifter. In addition, the LTC5584 provides four analog control voltage interface pins for IIP2 and DC offset correction, greatly simplifying system calibration.
The high linearity of the LTC5584 provides excellent spur-free dynamic range for the receiver. This direct conversion demodulator can eliminate the need for intermediate fre-quency (IF) signal processing, as well as the corresponding requirements for image filtering and IF filtering. These I/Q outputs can interface directly to channel-select filters (LPFs) or to baseband amplifiers.
Direct Conversion Receiver with IIP2 and DC Offset Calibration
applicaTions
n I/Q Bandwidth of 530MHz or Highern High IIP3: 31dBm at 450MHz, 28dBm at 900MHzn High IIP2: 70dBm at 450MHz, 65dBm at 900MHzn User Adjustable IIP2 to >80dBmn User Adjustable DC Offset Nulln High Input P1dB: 13.1dBm at 900MHzn Image Rejection: 45dB at 900MHzn Noise Figure: 9.9dB at 450MHz 10dB at 900MHzn Conversion Gain: 5.4dB at 450MHz 5.7dB at 900MHzn Shutdown Moden Operating Temperature Range (TC): –40°C to 105°Cn 24-Lead 4mm × 4mm QFN Package
n LTE/W-CDMA/TD-SCDMA Base Station Receiversn Wideband DPD Receiversn Point-To-Point Broadband Radiosn High Linearity Direct Conversion I/Q Receiversn Image Rejection Receivers
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
A/D
D/A
D/A
VGA
VGA
5584 TA01a
LPFRF+
RF–
BPFLNABPF RFINPUT
LO
EN
LO INPUT
ENABLE
LPF
IP2 ADJUST
DC OFFSET
I+
I–
Q+
Q–
0°
90°
IP2 AND DCOFFSET CAL
LTC5584
VCC
5V
IP2 ADJUST
DC OFFSETIP2 AND DCOFFSET CAL
D/A
D/A
A/D
IIP2 vs IP2I, IP2Q Trim Voltage
IP2I, IP2Q (V)0
IIP2
(dBm
)
90
100
110
0.8 0.9
5584 TA01b
80
70
500.2 0.4 0.60.1 1.00.3 0.5 0.7
60
130
120
I, –40°CI, 25°CI, 85°CI, 105°C
Q, –40°CQ, 25°CQ, 85°CQ, 105°C
fRF = 450MHz
LTC5584
25584f
pin conFiguraTionabsoluTe MaxiMuM raTings
VCC Supply Voltage ................................... –0.3V to 5.5VVCAP Voltage .................................................VCC ±0.05V I–, I+, Q+, Q–, CMI, CMQ Voltage ........2.5V to VCC + 0.3VVoltage on Any Other Pin .................–0.3V to VCC + 0.3VLO+, LO–, RF+, RF– Input Power ...........................20dBmRF+, RF– Input DC Voltage ........................ –0.3V to 2.7VMaximum Junction Temperature (TJMAX) ............. 150°COperating Temperature Range (TC) (Note 3) .................................................. –40°C to 105°CStorage Temperature Range .................. –65°C to 150°C
(Note 1)
24 23 22 21 20 19
7 8 9
TOP VIEW
25GND
UF PACKAGE24-LEAD (4mm × 4mm) PLASTIC QFN
10 11 12
6
5
4
3
2
1
13
14
15
16
17
18IP2Q
DCOQ
DCOI
IP2I
RF+
RF–
CMQ
VCAP
LO–
LO+
GND
GND
REF
I+ I– Q+ Q– CMI
EN
GND
V BIA
S
V CC
EDC
EIP2
TJMAX = 150°C, θJC = 7°C/W
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
elecTrical characTerisTics TC = 25°C, VCC = 5V, EN = 5V, EDC = EIP2 = 0V, REF = IP2I = IP2Q = DCOI = DCOQ = 0.5V, PRF = –5dBm (–5dBm/tone for 2-tone IIP2 and IIP3 tests), PLO = 6dBm, unless otherwise noted. (Notes 2, 3, 5, 6, 9)
orDer inForMaTionLEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC5584IUF#PBF LTC5584IUF#TRPBF 5584 24-Lead (4mm x 4mm) Plastic QFN –40°C to 105°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts.For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSfRF(RANGE) RF Input Frequency Range (Note 12) 30 to 1400 MHzfLO(RANGE) LO Input Frequency Range (Note 12) 30 to 1400 MHzPLO(RANGE) LO Input Power Range (Note 12) 0 to 10 dBmfRF1 = 140MHz, fRF2 = 141MHz, fLO = 130MHz, L6 = 68nH, C19 = 8.0pF, L5 = 82nHfRF(MATCH) RF Input Frequency Range Return Loss > 10dB 95 to 190 MHzfLO(MATCH) LO Input Frequency Range Return Loss > 10dB 105 to 180 MHzGV Voltage Conversion Gain Loaded with 100Ω Pull-Up (Note 8) 5.7 dBNF Noise Figure Double-Side Band (Note 4) 9.9 dBNFBLOCKING Noise Figure Under Blocking Conditions Double-Side Band, PRF = 0dBm (Note 7) 15.5 dBIIP3 Input 3rd Order Intercept 33 dBmIIP2 Input 2nd Order Intercept Unadjusted, EIP2 = 0V 70 dBmIIP2OPT Optimized Input 2nd Order Intercept EIP2 = 5V, IP2I, IP2Q Adjusted for Minimum IM2 80 dBmP1dB Input 1dB Compression 12 dBmDCOFFSET DC Offset at I/Q Outputs Unadjusted, EDC = 0V (Note 13) 1.5 mV∆G I/Q Gain Mismatch 0.02 dB
∆φ I/Q Phase Mismatch 0.2 Deg
LTC5584
35584f
elecTrical characTerisTics TC = 25°C, VCC = 5V, EN = 5V, EDC = EIP2 = 0V, REF = IP2I = IP2Q = DCOI = DCOQ = 0.5V, PRF = –5dBm (–5dBm/tone for 2-tone IIP2 and IIP3 tests), PLO = 6dBm, unless otherwise noted. (Notes 2, 3, 5, 6, 9)SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSIRR Image Rejection Ratio (Note 10) 53 dBLO-RF LO to RF Leakage –85 dBmRF-LO RF to LO Isolation 74 dBfRF1 = 450MHz, fRF2 = 451MHz, fLO = 440MHz, L6 = 15nH, C19 = 1.0pF, L5 = 12nH, C14 = 4.0pFfRF(MATCH) RF Input Frequency Range Return Loss > 10dB 300 to 600 MHzfLO(MATCH) LO Input Frequency Range Return Loss > 10dB 310 to 590 MHzGV Voltage Conversion Gain Loaded with 100Ω Pull-Up (Note 8) 5.4 dBNF Noise Figure Double-Side Band (Note 4) 9.9 dBNFBLOCKING Noise Figure Under Blocking Conditions Double-Side Band, PRF = 0dBm (Note 7) 13.6 dBIIP3 Input 3rd Order Intercept 31 dBmIIP2 Input 2nd Order Intercept Unadjusted, EIP2 = 0V 70 dBmIIP2OPT Optimized Input 2nd Order Intercept EIP2 = 5V, IP2I, IP2Q Adjusted for Minimum IM2 80 dBmP1dB Input 1dB Compression 12.6 dBmDCOFFSET DC Offset at I/Q Outputs Unadjusted, EDC = 0V (Note 13) 2 mV∆G I/Q Gain Mismatch 0.02 dB
∆φ I/Q Phase Mismatch 0.25 DegIRR Image Rejection Ratio (Note 10) 52 dBLO-RF LO to RF Leakage –80 dBmRF-LO RF to LO Isolation 70 dBfRF1 = 900MHz, fRF2 = 901MHz, fLO = 940MHz, C17 = 1.5pF, L6 = 5.6nH, C13 = 2.2pF, L5 = 3.9nHfRF(MATCH) RF Input Frequency Range Return Loss > 10dB 630 to 1200 MHzfLO(MATCH) LO Input Frequency Range Return Loss > 10dB 470 to 1100 MHzGV Voltage Conversion Gain Loaded with 100Ω Pull-Up (Note 8) 5.7 dBNF Noise Figure Double-Side Band (Note 4) 10 dBNFBLOCKING Noise Figure Under Blocking Conditions Double-Side Band, PRF = 0dBm (Note 7) 14.7 dBIIP3 Input 3rd Order Intercept 28 dBmIIP2 Input 2nd Order Intercept Unadjusted, EIP2 = 0V 65 dBmIIP2OPT Optimized Input 2nd Order Intercept EIP2 = 5V, IP2I, IP2Q Adjusted for Minimum IM2 80 dBmP1dB Input 1dB Compression 13.1 dBmDCOFFSET DC Offset at I/Q Outputs Unadjusted, EDC = 0V (Note 13) 2.5 mV∆G I/Q Gain Mismatch 0.01 dB
∆φ I/Q Phase Mismatch 0.7 DegIRR Image Rejection Ratio (Note 10) 45 dBLO-RF LO to RF Leakage –75 dBmRF-LO RF to LO Isolation 65 dBPower Supply and Other ParametersVCC Supply Voltage 4.75 5.0 5.25 VICC Supply Current EDC = EIP2 = VCC 180 200 220 mAICC(LOW) Supply Current EDC = EIP2 = 0V 174 194 214 mAICC(OFF) Shutdown Current EN < 0.3V 11 900 μAtON Turn-On Time EN Transition from Logic Low to High (Note 14) 0.2 µstOFF Turn-Off Time EN Transition from Logic High to Low (Note 15) 0.8 µsVEH EN, EDC, EIP2 Input High Voltage (On) 2.0 VVEL EN, EDC, EIP2 Input Low Voltage (Off) 0.3 V
LTC5584
45584f
elecTrical characTerisTics TC = 25°C, VCC = 5V, EN = 5V, EDC = EIP2 = 0V, REF = IP2I = IP2Q = DCOI = DCOQ = 0.5V, PRF = –5dBm (–5dBm/tone for 2-tone IIP2 and IIP3 tests), PLO = 6dBm, unless otherwise noted. (Notes 2, 3, 5, 6, 9)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSIENH EN Pin Input Current EN = 5.0V 52 μAIEDCH EDC Pin Input Current EDC = 5.0V 33 μAIEIP2H EIP2 Pin Input Current EIP2 = 5.0V 50 μAVREF REF Pin Voltage With REF Pin Unloaded 0.5 VVREF(RANGE) REF Pin Voltage Range When Driven with External Source 0.4 to 0.7 VZREF REF Input Impedance (Note 11) 2||1 kΩ||pF
DCOI, DCOQ, IP2I, IP2Q Pin Voltage Unloaded 0.5 VDCOI, DCOQ, IP2I, IP2Q Voltage Range When Driven with External Source 0 to 2VREF VDCOI, DCOQ, IP2I, IP2Q Impedance (Note 11) 8||1 kΩ||pFDCOI, DCOQ, IP2I, IP2Q Settling Time For Step Input, Output with 90% of Final Value 20 nsDC Offset Adjustment Range DCOI, DCOQ Swept from 0V to 1V, EDC = 5V ±20 mV
DC Offset Drift Over Temperature Unadjusted, EDC = 0V 20 μV/°CVCM I+, I–, Q+, Q– Common Mode Voltage VCC – 1.5 VZOUT I+, I–, Q+, Q– Output Impedance Single Ended 100||6 Ω||pFBWBB I+, I–, Q+, Q– Output Bandwidth 100Ω External Pull-Up, –3dB Corner Frequency 530 MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: Tests are performed with the test circuit of Figure 1.Note 3: The LTC5584 is guaranteed to be functional over the –40°C to 105°C case temperature operating range.Note 4: DSB noise figure is measured at the baseband frequency of 15MHz with a small-signal noise source without any filtering on the RF input and no other RF signal applied.Note 5: Performance at the RF frequencies listed is measured with external RF and LO impedance matching, as shown in the table of Figure 1.Note 6: The complementary outputs (I+, I– and Q+, Q–) are combined using a 180° phase-shift combiner.Note 7: Noise figure under blocking conditions (NFBLOCKING) is measured at an output noise frequency of 60MHz with an RF input blocking signal at fLO + 1MHz. Both RF and LO input signals are appropriately filtered, as well as the baseband output. NFBLOCKING measured at fLO of 160MHz, 460MHz and 885MHz.
Note 8: Voltage conversion gain is calculated from the average measured power conversion gain of the I and Q outputs using the test circuit shown in Figure 1. Power conversion gain is measured with a 100Ω differential load impedance on the I and Q outputs.Note 9: Baseband outputs have a 100Ω external pull-up resistor to VCC as shown in the test circuit shown in Figure 1.Note 10: Image rejection is calculated from the measured gain error and phase error using the method listed in the appendix.Note 11: The DCOI, DCOQ, IP2I, IP2Q pins have an 8k internal resistor to ground. The REF pin has a 2k internal resistor to ground. If unconnected, these pins will float up to 500mV through internal current sources. A low output resistance voltage source is recommended for driving these pins.Note 12: This is the recommended operating range, operation outside the listed range is possible with degraded performance to some parameters.Note 13: DC offset measured differentially between I+ and I– and between Q+ and Q–. The reported value is the mean of the absolute values of the characterization data distribution. Note 14: Baseband amplitude is within 10% of final value.Note 15: Baseband amplitude is at least 30dB down from its on state.
LTC5584
55584f
Dc perForMance characTerisTics
Typical perForMance characTerisTics
IIP3 and P1dB vs Temperature (TC)IIP3 and P1dB vs Supply Voltage (VCC) IIP3 vs LO Power
Supply Current vs Supply Voltage REF Voltage vs Temperature
EN = 5V, EDC = 0V and EIP2 = 0V. Test circuit shown in Figure 1
140MHz application. VCC = 5V, EN = 5V, EDC = 0V, EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 130MHz, fRF1 = 140MHz, fRF2 = 141MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm, DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1.
LO FREQUENCY (MHz)80
IIP3,
P1d
B (d
Bm)
30
5584 G03
20
10120 160100 140 180
40
50
IIP3
P1dB
25
15
35
45
200
I, –40°CI, 25°CI, 85°CI, 105°C
Q, –40°CQ, 25°CQ, 85°CQ, 105°C
LO FREQUENCY (MHz)80
IIP3,
P1d
B (d
Bm)
30
5584 G04
20
10120 160100 140 180
40
50
25
15
35
45
200
I, 4.75VI, 5.0VI, 5.25V
Q, 4.75VQ, 5.0VQ, 5.25V
TC = 25°C
IIP3
P1dB
LO FREQUENCY (MHz)80
IIP3
(dBm
)
30
5584 G05
20
10120 160100 140 180
40
50
25
15
35
45
200
TC = 25°CI, 0dBmI, 6dBmI, 10dBm
Q, 0dBmQ, 6dBmQ, 10dBm
SUPPLY VOLTAGE (V)4.75
160
SUPP
LY C
URRE
NT (m
A)
170
190
200
210
260
230
5
5585 G01
180
240
250
220
5.25
TC = –40°CTC = 25°CTC = 85°CTC = 105°C
TEMPERATURE (°C)–40
500
REF
VOLT
AGE
(mV)
505
515
520
525
550
535
0 40 60 80
5584 G02
510
540
545
530
–20 20 100
VCC = 4.75VVCC = 5VVCC = 5.25V
LTC5584
65584f
Typical perForMance characTerisTics
IIP2 vs IP2I, IP2Q Trim Voltage IIP2 vs RF Tone Spacing2x2 Half-IF IIP2 vs RF to LO Tone Spacing
Noise Figure and Conversion Gain vs LO Power
Noise Figure and Conversion Gain vs Temperature (TC)
2-Tone IIP3 vs RF PowerUncalibrated IIP2 vs Temperature (TC)
Noise Figure vs RF Power and IP2I, IP2Q Trim Voltage
Uncalibrated IIP2 vs LO Power
140MHz application. VCC = 5V, EN = 5V, EDC = 0V, EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 130MHz, fRF1 = 140MHz, fRF2 = 141MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm, DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1.
RF POWER (dBm)–10
IIP3
(dBm
)
35
40
45
50
–4 0 2 4
5584 G06
30
25
20–8 –6 –2
TC = 25°CfRF1 = 140MHzfRF2 = 141MHzfLO = 130MHz
QI
LO FREQUENCY (MHz)80
130
120
110
100
90
80
70
60140 180
5584 G07
100 120 160 200
IIP2
(dBm
)
I, –40°CI, 25°CI, 85°CI, 105°C
Q, –40°CQ, 25°CQ, 85°CQ, 105°C
LO FREQUENCY (MHz)80
130
120
110
100
90
80
70
60140 180
5584 G08
100 120 160 200
IIP2
(dBm
)
TC = 25°CI, 0dBmI, 6dBmI, 10dBm
Q, 0dBmQ, 6dBmQ, 10dBm
IP2I, IP2Q (V)0
IIP2
(dBm
)
90
100
110
0.8 0.9
5585 G09
80
70
500.2 0.4 0.60.1 1.00.3 0.5 0.7
60
130fRF = 140MHzEIP2 = 5V120
I, –40°CI, 25°CI, 85°CI, 105°C
Q, –40°CQ, 25°CQ, 85°CQ, 105°C
RF TONE SPACING (MHz)1
50
IIP2
(dBm
)
60
70
80
90
100
110
10 100 1000
5584 G10
I (UNCALIBRATED)I (NULLED AT 1MHz)Q (UNCALIBRATED)Q (NULLED AT 1MHz)
TC = 25°CfRF1 = 140MHzfLO = 130MHz
ZFSCJ-2-1BB COMBINER
RF TO LO SPACING (MHz)1
50
IIP2
(dBm
)
60
70
80
90
100
110
10 100 1000
5584 G11
QI
ZFSCJ-2-1BB COMBINER
TC = 25°CfLO = 140MHz
LO FREQUENCY (MHz)80
0
NF, G
AIN
(dB)
4
8
12
100 120 140 160
5584 G12
180
16
20
2
6
10
14
18
200
NF
GAIN
I, –40°CI, 25°CI, 85°CI, 105°C
Q, –40°CQ, 25°CQ, 85°CQ, 105°C
LO FREQUENCY (MHz)80
0
NF, G
AIN
(dB)
4
8
12
100 120 140 160
5584 G13
180
16
20
2
6
10
14
18
200
NF
GAIN
TC = 25°CI, 0dBmI, 6dBmI, 10dBm
Q, 0dBmQ, 6dBmQ, 10dBm
IP2I, IP2Q TRIM VOLTAGE (V)0
DSB
NOIS
E FI
GURE
(dB)
16
18
20
0.8
5584 G14
14
12
15
17
19
13
11
100.20.1 0.40.3 0.6 0.7 0.90.5 1.0
I, –20dBmI, 0dBm
Q, –20dBmQ, 0dBm
TC = 25°CfRF = 160MHzfLO = 159MHzfNOISE = 60MHzEIP2 = 5V
LTC5584
75584f
Typical perForMance characTerisTics
DC Offset vs LO PowerNoise Figure vs RF Input Power DC Offset vs Temperature (TC)
DC Offset vs DCOI, DCOQ Control Voltage
LO to RF Leakage and RF to LO Isolation Image Rejection vs Temperature
DC Offset Distribution, I-Side DC Offset Distribution, Q-Side
140MHz application. VCC = 5V, EN = 5V, EDC = 0V, EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 130MHz, fRF1 = 140MHz, fRF2 = 141MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm, DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1.
RF INPUT POWER (dBm)–20
DSB
NOIS
E FI
GURE
(dB)
19
22
2423
2021
1718
1415
1112
–5 5 10
5584 G15
16
13
109
–15 –10 0
PLO = 0dBmPLO = 6dBmPLO = 10dBm
TC = 25°CfLO = 159MHzfRF = 160MHzfNOISE = 60MHz
LO FREQUENCY (MHz)80
DC O
FFSE
T (m
V) 5
8
109
67
34
01
–3–2
140 180 200
5584 G16
2
–1
–4–5
100 120 160
I, –40°CI, 25°CI, 85°CI, 105°C
Q, –40°CQ, 25°CQ, 85°CQ, 105°C
LO FREQUENCY (MHz)80
DC O
FFSE
T (m
V) 5
8
109
67
34
01
–3–2
140 180 200
5584 G17
2
–1
–4–5
100 120 160
TC = 25°CI, 0dBmI, 6dBmI, 10dBm
Q, 0dBmQ, 6dBmQ, 10dBm
DCOI, DCOQ (V)0
–25
DC O
FFSE
T (m
V)
–20
–10–5
0
25303540
10
0.2 0.4
5584 G18
–15
1520
5
0.6 1.00.80.1 0.3 0.5 0.7 0.9
I, –40°CI, 25°CI, 85°CI, 105°C
Q, –40°CQ, 25°CQ, 85°CQ, 105°C
fLO = 140MHzEDC = 5V
DC OFFSET (mV)–2.5
PERC
ENTA
GE D
ISTR
IBUT
ION
(%)
20
30
5584 G19
10
0–1.5 0.5–0.5 1.5 2.5
90
40
TC = –40°CTC = 25°CTC = 85°CTC = 105°C
fLO = 100MHz
DC OFFSET (mV)–2.5
PERC
ENTA
GE D
ISTR
IBUT
ION
(%)
20
30
5584 G20
10
0–1.5 0.5–0.5 1.5 2.5
90
40
TC = –40°CTC = 25°CTC = 85°CTC = 105°C
fLO = 100MHz
LO FREQUENCY (MHz)80
–30
–40
–50
–60
–70
–80
–90
–100140 180
5584 G21
100 120 160 200
LEAK
AGE
(dBm
), –I
SOLA
TION
(dB)
L-R, –40°CL-R, 25°CL-R, 85°CL-R, 105°C
R-L, –40°CR-L, 25°CR-L, 85°CR-L, 105°C
LO FREQUENCY (MHz)80
IMAG
E RE
JECT
ION
(dB)
60
5584 G22
40
20120 160100 140 180
80
100
50
30
70
90
200
TC = –40°CTC = 25°CTC = 85°CTC = 105°C
LTC5584
85584f
Typical perForMance characTerisTics 450MHz application. VCC = 5V, EN = 5V, EDC = 0V, REF = 0.5V, EIP2 = 0V, TC = 25°C, PLO = 6dBm, fLO = 440MHz, fRF1 = 450MHz, fRF2 = 451MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm, DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1.
2-Tone IIP3 vs RF Power
2x2 Half-IF IIP2 vs RF to LO Tone Spacing
Uncalibrated IIP2 vs Temperature (TC) Uncalibrated IIP2 vs LO Power
IIP2 vs IP2I, IP2Q Trim Voltage IIP2 vs RF Tone Spacing
IIP3 and P1dB vs Temperature (TC)IIP3 and P1dB vs Supply Voltage (VCC) IIP3 vs LO Power
LO FREQUENCY (MHz)200
IIP3,
P1d
B (d
Bm)
25
30
35
500 700
IIP3
5584 G23
20
15
10300 400 600
40
45
50I, –40°CI, 25°CI, 85°CI, 105°C
Q, –40°CQ, 25°CQ, 85°CQ, 105°C
P1dB
LO FREQUENCY (MHz)200
IIP3,
P1d
B (d
Bm)
25
30
35
500 700
5584 G24
20
15
10300 400 600
40
45
50I, 4.75VI, 5.0VI, 5.25V
Q, 4.75VQ, 5.0VQ, 5.25V
TC = 25°C
IIP3
P1dB
LO FREQUENCY (MHz)200
IIP3
(dBm
)
25
30
35
500 700
5584 G25
20
15
10300 400 600
40
45
50TC = 25°CI, 0dBm
I, 6dBmI, 10dBm
Q, 0dBmQ, 6dBmQ, 10dBm
RF POWER (dBm)–10
IIP3
(dBm
)
35
40
45
50
–4 0 2 4
5584 G26
30
25
20–8 –6 –2
TC = 25°CfRF1 = 450MHzfRF2 = 451MHzfLO = 440MHz
QI
LO FREQUENCY (MHz)200
130
120
110
100
90
80
70
60500
5584 G27
300 400 600 700
IIP2
(dBm
)
I, –40°CI, 25°CI, 85°CI, 105°C
Q, –40°CQ, 25°CQ, 85°CQ, 105°C
LO FREQUENCY (MHz)200
130
120
110
100
90
80
70
60500
5584 G28
300 400 600 700
IIP2
(dBm
)
TC = 25°CI, 0dBmI, 6dBmI, 10dBm
Q, 0dBmQ, 6dBmQ, 10dBm
IP2I, IP2Q (V)0
IIP2
(dBm
)
90
100
110
0.8 0.9
5584 G29
80
70
500.2 0.4 0.60.1 1.00.3 0.5 0.7
60
130
120
I, –40°CI, 25°CI, 85°CI, 105°C
Q, –40°CQ, 25°CQ, 85°CQ, 105°C
fRF = 450MHzEIP2 = 5V
RF TONE SPACING (MHz)1
50
IIP2
(dBm
)
60
70
80
90
100
110
10 100 1000
5584 G30
I (UNCALIBRATED)I (NULLED AT 1MHz)Q (UNCALIBRATED)Q (NULLED AT 1MHz)
TC = 25°CfRF1 = 450MHzfLO = 440MHz
ZFSCJ-2-1BB COMBINER
QI
RF TO LO SPACING (MHz)1
50
IIP2
(dBm
)
60
70
80
90
100
110
10 100 1000
5584 G31
TC = 25°CfLO = 450MHz
ZFSCJ-2-1BB COMBINER
LTC5584
95584f
Typical perForMance characTerisTics 450MHz application. VCC = 5V, EN = 5V, EDC = 0V, REF = 0.5V, EIP2 = 0V, TC = 25°C, PLO = 6dBm, fLO = 440MHz, fRF1 = 450MHz, fRF2 = 451MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm, DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1.
Noise Figure vs RF Input PowerNoise Figure and Conversion Gain vs Temperature (TC)
Noise Figure and Conversion Gain vs LO Power
DC Offset vs DCOI, DCOQ Control VoltageDC Offset vs Temperature (TC) DC Offset vs LO Power
LO to RF Leakage and RF to LO Isolation Image Rejection vs Temperature
RF INPUT POWER (dBm)–20
9
DSB
NOIS
E FI
GURE
(dB)
11
13
17
15
19
23
21
–15 –10 –5 0
5584 G32
5 10
PLO = 0dBmPLO = 6dBmPLO = 10dBm
TC = 25°CfLO = 460MHzfRF = 461MHzfNOISE = 60MHz
LO FREQUENCY (MHz)200
NF, G
AIN
(dB) 12
16
20
600
5584 G33
8
4
10
14
18
6
2
0300 400 500 700
I, –40°CI, 25°CI, 85°CI, 105°C
Q, –40°CQ, 25°CQ, 85°CQ, 105°C
NF
GAIN
LO FREQUENCY (MHz)200
NF, G
AIN
(dB) 12
16
20
600
5584 G34
8
4
10
14
18
6
2
0300 400 500 700
NF
GAIN
TC = 25°CI, 0dBmI, 6dBmI, 10dBm
Q, 0dBmQ, 6dBmQ, 10dBm
LO FREQUENCY (MHz)200
10.0
7.5
5.0
2.5
0
–2.5
–5.0500
5584 G35
300 400 600 700
DC O
FFSE
T (m
V)
I, –40°CI, 25°CI, 85°CI, 105°C
Q, –40°CQ, 25°CQ, 85°CQ, 105°C
DCOI, DCOQ (V)0
–25
DC O
FFSE
T (m
V)
–20
–10–50
25303540
10
0.2 0.4
5584 G36
–15
1520
5
0.6 1.00.80.1 0.3 0.5 0.7 0.9
I, –40°CI, 25°CI, 85°CI, 105°C
Q, –40°CQ, 25°CQ, 85°CQ, 105°C
fLO = 450MHzEDC = 5V
LO FREQUENCY (MHz)200
10.0
7.5
5.0
2.5
0
–2.5
–5.0500
5584 G37
300 400 600 700
DC O
FFSE
T (m
V)
TC = 25°CI, 0dBmI, 6dBmI, 10dBm
Q, 0dBmQ, 6dBmQ, 10dBm
LO FREQUENCY (MHz)200
–30
–40
–50
–60
–70
–80
–90
–100500
5584 G38
300 400 600 700
LEAK
AGE
(dBm
), –I
SOLA
TION
(dB)
L-R, –40°CL-R, 25°CL-R, 85°CL-R, 105°C
R-L, –40°CR-L, 25°CR-L, 85°CR-L, 105°C
LO FREQUENCY (MHz)200
IMAG
E RE
JECT
ION
(dB)
60
5584 G39
40
20400 600300 500
80
100
50
30
70
90
700
TC = –40°CTC = 25°CTC = 85°CTC = 105°C
LTC5584
105584f
Typical perForMance characTerisTics 900MHz application. VCC = 5V, EN = 5V, EDC = 0V, EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 890MHz, fRF1 = 900MHz, fRF2 = 901MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm, DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1.
IIP3 and P1dB vs Temperature (TC)IIP3 and P1dB vs Supply Voltage (VCC) IIP3 vs LO Power
2-Tone IIP3 vs RF PowerUncalibrated IIP2 vs Temperature (TC) Uncalibrated IIP2 vs LO Power
IIP2 vs IP2I, IP2Q Trim Voltage IIP2 vs RF Tone Spacing2x2 Half-IF IIP2 vs RF to LO Tone Spacing
LO FREQUENCY (MHz)400
IIP3,
P1d
B (d
Bm)
25
30
35
1000 1400
IIP3
5584 G40
20
15
10600 800 1200
40
45
50I, –40°CI, 25°CI, 85°CI, 105°C
Q, –40°CQ, 25°CQ, 85°CQ, 105°C
P1dB
LO FREQUENCY (MHz)400
IIP3,
P1d
B (d
Bm)
25
30
35
1000 1400
5584 G41
20
15
10600 800 1200
40
45
50I, 4.75VI, 5.0VI, 5.25V
Q, 4.75VQ, 5.0VQ, 5.25V
TC = 25°C
IIP3
P1dB
LO FREQUENCY (MHz)400
IIP3
(dBm
)
25
30
35
1000 1400
5584 G42
20
15
10600 800 1200
40
45
50TC = 25°CI, 0dBm
I, 6dBmI, 10dBm
Q, 0dBmQ, 6dBmQ, 10dBm
RF POWER (dBm)–10
IIP3
(dBm
)
35
40
45
50
–4 0 2 4
5584 G43
30
25
20–8 –6 –2
TC = 25°CfRF1 = 900MHzfRF2 = 901MHzfLO = 890MHz
QI
LO FREQUENCY (MHz)400
120
110
100
90
80
70
60
501000
5584 G44
600 800 1200 1400
IIP2
(dBm
)
I, –40°CI, 25°CI, 85°CI, 105°C
Q, –40°CQ, 25°CQ, 85°CQ, 105°C
LO FREQUENCY (MHz)400
120
110
100
90
80
70
60
501000
5584 G45
600 800 1200 1400
IIP2
(dBm
)
TC = 25°CI, 0dBmI, 6dBmI, 10dBm
Q, 0dBmQ, 6dBmQ, 10dBm
IP2I, IP2Q (V)0
IIP2
(dBm
)
90
100
110
0.8 0.9
5585 G46
80
70
500.2 0.4 0.60.1 1.00.3 0.5 0.7
60
130fRF = 900MHzEIP2 = 5V120
I, –40°CI, 25°CI, 85°CI, 105°C
Q, –40°CQ, 25°CQ, 85°CQ, 105°C
ZFSCJ-2-1BB COMBINER
RF TONE SPACING (MHz)1
50
IIP2
(dBm
)
60
70
80
90
100
110
10 100 1000
5584 G47
I (UNCALIBRATED)I (NULLED AT 1MHz)Q (UNCALIBRATED)Q (NULLED AT 1MHz)
TC = 25°CfRF1 = 900MHzfLO = 890MHz
QI
RF TO LO SPACING (MHz)1
50
IIP2
(dBm
)
60
70
80
90
100
110
10 100 1000
5584 G48
TC = 25°CfLO = 900MHz
ZFSCJ-2-1BB COMBINER
LTC5584
115584f
Typical perForMance characTerisTics 900MHz application. VCC = 5V, EN = 5V, EDC = 0V, EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 890MHz, fRF1 = 900MHz, fRF2 = 901MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm, DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1.
DC Offset vs Temperature (TC) DC Offset vs LO PowerDC Offset vs DCOI, DCOQ Control Voltage
LO to RF Leakage and RF to LO Isolation Image Rejection vs Temperature Conversion Gain Distribution
Noise Figure vs RF Input PowerNoise Figure and Conversion Gain vs Temperature (TC)
Noise Figure and Conversion Gain vs LO Power
RF INPUT POWER (dBm)–20
9
DSB
NOIS
E FI
GURE
(dB)
11
13
17
15
19
23
21
–15 –10 –5 0
5584 G49
5 10
PLO = 0dBmPLO = 6dBmPLO = 10dBm
TC = 25°CfLO = 884MHzfRF = 885MHzfNOISE = 60MHz
LO FREQUENCY (MHz)400
NF, G
AIN
(dB) 12
16
20
1200
5584 G50
8
4
10
14
18
6
2
0600 800 1000 1400
I, –40°CI, 25°CI, 85°CI, 105°C
Q, –40°CQ, 25°CQ, 85°CQ, 105°C
NF
GAIN
LO FREQUENCY (MHz)400
NF, G
AIN
(dB) 12
16
20
1200
5584 G51
8
4
10
14
18
6
2
0600 800 1000 1400
NF
GAIN
TC = 25°CI, 0dBmI, 6dBmI, 10dBm
Q, 0dBmQ, 6dBmQ, 10dBm
LO FREQUENCY (MHz)400
10.0
7.5
5.0
2.5
0
–2.5
–5.01000
5584 G52
600 800 1200 1400
DC O
FFSE
T (m
V)
I, –40°CI, 25°CI, 85°CI, 105°C
Q, –40°CQ, 25°CQ, 85°CQ, 105°C
LO FREQUENCY (MHz)400
10.0
7.5
5.0
2.5
0
–2.5
–5.01000
5584 G53
600 800 1200 1400
DC O
FFSE
T (m
V)
TC = 25°CI, 0dBmI, 6dBmI, 10dBm
Q, 0dBmQ, 6dBmQ, 10dBm
DCOI, DCOQ (V)0
–25
DC O
FFSE
T (m
V)
–20
–10–50
25303540
10
0.2 0.4
5584 G54
–15
1520
5
0.6 1.00.80.1 0.3 0.5 0.7 0.9
I, –40°CI, 25°CI, 85°CI, 105°C
Q, –40°CQ, 25°CQ, 85°CQ, 105°C
fLO = 900MHzEDC = 5V
LO FREQUENCY (MHz)400
–30
–40
–50
–60
–70
–80
–90
–1001000
5584 G55
600 800 1200 1400
LEAK
AGE
(dBm
), –I
SOLA
TION
(dB)
L-R, –40°CL-R, 25°CL-R, 85°CL-R, 105°C
R-L, –40°CR-L, 25°CR-L, 85°CR-L, 105°C
LO FREQUENCY (MHz)400
IMAG
E RE
JECT
ION
(dB)
60
5584 G56
40
20800 1200600 1000
80
100
50
30
70
90
1400
TC = –40°CTC = 25°CTC = 85°CTC = 105°C
CONVERSION GAIN (dB)4.7
40
50
70
5.3 5.7
5584 G57
30
20
4.9 5.1 5.5 5.9
10
0
60
PERC
ENTA
GE D
ISTR
IBUT
ION
(%)
TC = –40°CTC = 25°CTC = 85°CTC = 105°C
LTC5584
125584f
Typical perForMance characTerisTics 900MHz application. VCC = 5V, EN = 5V, EDC = 0V, EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 890MHz, fRF1 = 900MHz, fRF2 = 901MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm, DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1.
DSB Noise Figure Distribution, Q-Side IIP2 Distribution, I-Side IIP2 Distribution, Q-Side
Gain Error Distribution Phase Error DistributionImage Rejection Distribution (Note 10)
IIP3 Distribution, I-Side IIP3 Distribution, Q-SideDSB Noise Figure Distribution, I-Side
IIP3 (dBm)26.5
PERC
ENTA
GE D
ISTR
IBUT
ION
(%)
40
60
5584 G58
20
027.5 28.5 29.527 28 29 30
80
30
50
10
70
TC = –40°CTC = 25°CTC = 85°CTC = 105°C
IIP3 (dBm)27
PERC
ENTA
GE D
ISTR
IBUT
ION
(%)
40
60
5584 G59
20
027.5 28.5 29.528 29 30
80
30
50
10
70
TC = –40°CTC = 25°CTC = 85°CTC = 105°C
DSB NOISE FIGURE (dB)9
50
60
70
10.6
5584 G61
40
30
9.4 9.8 10.2
20
10
0
PERC
ENTA
GE D
ISTR
IBUT
ION
(%)
TC = –40°CTC = 25°C
TC = 85°CTC = 105°C
IIP2 (dBm)69
0
PERC
ENTA
GE D
ISTR
IBUT
ION
(%)
10
30
40
50
100
70
70 71 71.5 72
5584 G62
20
80
90
60
69.5 70.5
TC = –40°CTC = 25°CTC = 85°CTC = 105°C
IIP2 (dBm)64.5
0
PERC
ENTA
GE D
ISTR
IBUT
ION
(%)
10
30
40
50
100
70
66.5 68.5 69.5
5584 G63
20
80
90
60
65.5 67.5
TC = –40°CTC = 25°CTC = 85°CTC = 105°C
GAIN ERROR (dB)–0.04
40
50
70
0 0.04
5584 G64
30
20
–0.02 0.02 0.06
10
0
60
PERC
ENTA
GE D
ISTR
IBUT
ION
(%)
TC = –40°CTC = 25°CTC = 85°CTC = 105°C
PHASE ERROR (DEGREES)0.4
PERC
ENTA
GE D
ISTR
IBUT
ION
(%)
40
60
5584 G65
20
00.5 0.7 0.90.6 0.8 1.0
70
30
50
10
TC = –40°CTC = 25°CTC = 85°CTC = 105°C
IMAGE REJECTION (dB)41
PERC
ENTA
GE D
ISTR
IBUT
ION
(%)
30
40
50
44 46
5584 G66
20
10
042 43 45 47 48
TC = –40°CTC = 25°CTC = 85°CTC = 105°C
DSB NOISE FIGURE (dB)9
PERC
ENTA
GE D
ISTR
IBUT
ION
(%)
20
30
40
5584 G60
10
09.4 10.29.8 10.6 11
70
60
50
TC = –40°CTC = 25°CTC = 85°CTC = 105°C
LTC5584
135584f
pin FuncTionsIP2Q, IP2I (Pin 1, Pin 4): IIP2 Adjustment Analog Control Voltage Input for Q and I Channel. A decoupling capacitor is recommended on this pin. A low output resistance volt-age source is recommended for driving these pins. These pins should be left floating if unused.
DCOQ, DCOI (Pin 2, Pin 3): DC Offset Analog Control Voltage Input for Q and I Channel. A decoupling capaci-tor is recommended on this pin. A low output resistance voltage source is recommended for driving these pins. These pins should be left floating if unused.
RF+, RF– (Pin 5, Pin 6): RF Differential Inputs. An external balun transformer with matching is used to obtain good return loss across the RF input frequency range. The RF pin should be DC-blocked with a 0.01µF coupling capacitor.
GND (Pins 8, 13, 14, Exposed Pad Pin 25): Ground. These pins must be soldered to the RF ground plane on the circuit board. The backside exposed pad ground connection should have a low inductance connection and good thermal contact to the printed circuit board ground plane using many through-hole vias. See Figures 2 and 3.
EN (Pin 7): Enable Pin. When the voltage on the EN pin is a logic high, the chip is completely turned on; the chip is completely turned off for a logic low. An internal 200k pull-down resistor ensures the chip remains disabled if there is no connection to the pin (open-circuit condition).
VBIAS (Pin 9): This pin can be pulled to ground through a resistor to lower the current consumption of the chip. See Applications Information.
VCC (Pin 10): Positive Supply Pin. This pin should be bypassed with shunt 0.01µF and 1µF capacitors.
EDC (Pin 11): DC Offset Adjustment Mode Enable Pin. When the voltage on the EDC pin is a logic high, the DC offset control circuitry is enabled. The circuitry is disabled for a logic low. An internal 200k pull-down resistor ensures the circuitry remains disabled if there is no connection to the pin (open-circuit condition).
EIP2 (Pin 12): IP2 Offset Adjustment Mode Enable Pin. When the voltage on the EIP2 pin is a logic high, the IP2 adjustment circuitry is enabled. The circuitry is disabled for a logic low. An internal 200k pull-down resistor ensures the circuitry remains disabled if there is no connection to the pin (open-circuit condition).
LO+,LO– (Pin 15, Pin 16): LO Inputs. External matching is required to obtain good return loss across the LO input frequency range. Can be driven single ended or differen-tially with an external transformer. The LO pins should be DC-blocked with 0.01µF coupling capacitors.
VCAP, CMQ, CMI (Pin 17, Pin 18, Pin 19): Common Mode Bypass Capacitor Pins. It is recommended that CMI and CMQ be connected to VCAP through 0.1µF capacitors. Nothing else should be connected to VCAP since it is con-nected to VCC inside the chip.
I+, I–, Q+, Q– (Pin 23, Pin 22, Pin 21, Pin 20): Differential Baseband Output Pins for the I Channel and Q Channel. The DC bias point is VCC – 1.5V for each pin. These pins must have an external 100Ω or an inductor pull-up to VCC.
REF (Pin 24): Voltage Reference Input for Analog Control Voltage Pins. A decoupling capacitor is recommended on this pin. A low output resistance voltage source is recommended for driving this pin. This pin should be left floating if unused.
LTC5584
145584f
block DiagraM
RF+
RF–
0°
90°
BIAS
IP2 AND DCOFFSET CAL
VCC VCAPCMI
I+
I–
IP2 AND DCOFFSET CAL
23
19
22
5
Q+
Q–
CMQ20
21
18
EDC
EIP2
REF12
11
24
DCOI3
IP2I4
IP2Q1
DCOQ2
6
LO+15
LO–16
EN
GND
7
GND GND
5584 BD
EXPOSEDPAD
VBIAS9
258 13 14
10 17
LTC5584
155584f
TesT circuiT
FREQUENCY RANGE
RF MATCH LO MATCH
C17 L6 C19 C13 L5 C14
140MHz 68nH 8.0pF 82nH
450MHz 15nH 1.0pF 12nH 4.0pF
900MHz 1.5pF 5.6nH 2.2pF 3.9nH
REF DES VALUE SIZE VENDOR REF DES VALUE SIZE VENDOR
C10, C11, C31-C35 0.1μF 0402 Murata L5, L6 See Table 0402 Murata
C15, C38-C41 0.01µF 0402 Murata R9, R11, R13, R14 100Ω 0402 Vishay
C13, C14, C17, C19 See Table 0402 Murata T1, T2 1:1 AT224-1 Mini-Circuits TC1-1-13M+
C16, C21, C22, C29, C30 1μF 0402 Murata
Figure 1. Test Circuit Schematic
24 23 22 21 20 19
7
C35
C40
C38T1 L5
LOC39 C13 C14
C41
T216
42
3
3 4
62
1
8 9 10 11 12
6
5
4
3
2
1
1325
14
15
16
17
18C11
IP2Q
DCOQ
DCOI
IP2I
RF+
RF–
IP2Q
DCOQ
DCOI
IP2I
CMQ
VCAP
LO–
LO+
GNDGNDGND
REF I+ I– Q+ Q–
CMI
EN GND
V BIA
S
V CC
EDC
EIP2
LTC5584IUF
C10
C19C17
C31
C21R11
C22 C30
EIP2EDC
C16
5584 F01
VCC4.75V TO 5.25V
C15
C34C33
C29
C32
RF
I+ OUT
I– OUT
Q– OUT
Q+ OUT
EN
REF
RFGND0.015"
0.015"
0.062"
NELCO N4000-13
DCGND
R13R9 R14
L6••
••
LTC5584
165584f
TesT circuiT
Figure 2. Component Side of Evaluation Board Figure 3. Bottom Side of Evaluation Board
applicaTions inForMaTionThe LTC5584 is an IQ demodulator designed for high dynamic range receiver applications. It consists of RF transconductance amplifiers, I/Q mixers, quadrature LO amplifiers, IIP2 and DC offset correction circuitry, and bias circuitry.
Operation
As shown in the Block Diagram for the LTC5584, the RF signal is applied to the inputs of the RF transconductor V-to-I converters and is then demodulated into I/Q baseband signals using quadrature LO signals which are internally generated by a precision 90° phase shifter. The demodulated I/Q signals are lowpass filtered on-chip with a –3dB bandwidth of 530MHz. The differential outputs of the I-channel and Q-channel are well matched in amplitude and their phases are 90° apart.
RF Input Port
Figure 4 shows the demodulator’s differential RF input which consists of high linearity transconductance ampli-fiers (V-I converters). External DC voltage should not be applied to the RF input pins. DC current flowing into the pins may cause damage to the transconductance amplifiers. Series DC blocking capacitors should be used to couple the RF input pins to the RF signal source.
The RF input port can be externally matched over the operating frequency range with simple L-C matching. An input return loss greater than 10dB can be obtained over a fractional bandwidth of greater than 66% with this method. Figure 5 shows the RF input return loss for various matching component values. Table 1 shows the differential and single-ended S parameters for the RF input without using any external matching components. The input transmission line length and balun are de-embedded from the measurement.
LTC5584
175584f
RF+
RF–
BIASC40
0.01µF
C410.01µF
RFINPUT
(MATCHED)
GND
5584 F04
LTC5584
C19C17
L6 16
42
3
••
T2MINI-CIRCUITS
TC1-1-13M+
Figure 4: Simplified Schematic of the RF Interface
applicaTions inForMaTion
Figure 5. RF Input Return Loss
Larger bandwidths can be obtained by using more ele-ments. For example Figure 6 shows an L-C match having a bandwidth of about 98% where return loss is >10dB. Figure 7 shows the RF input return loss for the wide bandwidth match.
Table 1. RF Input S Parameters
FREQUENCY (MHz)
S11 (DIFFERENTIAL) S11 (SINGLE ENDED)
MAG ANGLE(°) MAG ANGLE(°)
10 0.5657 –2.416 0.3253 –5.287
20 0.55 –2.674 0.3055 –5.761
40 0.5391 –2.288 0.2938 –4.499
80 0.5349 –2.268 0.2984 –4.517
140 0.5336 –2.946 0.3097 –9.805
200 0.5329 –3.836 0.2989 –16.34
300 0.5317 –5.453 0.2732 –21.46
400 0.5301 –7.128 0.2614 –24.35
450 0.5292 –7.975 0.2583 –25.79
500 0.5282 –8.826 0.2562 –27.29
600 0.5258 –10.54 0.2536 –30.43
700 0.523 –12.25 0.2523 –33.66
800 0.5199 –13.97 0.2517 –36.88
900 0.5164 –15.7 0.2519 –39.97
1000 0.5124 –17.43 0.2529 –42.85
1100 0.5082 –19.17 0.2556 –45.49
1200 0.5035 –20.91 0.2609 –48.02
1300 0.4985 –22.66 0.2693 –50.73
1400 0.4931 –24.42 0.2804 –53.98
1500 0.4873 –26.19 0.2925 –57.96
1600 0.4812 –27.97 0.3035 –62.52
1700 0.4747 –29.77 0.3122 –67.36
1800 0.4678 –31.58 0.3187 –72.19
1900 0.4606 –33.41 0.3235 –76.87
2000 0.453 –35.26 0.3271 –81.36
Note: Differential S parameters measured with 1:1 balun and single-ended S parameters measured with 50Ω termination on unused port.
FREQUENCY (GHz)
–30
RETU
RN L
OSS
(dB)
–20
–10
0
–25
–15
–5
0.4 0.8 1.2 1.6
5584 F05
2.00.20 0.6 1.0 1.4 1.8
L6 = 68nH, C19 = 8.0pFL6 = 15nH, C19 = 1.0pFC17 = 1.5pF, L6 = 5.6nHNO MATCHING
TC = 25°C
RF+
RF–
BIASC40
0.01µF
T2MINI-CIRCUITS
TC1-1-13M+
C410.01µF
RF INPUT650MHz TO
950MHz
GND
5584 F06
LTC5584
C172.7pF
L67.5nH
L75.6nH 1••6
42
3
Figure 7. RF Input Return Loss for Wideband Match
Figure 6. Wide Bandwidth RF Input Match
FREQUENCY (GHz)0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
RETU
RN L
OSS
(dB)
–10
–5
5584 F07
–15
–202.0
TC = 25°CC17 = 2.7pFL6 = 7.5nHL7 = 5.6nH
0
LTC5584
185584f
applicaTions inForMaTionBroadband Performance
To get an idea of the broadband performance of the LTC5584, a 6dB pad can be put on the RF and LO ports, and the ports can be left unmatched. The measured RF performance for this configuration is shown in Figures 8, 9, 10 and 11 with the 6dB pad de-embedded. The RF tone spacing is 1MHz, and fLO is 10MHz lower than fRF. The conversion gain is lower than under the impedance matched condition, and correspondingly the P1dB, IIP3, and NF are higher. As shown, the part can be used at frequencies outside its specified operating range with reduced conversion gain and higher NF.
Figure 8. Broadband IIP3 and IP1dB
Figure 9. Broadband IIP2
Figure 10. Broadband NF and Gain
Figure 11. Broadband Image Rejection
LO FREQUENCY (GHz)0
IIP3,
P1d
B (d
Bm)
30
35
40
1.6 1.8
5584 F08
25
20
100.4 0.8 1.20.2 2.00.6 1.0 1.4
15
50
45
IIP3
P1dB
I, –40°CI, 25°CI, 85°CI, 105°C
Q, –40°CQ, 25°CQ, 85°CQ, 105°C
LO FREQUENCY (GHz)0
IIP2
(dBm
) 100
120
140
1.6
5584 F09
80
60
90
110
130
70
50
400.40.2 0.80.6 1.2 1.4 1.81.0 2.0
I, –40°CI, 25°CI, 85°CI, 105°C
Q, –40°CQ, 25°CQ, 85°CQ, 105°C
LO FREQUENCY (GHz)0
NF, G
AIN
(dB) 12
16
20
1.6
5584 F10
8
4
10
14
18
6
2
00.40.2 0.80.6 1.2 1.4 1.81.0 2.0
I, –40°CI, 25°CI, 85°CI, 105°C
Q, –40°CQ, 25°CQ, 85°CQ, 105°C
GAIN
NF
LO FREQUENCY (GHz)0
IMAG
E RE
JECT
ION
(dB)
60
70
80
1.6 1.8
5584 F11
50
40
200.4 0.8 1.20.2 2.00.6 1.0 1.4
30
100
90TC = –40°CTC = 25°CTC = 85°CTC = 105°C
LO Input Port
The demodulator’s LO input interface is shown in Fig-ure 12. The input consists of a high precision quadrature phase shifter which generates 0° and 90° phase shifted LO signals for the LO buffer amplifiers to drive the I/Q mixers. DC blocking capacitors are required on the LO+
and LO– inputs.
The differential and single-ended LO input S parameters with the input transmission lines and balun de-embedded are listed in Table 2.
LTC5584
195584f
applicaTions inForMaTion
Figure 12. Simplified Schematic of LO Input Interface with External Matching Components
TO IDENTICALQ-CHANNEL
PHASE SHIFTER
LTC5584
VCC
LO+
C390.01µF
LOINPUT
(MATCHED) C13
C380.01µF
LO–
GND5584 F12
C14
L5
MINI-CIRCUITSTC1-1-13M+
1••6
42
3
Table 2. LO Input S-Parameters
FREQUENCY (MHz)
S11 (DIFFERENTIAL) S11 (SINGLE ENDED)
MAG ANGLE(°) MAG ANGLE(°)
10 0.8138 –1.736 0.7869 –1.896
20 0.8485 –6.615 0.8127 –6.425
40 0.7857 –18.67 0.7382 –16.33
80 0.6608 –25.61 0.6356 –20.1
140 0.5968 –33.93 0.5801 –25.43
200 0.5515 –42.29 0.5395 –30.5
300 0.4932 –54.56 0.4911 –37.49
400 0.4538 –65.21 0.4606 –43.5
450 0.4396 –70.18 0.4498 –46.36
500 0.4283 –75.01 0.441 –49.17
600 0.412 –84.37 0.4278 –54.67
700 0.4018 –93.45 0.4187 –60.04
800 0.3958 –102.3 0.4124 –65.26
900 0.3928 –110.9 0.4083 –70.32
1000 0.3921 –119.2 0.4059 –75.21
1100 0.3931 –127.2 0.405 –79.94
1200 0.3955 –135 0.4052 –84.52
1300 0.399 –142.4 0.4064 –88.94
1400 0.4035 –149.5 0.4084 –93.23
1500 0.4088 –156.3 0.411 –97.37
1600 0.4148 –162.9 0.4143 –101.4
1700 0.4213 –169.1 0.4181 –105.3
1800 0.4283 –175.1 0.4224 –109.1
1900 0.4357 –180.8 0.4271 –112.8
2000 0.4435 –186.2 0.4322 –116.4
Note: Differential S parameters measured with 1:1 balun and single-ended S parameters measured with 50Ω termination on unused port.
Figure 13 shows LO input return loss using the Mini-Circuits TC1-1-13M+ 1:1 balun with various matching component values.
For optimum IIP2 and large-signal NF performance the LO inputs should be driven differentially with a 1:1 balun such as the Mini-Circuits TC1-1-13M+ or M/A Com ETC1-1-13. As shown in Figure 14, the LO input can also be driven single-ended from either the LO+ or LO– input. The unused port should be DC-blocked and terminated with a 50Ω load. Figure 15 compares the uncalibrated IIP2 performance of single ended versus differential LO drive.
Figure 13. LO Input Return Loss
FREQUENCY (GHz)
–30
RETU
RN L
OSS
(dB)
–20
–10
0
–25
–15
–5
0.4 0.8 1.2 1.6
5584 F13
2.00.20 0.6 1.0 1.4 1.8
L5 = 82nHL5 = 12nH, C14 = 4.0pFC13 = 2.2pF, L5 = 3.9nH NO MATCHING
TC = 25°C
LTC5584
205584f
applicaTions inForMaTion
Figure 14. Recommended Single-Ended LO Input Configuration
Figure 15. Broadband IIP2 with Differential and Single-Ended LO Drive
Figure 16. Conversion Gain Baseband Output Response with RLOAD(DIFF) = 100Ω, 200Ω, 400Ω and 1k and RPULL-UP = 100Ω
I-Channel and Q-Channel Outputs
The phase relationship between the I-channel output signal and the Q-channel output signal is fixed. When the LO input frequency is higher (or lower) than the RF input frequency, the Q-channel outputs (Q+, Q–) lead (or lag) the I-channel outputs (I+, I–) by 90°.
Each of the I-channel and Q-channel outputs is internally connected to VCC through a 100Ω resistor. In order to maintain an output DC bias voltage of VCC – 1.5V, external 100Ω pull-up resistors or equivalent 15mA DC current sources are required. Each single-ended output has an impedance of 100Ω in parallel with a 6pF internal capaci-tor. With an external 100Ω pull-up resistor this forms a lowpass filter with a –3dB corner frequency at 530MHz.
LO FREQUENCY (GHz)
30
IIP2
(dBm
)
50
70
100
40
60
80
90
0.4 0.8 1.2 1.6
5584 F15
2.00.20 0.6 1.0 1.4 1.8
SINGLE-ENDED LO, I-SIDEDIFFERENTIAL LO, I-SIDESINGLE-ENDED LO, Q-SIDEDIFFERENTIAL LO, Q-SIDE
TC = 25°C
TO IDENTICALQ-CHANNEL
PHASE SHIFTER
LTC5584
VCC
LO+
C390.01µF
50Ω
L5
LOINPUT
(MATCHED)
C13
C380.01µF
LO–
GND5584 F14
C14
BASEBAND FREQUENCY (GHz)0
CONV
ERSI
ON G
AIN
(dB)
210
4
67
5
3
–1
0.4 0.5 0.7 1.0
–4
–2
–8
–6–5
–3
–7
0.1 0.2 0.3 0.6 0.8 0.9
RLOAD(DIFF) = 100Ω, BW = 850MHzRLOAD(DIFF) = 200Ω, BW = 630MHzRLOAD(DIFF) = 400Ω, BW = 530MHzRLOAD(DIFF) = 1kΩ, BW = 460MHz
TC = 25°C
The outputs can be DC coupled or AC coupled to exter-nal loads. The voltage conversion gain is reduced by the external load by:
20Log10
12
+ 50ΩRPULL-UP ||RLOAD(SE)
dB
when the output port is terminated by RLOAD(SE). For in-stance, the gain is reduced by 6dB when each output pin is connected to a 50Ω load (or 100Ω differentially). The output should be taken differentially (or by using differential-to-single-ended conversion) for best RF performance, includ-ing NF and IIP2. When no external filtering or matching components are used, the output response is determined by the loading capacitance and the total resistance loading the outputs. The –3dB corner frequency, fC, is given by the following equation:
fC = [2π(RLOAD(SE)||100Ω||RPULL-UP) (6pF)]–1
Figure 16 shows the actual measured output response with various load resistances.
Figure 17 shows a simplified model of the I, Q outputs with a 100Ω differential load and 100Ω pull-ups. The –1dB bandwidth in this configuration is about 520MHz, or about twice the –1dB bandwidth with no load.
Figure 18 shows a simplified model of the I, Q outputs with a L-C matching network for bandwidth extension. Capacitor CS serves to filter common mode LO switching noise immediately at the demodulator outputs. Capacitor CC in combination with inductor LS is used to peak the
LTC5584
215584f
applicaTions inForMaTion
Figure 17. Simplified Model of the Baseband Output
100Ω
LTC5584
100Ω6pF 6pF
0.2pF
I+
I–
0.2pF
5584 F17
RLOAD(DIFF)100Ω
–1dB BW = 520MHz
1.5nH
VCC
VCC
GND
1k
AC CURRENTSOURCE
1.5nH
30mA30mA
RPULL-UP100Ω
RPULL-UP100Ω
PACKAGEPARASITICS
Figure 19. Alternate Layout of PCB with Baseband Outputs on the Backside
Figure 18. Simplified Model of the Baseband Output Showing Bandwidth Extension with External L, C Matching
100Ω
LTC5584
100Ω6pF 6pF
0.2pF
I+
I–
0.2pFCS2pF
CS2pF CC
4pF
CC4pF
LS10nH
LS10nH
5584 F18
RLOAD(DIFF)100Ω
LOWPASS–1dB BW = 650MHz
6mA MAX DC
1.5nF
VCC
VCC
GND
1k
AC CURRENTSOURCE
1.5nF
30mA DC30mA DC
RPULL-UP100Ω
RPULL-UP100Ω
PACKAGEPARASITICS
output response to give greater bandwidth of 650MHz. In this case, capacitor CC was chosen as a common mode capacitor instead of a differential mode capacitor to increase rejection of common mode LO switching noise.
When AC output coupling is used, the resulting highpass filter’s –3dB roll-off frequency, fC, is defined by the R-C constant of the external AC coupling capacitance, CAC, and the differential load resistance, RLOAD(DIFF):
fC = [2π • RLOAD(DIFF) • CAC]–1
Care should be taken when the demodulator’s outputs are DC coupled to the external load to make sure that the I/Q mixers are biased properly. If the current drain from the outputs exceeds about 6mA, there can be significant degradation of the linearity performance. Keeping the com-mon mode output voltage of the demodulator above 3.15V,
with a 5V supply, will ensure optimum performance. Each output can sink no more than 30mA when the outputs are connected to an external load with a DC voltage higher than VCC – 1.5V.
In order to achieve the best IIP2 performance, it is im-portant to minimize high frequency coupling among the baseband outputs, RF port, and LO port. Although it may increase layout complexity, routing the baseband output traces on the backside of the PCB can improve uncalibrated IIP2 performance. Figure 19 shows the alternate layout having the baseband outputs on the backside of the PCB.
LTC5584
225584f
applicaTions inForMaTionAnalog Control Voltage Pins
Figure 20 shows the equivalent circuit for the DCOI, DCOQ, IP2I, and IP2Q pins. Internal temperature compensated 62.5μA current sources keep these pins biased at a nominal 500mV through 8k resistors. A low impedance voltage source with a source resistance of less than 200Ω is recommended to drive these pins.
As shown in Figure 21, the REF pin is similar to the DCOI pin, but the bias current source is 250µA, and the inter-nal resistance is 2k. If this pin is left disconnected, it will self-bias to 500mV. A low impedance voltage source with a source resistance of less than 200Ω is recommended to drive this pin. The control voltage range of the DCOI, DCOQ, IP2I and IP2Q pins is set by the REF pin. This range is equal to 0V to twice the voltage on the REF pin, whether internally or externally applied.
It is recommended to decouple any AC noise present on the signal lines that connect to the analog control-voltage inputs. A shunt capacitor to ground placed close to these pins can provide adequate filtering. For instance, a value of 1000pF on the DCOI, DCOQ, IP2I and IP2Q pins will provide a corner frequency of around 6 to 7MHz. A similar corner frequency can be obtained on the REF pin with a value of 3900pF. Using larger capacitance values such as 0.1µF is recommended on these pins unless a faster control response is needed. Figure 22 shows the input response –3dB bandwidth for the pins versus shunt capacitance when driven from a 50Ω source.
DC Offset Adjustment Circuitry
Any sources of LO leakage to the RF input of a direct conversion receiver will contribute to the DC offsets of its baseband outputs. The LTC5584 features DC offset adjustment circuitry to reduce such effects. When the EDC pin is a logic high the circuitry is enabled and the resulting DC offset adjustment range is typically ±20mV. In a typical direct conversion receiver application, DC offset calibration will be done periodically at a time when no receive data is present and when the receiver DC levels have sufficiently settled.
Figure 20. Simplified Schematic of the Interface for the DCOI, DCOQ, IP2I and IP2Q Pins
Figure 21. Simplified Schematic of the REF Pin Interface
GND5584 F20
VCC
8k
DCOI, DCOQ,IP2I, IP2Q
62.5µA
LTC5584
GND5584 F21
VCC
2k
REF
250µA
LTC5584
Figure 22. Input Response Bandwidth for the DCOI, DCOQ, IP2I and IP2Q Pins
FREQUENCY (MHz)0
RESP
ONSE
(dB)
–4
–2
0
165584 F22
–6
–8
–5
–3
–1
–7
–9
–1042 86 12 14 1810 20
DCOI, DCOQ; C = 470pFDCOI, DCOQ; C = 1000pFIP2I, IP2Q; C = 100pF
TC = 25°C
LTC5584
235584f
applicaTions inForMaTionDC Offset Adjustment Example
Figure 23 shows a typical direct conversion receive path having a DSP feedback path for DC offset adjustment. Any sources of LO leakage to the RF input of the LTC5584 demodulator will contribute to the DC offset of the receiver. This includes both static and dynamic DC offsets. If the coupling is static in nature due to fixed board-level leakage paths, the resulting DC offset does not typically need to be adjusted at a high repetition rate. Dynamic DC offsets due to transmitter transient leakage or antenna reflection can be much harder to correct for and will require a faster update rate from the DSP.
LO leakage into the RF port of the demodulator causes a DC offset at the baseband outputs which is then multiplied by the gain in the baseband path. The usable ADC voltage window will be reduced by the amplified DC offset, resulting in lower dynamic range. Using DSP, this DC offset value can be averaged and sampled at a given update rate and then a 1D minimization algorithm can be applied before a new DCOI or DCOQ control signal is generated to mini-mize the offset. The 1-D minimization algorithm can be implemented in many ways such as golden-section search, backtracking, or Newton’s method.
IM2 Adjustment Circuitry
The LTC5584 also contains circuitry for the independent adjustment of IM2 levels on the I and Q channels. When the EIP2 pin is a logic high, this circuitry is enabled and the IP2I and IP2Q analog control voltage inputs are able to adjust the IM2 level. The IM2 level can be effectively minimized over a large range of the baseband bandwidth. The circuitry has an effective baseband frequency upper Figure 24. Equivalent Circuit of the CMI and CMQ Pin Interfaces
GND5584 F24
VCC
VCAP
CMI OR CMQ
40pF
LTC5584
SAMPLE ANDHOLD
DCAVERAGINGLOWPASS
FILTER
DSP
DAC
ADC
DCOI
fLO = 900MHz 5585 F23
LNA
BPF
LTC5584
1-DMINIMIZATIONALGORITHM
Figure 23. Block Diagram of a Receiver with a DSP Feedback Loop for DC Offset Adjustment
limit of about 200MHz. Any IM2 component that falls in this frequency range can be minimized. Beyond this frequency, the gain of the IM2 correction amplifier falls off appreciably and the circuit no longer improves IP2 performance. The lower baseband frequency limit of the IM2 adjustment circuitry is set by the common mode reference decoupling capacitor at the CMI and CMQ pins. Below this frequency the circuit can not minimize the IM2 component.
Figure 24 shows the CMI (and identical CMQ) pin interface. These pins have an internal 40pF decoupling capacitance to VCC, to provide a reference for the IP2 adjustment cir-cuitry. The lower 3dB frequency limit, fC, of the circuitry is set by the following equation:
fC = [2π • 500(40pF + CCM(EXT))]–1
Without any external capacitor on the CMI or CMQ pin the lower limit is 8MHz. By adding a 0.1μF capacitor, CCM(EXT), between the CMI and CMQ pins to VCAP, the lower –3dB frequency corner can be reduced to 3kHz. Figure 25 shows IIP2 as a function of RF frequency spacing versus common mode decoupling capacitance values of 0.1µF and 1500pF. There is effectively no limit on the size of this capacitor,
LTC5584
245584f
applicaTions inForMaTionother than the impact it has on enable time for the IM2 circuitry to be operational. When the chip is disabled, there is no current in the I or Q mixers, so the common mode output voltage will be equal to VCC (if no DC common mode current is being drawn by external baseband circuitry such as a baseband amplifier). When the chip is enabled, the off-chip common mode decouping capacitor must charge up through a 500Ω resistor. The time constant for this is essentially 500Ω times the common mode decoupling capacitance value. For example, with a 0.01µF capacitor this wait time is approximately 30μs. Figure 26 shows the pulsed enable response of the common-mode output voltage with 0.01µF on the CMI and CMQ pins.
IM2 Suppression Example
IM2 adjustment circuitry can be used in a typical transceiver loop-back application as shown in Figure 27. In this example a 2-tone SSB training source of f1 = 20MHz and f2 = 21MHz is generated in DSP and upconverted by the LTC5588-1 quadrature modulator to RF tones at 870MHz and 871MHz using an LO source at 850MHz. A narrowband RF filter is required to remove the IM2 component generated by the LTC5588-1. During the loopback test these RF tones are routed through high isolation switches and an attenuation pad to the LTC5584 demodulator input. The tones are then downconverted by the same LO source at 850MHz to produce two tones at the baseband outputs of 20MHz and 21MHz plus an IM2 impairment signal at 1MHz. After base-band channel filtering and amplification the output of the ADC is filtered by a 1MHz bandpass filter in DSP to isolate the IM2 tone. The power in this tone is calculated in DSP and then a 1-D minimization algorithm is applied to calculate the correction signal for the IP2I control voltage pin. The 1-D minimization algorithm can be implemented in many ways such as golden-section search, backtracking or Newton’s method.
Enable Interface
A simplified schematic of the EN pin is shown in Figure 28. The enable voltage necessary to turn on the LTC5584 is 2V. To disable or turn off the chip, this voltage should be below 0.3V. If the EN pin is not connected, the chip is disabled.
Figures 29 and 30 show the simplified schematics for the EDC and EIP2 pins.
It is important that the voltage applied to the EN, EDC and EIP2 pins should never exceed VCC by more than 0.3V. Otherwise, the supply current may be sourced through the upper ESD protection diode connected at the pin. Under no circumstances should voltage be applied directly to the enable pins before the supply voltage is applied to the VCC pin. If this occurs, damage to the IC may result. A 1k resistor in series with the enable pin can be used to limit current.
Reducing Power Consumption
Figure 31 shows the simplified schematic of the VBIAS interface. The VBIAS pin can be used to lower the mixer
Figure 26. Common Mode Output Voltage with a Pulsed Enable
Figure 25. IIP2 vs Common Mode Decoupling Capacitance
TIME (µs)0
V CM
(V)
ENABLE VOLTAGE (V)
6
7
8
80
5584 F26
5
4
3
0
5
10
–5
–10
–1510 20 30 40 50 60 70 90 100
TC = 25°CCCMI,Q = 0.01µF
ENPULSE
OFF
EN PULSE ON
CMI, CMQ
BASEBAND OUTPUTS
RF FREQUENCY SPACING (MHz)0.01
IIP2
(dBm
)
90
5584 F25
70
500.1 1
110
130
80
60
100
120
10
0.1µF (UNCALIBRATED)0.1µF (NULLED IP2I = 0.6V)1500pF (UNCALIBRATED)1500pF (NULLED IP2I = 0.6V)
TC = 25°CfRF1 = 1000MHzfLO = 960MHz
LTC5584
255584f
applicaTions inForMaTion
Figure 27. Block Diagram for a Direct Conversion Transceiver with IM2 Adjustment. Only the I-Channel Is Shown
RMSDETECTION
1MHz BPF
DSP
DAC
ADC
IP2I
fLO = 850MHz
f1 = 20MHz
f2 = 21MHz
5584 F27
LNA
LTC5584
LOOPBACK
LTC5588-1
1-DMINIMIZATIONALGORITHM
DACPA
+
Figure 28. Simplified Schematic of the EN Pin Interface
Figure 29. Simplified Schematic of the EDC Pin Interface
100k
EN
LTC5584
GND5584 F28
VCC
100k
EN100k
100k
EDC
LTC5584
5584 F29
VCC
GND
100k
EIP2
LTC5584
GND5584 F30
VCC
100k10k
Figure 30. Simplified Schematic of the EIP2 Pin Interface
core bias current and total power consumption for the chip. For example, adding 487Ω from the VBIAS pin to GND will lower the DC current to 169mA, at the expense of reduced IIP3 performance. Figure 32 shows IIP3 and
EN
VCC
GND5584 F31
100ΩVBIAS
COPT
OPTIONAL RTO REDUCE
CURRENT
LTC5584
Figure 31. Simplified Schematic of the VBIAS Pin Interface
P1dB performance versus DC current and resistor value. An optional capacitor, COPT in Figure 31, has minimal effect on improving PSRR and IIP2.
LTC5584
265584f
Figure 32. IIP3 and P1dB vs DC Current and VBIAS Resistor Value
applicaTions inForMaTion
900MHz Receiver Application
Figure 33 shows a typical receiver application consisting of the chain of LNA, demodulator, lowpass filter, ADC driver, and ADC. Total DC power consumption is about 2.1W. Full-scale power at the RF input is –8.4dBm. The Chebychev lowpass filter with unequal terminations is designed us-ing the method shown in the appendix. Filter component values are then adjusted for the best overall response and available component values. A positive voltage gain slope with frequency is necessary to compensate for the roll-off contributed by the ADC Driver and Anti-Alias Filter. From the chain analysis shown in Figure 34, the IIP3-NF dynamic range figure of merit (FOM) is 5.3dB at the LNA input, 11.3dB at the demodulator input, and 16.8dB at the ADC driver amp input.
The measured 6th order lowpass baseband response is shown in Figure 35.
The receiver spurious free dynamic range (SFDR) in terms of FOM can be calculated using the following equations:
FOM = IIP3 – NF
SFDR = 2/3(FOM – P0)
P0 = –174dBm + 10Log10(BW|Hz)
RF FREQUENCY (MHz)400
0
5
P1dB
, IIP
3 (d
Bm)
15
20
25
50
35
800 1200
5584 F32
10
40
45
30
600 1000 1400
I, 194mAI, 169mA, 487ΩI, 145mA, 294Ω
Q, 194mAQ, 169mA, 487ΩQ, 145mA, 294Ω
TC = 25°CfRF = 900MHz
P1dB
IIP3
where P0 is the input noise power and –174dBm is the input thermal noise power in a 1Hz bandwidth. A measured 2-tone output spectrum at 890MHz is shown in Figure 36. IIP3 is calculated from the 2-tone IM3 levels:
IIP3 = (–6.929 – (–88.33))/2 – 15.4
IIP3 = 25.3dBm
For this example, receiver noise floor is approximated by a measurement from 28MHz to 36MHz offset frequency, where adequate filtering for RF and LO signals was pos-sible. Using the test data from Figure 36, the receiver noise figure for the I-channel (Ch 1) is calculated using the –8.4dBm input power, 15kHz bin width, 40MHz bandwidth, and –108dBFS measured in-band noise floor:
SNRIN = PIN – P0
SNRIN = –8.4 – (–174 + 76) = 89.6dB
SNROUT = –10 Log10(BinW/BW) – Floor
SNROUT = –43.3 + 108 = 73.7dB
NF = SNRIN – SNROUT
NF = 89.6 – 73.7 = 15.9dB
Finally, the receiver spurious free dynamic range can be calculated using the measured data at 890MHz:
SFDR = 2(IIP3 – NF – P0)/3
SFDR = 2(25.3 – 15.9 – (–174 + 76))/3
SFDR = 73dB
LTC5584
275584f
applicaTions inForMaTion
D13
D0
CONT
ROL
V CM
V DD
LTC2
185
ADC
1.8V
206m
A
5V20
0mA
5V48
mA
A IN+
A IN–
R20
150Ω
C22
39pF
C21
39pF
R19
150Ω
R16
27.4
Ω
R15
27.4
Ω
R5 110Ω
R411
0Ω
C23
1µF
5585
F33
R18
86.6
Ω
R17
86.6
Ω
R10
100Ω
R12
36.5
Ω
R8 402Ω R9 402Ω
R7 20Ω
R2 5.6k
R6 20Ω
R11
36.5
Ω
R13
243Ω
R14
243Ω
5V52
mA
C19
0.5p
F
C20
0.5p
F
C18
0.1µ
F
L12
180n
H
L11
180n
H
L8 1
80nH
L7 1
80nH
40M
Hz L
OWPA
SS F
ILTE
R40
MHz
ANT
I-ALI
AS F
ILTE
R
L6 4
70nH
L3 5
.6nH
AVAG
OM
GA-6
33P8
L2 33nH
L4 3
.9nH
L5 4
70nH
L10
270n
H
L9 2
70nH
• • •
C15
150p
F
C16
150p
F
C17
1µF
R3 10Ω
R1 0Ω
–
–+
+V O
CNLT
C640
9
C13
150p
F
C14
150p
F
C12
47pF
C10
0.01
µFC1
10.
01µF
LO IN
PUT
881M
Hz6d
Bm
C9 47pF
L233
nH
C7 1.5p
FC2
0.01
µF
C24
0.01
µF
C25
0.01
µF
C10.
01µF
RF IN
PUT
800M
Hz TO
1000
MHz
C4 33pF
C5 100p
F
C3 4.7µ
FC6 4.
7µF
C8 2.2p
F
I+V C
C
I–
RF+
RF–
LO–
LO+LT
C558
4
LNA
BIAS
••
T2M
INI-C
IRCU
ITS
TC1-
1-13
M+
16 4
2 3
• •
T1 MIN
I-CIR
CUIT
STC
1-1-
13M
+
12
3 46
Figu
re 3
3. S
impl
ified
Sch
emat
ic o
f 900
MHz
Rec
eive
r, (O
nly
I-Cha
nnel
Is S
how
n)
LTC5584
285584f
applicaTions inForMaTion
Figure 34. 900MHz Receiver Chain Analysis
LTC2185
5584 F34
40MHz AAFLTC6409
G = 0dBNF = 23.1dBIP3 = 47.5dBm
G = –1.2dBNF = 1.2dB
G = 0dBNF = 23.1dBIIP3 = 47.5dBmFOM = 24.4dB
G = –1.2dBNF = 24.3dBIIP3 = 48.7dBmFOM = 24.4dB
40MHz LPF
900MHz Receiver Chain Analysis
LTC5584
G = –0.3dBNF = 0.3dB
G = –0.3dBNF = 10.4dBIIP3 = 27.9dBm
G = 16.5dBNF = 11.8dBIIP3 = 28.6dBmFOM = 16.8dB
G = 16.2dBNF = 14.2dBIIP3 = 25.5dBmFOM = 11.3dB
G = 16.8dBNF = 11.5dBIIP3 = 28.3dBmFOM = 16.8dB
G = 18dBNF = 10dBOIP3 = 50dBm
MGA-633P8
G = 34.2dBNF = 1.7dBIIP3 = 7dBmFOM = 5.3dB
G = 18dBNF = 0.37dBOIP3 = 37dBm
Figure 35. Baseband Gain Response without LNA
FREQUENCY (MHz)0
–80
GAIN
(dB)
–70
–50
–40
–30
20
–10
40 80 1005584 F35
–60
0
10
–20
20 60 120 140 160
TC = 25°C
Figure 36. fRF = 889MHz and 890MHz 2-Tone Receiver Test, fLO = 881MHz. Ch.1 Is the I Channel and Ch.2 Is the Q Channel. Tested without LNA
LTC5584
295584f
appenDixChebychev Filter Synthesis with Unequal Terminations
To synthesize Chebychev filters with unequal terminations, two equally terminated filters are synthesized at the two different impedance levels and the resulting networks are joined using the Impedance Bisection Theorem[1]. This method only works with symmetrical odd-order filters. The general lowpass prototype element values are generated by the method shown [2]:
β = In cothLAr |dB17.37
γ = sinhβ2n
ak = sinπ 2k –1( )
2n, k = 1,2,...,n
bk = γ 2 +sin2 πkn
, k = 1,2,...,n
where LAr|dB is the passband ripple in dB, and n is the filter order.
The prototype element values will be:
g1 =2a1γ
gk =4akak–1bk−1gk−1
, k = 1,2,...,n
gn+1 = 1 for n odd
gn+1 = coth2 β4
for n even
Assuming the first element is a capacitor, we can scale the filter capacitor prototype values up to our desired cutoff frequency fC:
Ck = gk
2π • fC •RIN, k = 1,3,...,n
The filter inductor values can be scaled with:
LK = gk •RIN
2π • fC, k = 2,4,...,n Figure 37. Final Design Schematic
+
–
RIN100Ω
L1531.98nH
C153.3pF
C2258.56pF
L2106.4nH
C3266.48pF
ROUT20Ω
5585 F37
where RIN is the input impedance and the terminating impedance ROUT is equal to RIN for the n odd case but is scaled by the gn+1 prototype value for the n even case.
The Impedance Bisection Theorem can be applied to sym-metrical networks by dividing the element values along the networks’ plane of symmetry, and then adding the two networks together. The filter response is preserved.
For example, if LAr|dB = 0.2dB, fC = 40MHz, RIN = 100Ω, ROUT = 20Ω and n = 5, the prototype element values and resulting scaled filter values are listed:
Filter 1: RIN = ROUT = 100Ω
g1 = 1.339 → C1 = 53.3pF g2 = 1.337 → L1 = 531.98nH g3 = 2.166 → C2 = 86.19pF g4 = 1.337 → L2 = 531.98nH g5 = 1.339 → C3 = 53.3pF
Filter 2: RIN = ROUT = 20Ω
g1 = 1.339 → C1 = 266.48pF g2 = 1.337 → L1 = 106.4nH g3 = 2.166 → C2 = 430.93pF g4 = 1.337 → L2 = 106.4nH g5 = 1.339 → C3 = 266.48pF
The Impedance Bisection Theorem can be applied at the plane of symmetry about C2 such that a new value of C2 can be computed with half the values of the two filters.
C2→ 86.19pF
2+ 430.93pF
2= 258.56pF
The final unequally-terminated filter design values are shown in Figure 37.[1] A.C. Bartlett, “An Extension of a Property of Artificial Lines,” Phil. Mag., vol.4, p.902, November 1927. [2] G. Matthaei, L. Young, and E.M.T. Jones, Microwave Filters, Impedance-Matching Networks, and Coupling Structures, p.99, 1964.
LTC5584
305584f
appenDixImage Rejection Calculation
Image rejection can be calculated from the measured gain and phase error responses of the demodulator. Consider the signal diagram of Figure 38:
where:
RF(t) = sin(ωLO + ωBB)t + sin(ωLO – ωIM)t
LOI(t) = cos(ωLOt + φERR)
LOQ(t) = sin(ωLOt)
ωLO + ωBB is the desired sideband frequency and ωLO – ωIM is the image frequency. The total phase error of the I and Q channels is lumped into the I-channel LO source as φERR. The total gain error is represented by AERR, and is lumped into a gain multiplier in the I-channel.
After lowpass filtering the I and Q signals can be written as:
I(t)= AERR2
sin ωBBt – φERR( )– sin ωIMt+φERR( )
Q(t)= 12
cos ωBBt( )+cos ωIMt( )
Shifting the Q channel by –90° can be accomplished by replacing sine with cosine such that the shifted Q-channel signal is:
Q–90(t)= 1
2sin ωBBt( )+sin ωIMt( )
We combine I(t) + Q–90(t) and choose terms containing ωBB as the desired signal:
desired= 1
2sin ωBBt( )+ AERR
2sin ωBBt – φERR( )
Similarly, we choose terms containing ωIM as the image signal:
image = 1
2sin ωIMt( )–
AERR2
sin ωIMt+φERR( )
The image rejection ratio (IRR) can then be written as:
IRR|dB = 10log
|desired|2
|image|2
Written in terms of AERR and φERR as:
IRR|dB = 10log
|1+ AERR2 +2AERR cos φERR( )||1+ AERR2 −2AERR cos φERR( )|
Figure 39 shows image rejection as a function of amplitude and phase errors for a demodulator.
AERR
LOI(t)
LOQ(t)RF(t)
I(t)
Q(t)5585 F38
Figure 38. Signal Diagram for a Demodulator
Figure 39. Image Rejection as a Function of Gain and Phase Errors
PHASE ERROR (DEG)
10
IMAG
E RE
JECT
ION
(dB)
30
50
70
20
40
60
2 4 6 8
5585 F39
1010 3 5 7 9
AERR = 0dBAERR = 0.05dBAERR = 0.1dBAERR = 0.2dBAERR = 0.3dBAERR = 0.5dBAERR = 1dB
LTC5584
315584f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
package DescripTionPlease refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
4.00 ±0.10(4 SIDES)
NOTE:1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED2. DRAWING NOT TO SCALE3. ALL DIMENSIONS ARE IN MILLIMETERS4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT5. EXPOSED PAD SHALL BE SOLDER PLATED6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
PIN 1TOP MARK(NOTE 6)
0.40 ±0.10
2423
1
2
BOTTOM VIEW—EXPOSED PAD
2.45 ±0.10(4-SIDES)
0.75 ±0.05 R = 0.115TYP
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UF24) QFN 0105 REV B
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.70 ±0.05
0.25 ±0.050.50 BSC
2.45 ±0.05(4 SIDES)3.10 ±0.05
4.50 ±0.05
PACKAGE OUTLINE
PIN 1 NOTCHR = 0.20 TYP OR 0.35 × 45° CHAMFER
UF Package24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697 Rev B)
LTC5584
325584f
Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com LINEAR TECHNOLOGY CORPORATION 2012
LT 0412 • PRINTED IN USA
relaTeD parTs
Typical applicaTionSimplified Schematic of 900MHz Receiver, (Only I-Channel Is Shown)
D13
D0
CONTROL
VCM
VDD
LTC2185ADC
1.8V206mA
5V200mA
AIN+
AIN–
R20150Ω
C2239pF
C2139pF
R19150Ω
R1627.4Ω
R1527.4Ω
R5110Ω
R4110Ω
C231µF
5584 TA02
R1886.6Ω
R1786.6Ω
R10100Ω
R1236.5Ω
R8402Ω
R9402Ω
R720Ω
R620Ω
R1136.5Ω
R13243Ω
R14243Ω
5V52mA
C190.5pF
C200.5pF
C180.1µF
L12 180nH
L11 180nH
L8 180nH
L7 180nH
40MHz LOWPASS FILTER
L6 470nH
L35.6nH
L5 470nHL10 270nH
L9 270nH •••
C15150pF
C16150pF
C171µF
–
–+
+VOCMLTC6409
C13150pF
C14150pF
C1247pF
C947pF
C71.5pF
C20.01µF
C240.01µF
C250.01µF
I+VCC
I–RF+
RF–
LO–LO+
LTC5584
RF INPUT800MHz
TO 1000MHz
40MHz ANTI-ALIAS FILTER (AAF)
• •
T2MINI-CIRCUITS
TC1-1-13M+16
42
3
L4 3.9nHLO INPUT900MHz
6dBm C82.2pF
••
T1MINI-CIRCUITSTC1-1-13M+
1 2 3
46
C100.01µF
C110.01µF
PART NUMBER DESCRIPTION COMMENTSInfrastructureLTC5569 300MHz to 4GHz Dual Active Downconverting Mixer 2dB Gain, 26.7dBm IIP3 and 11.7dB NF at 1950MHz, 3.3V/180mA SupplyLT5527 400MHz to 3.7GHz, 5V Downconverting Mixer 2.3dB Gain, 23.5dBm IIP3 and 12.5dB NF at 1900MHz, 5V/78mA SupplyLT5557 400MHz to 3.8GHz, 3.3V Downconverting Mixer 2.9dB Gain, 24.7dBm IIP3 and 11.7dB NF at 1950MHz, 3.3V/82mA SupplyLTC6409 10GHz GBW Differential Amplifier DC-Coupled, 48dBm OIP3 at 140MHz, 1.1nV/√Hz Input Noise DensityLTC6412 31dB Linear Analog VGA 35dBm OIP3 at 240MHz, Continuous Gain Range –14dB to 17dBLTC554X 600MHz to 4GHz Downconverting Mixer Family 8dB Gain, >25dBm IIP3, 10dB NF, 3.3V/200mA SupplyLT5554 Ultralow Distortion IF Digital VGA 48dBm OIP3 at 200MHz, 2dB to 18dB Gain Range, 0.125dB Gain StepsLTC5585 700MHz to 3GHz IQ Demodulator >530MHz IQ Bandwidth, 25.7dBm IIP3, IIP2 Adjustable to >80dBm, DC Offset Null
AdjustmentLTC5590 Dual 600MHz to 1.7GHz Downconverting Mixer 8.7dB Gain, 26dBm IIP3, 9.7dB Noise FigureLTC5591 Dual 1.3GHz to 2.3GHz Downconverting Mixer 8.5dB Gain, 26.2dBm IIP3, 9.9dB Noise FigureLTC5592 Dual 1.6GHz to 2.7GHz Downconverting Mixer 8.3dB Gain, 27.3dBm IIP3, 9.8dB Noise FigureRF PLL/Synthesizer with VCOLTC6946-1 Low Noise, Low Spurious Integer-N PLL with
Integrated VCO373MHz to 3.74GHz, –157dBc/Hz WB Phase Noise Floor, –100dBc/Hz Closed-Loop Phase Noise
LTC6946-2 Low Noise, Low Spurious Integer-N PLL with Integrated VCO
513MHz to 4.9GHz, –157dBc/Hz WB Phase Noise Floor, –100dBc/Hz Closed-Loop Phase Noise
LTC6946-3 Low Noise, Low Spurious Integer-N PLL with Integrated VCO
640MHz to 5.79GHz, –157dBc/Hz WB Phase Noise Floor, –100dBc/Hz Closed-Loop Phase Noise
ADCsLTC2145-14 14-Bit, 125Msps 1.8V Dual ADC 73.1dB SNR, 90dB SFDR, 95mW/Ch Power ConsumptionLTC2185 16-Bit, 125Msps 1.8V Dual ADC 76.8dB SNR, 90dB SFDR, 185mW/Channel Power ConsumptionLTC2158-14 14-Bit, 310Msps 1.8V Dual ADC, 1.25GHz Full-Power
Bandwidth68.8dBFS SNR, 88dB SFDR, 362mW/Ch Power Consumption, 1.32VP-P Input Range