1

M-PCIe Eye Diagram Diagnostic Improvement

Tsung-Jen Chuang

Department of Electrical Engineering

National Taipei University of Technology

Taipei, Taiwan, R.O.C.

graham0424@gmail.com

Kuang-Yow Lian , Professor Department of Electrical Engineering

National Taipei University of Technology

Taipei, Taiwan, R.O.C.

kylian@mail.ntut.edu.tw

Abstract—The objective was to improve the M-PCIe signal

integrity of Eye Diagram. The method was to analyze the M-PCIe

transmission signal and improve signal integrity by coupling

capacitor De-emphasis. The Eye Diagram of signal improvement

from the experimental result was compared for the followings:

Jitter, voltage noise tolerance, signal stability and zero-crossing

rate. Ultimately, this study successfully improved the signal

transmission of M-PCIe on mobile device to achieve optimal

signal integrity.

Keywords—M-PCIe; PCIe; Mobile Device; Eye Diagram

INTRODUCTION

Mobile device has become the most common

entertainment and communication tool in people’s lives and

the complexity of mobile device interface has been enhanced

with the ever-increasing demand for functionality. In order to

simplify the interface design and reduce the incompatibility

risk, the MIPI (Mobile Industry Processor Interface) Alliance

is committed to promote the standard to improve the interface

technology system with solution to assist developers to

overcome various corresponding interface design technologies

for the devices.

The MIPI specification provides three key features in the

face of the design technology required for the mobile device

industry, including high performance, low power consumption,

and low EMI (electromagnetic interference). The

high-performance interface has a large number of image data

processing capabilities and works on the high-pixel camera of

a mobile device. It also meets the demand of a 4K ultra-high

quality screen. The transmission speed must also reach 4G

LTE and 802.11ac Wi-Fi standard. Low power consumption is

also a prerequisite. The MIPI interface uses low-power

signaling for transmission when operating or idling, to reduce

the power usage and help to elongate the battery life to

prolong the usage time of mobile device for user. As for the

feature of low electromagnetic interference, it can effectively

reduce the interference in mobile device caused by many radio

interfaces. The MIPI interface effectively achieve low EMI by

technologies such as voltage slew rate control, low voltage

swing and etc., that each radio interface can coexist in a device.

It also avoids any interference from collision in mobile device

or the screen.

PCIe (PCI Express) specification has been widely studied

and used as a standard type of connection for internal devices

in PC. However, in the mobile market, to further achieve the

goal of reducing power consumption for current PCIe, there

are two major problems to overcome: the first is the high

power consumption of PHY of PCIe standard; the second is its

long latency when moving in and out of low-power state for

highly responsive mobile device. By contrast, M-PCIe

(Mobile PCI Express) specification makes PCIe architecture to

work over the MIPI M-PHY physical layer technique, further

extending the advantages of the PCIe I/O specification to

mobile devices. M-PCIe retains the higher hierarchy of PCI

specification and PCIe programming model. When compared

with similar PCIe designs, M-PCIe can significantly reduce

power consumption. By designing architecture in avoidance of

the state of heavy power consumption, the M-PHY has

prolonged battery life by minimizing the amount of power

consumed by all components in the design architecture.

To improve the signal integrity in high-speed transmitted

M-PCIe, two cases were presented in this study. Case I

improved PCIe jitter by coupling capacitor and Case II

analysis the eye diagram under strengthen signal.

EYE DIAGRAM

Eye diagrams are a common indicator that intuitively

assesses the quality of digital signal transmissions, it is

constructed by overlaying every possible bit sequence. The

eye diagram is a visual method to analyze the signal integrity

of a design [1]. Figure 1 shows common parameter of an eye

diagram.

Fig 1. Eye Diagram Parameter [1]

High Level - Fig 1.(A) shows the value of a logic high. The

measured value of the high level comes from the average

value of all the data samples measured in the upper 80% of the

eye diagram.

Low Level - Fig 1.(B) is the main value of a logic low. This

level is computed from the lower 40 to 60% region of the

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baseline area measured in the eye diagram.

Eye Amplitude - Fig 1.(C) is the difference between the high

and low levels. The data Rx port circuits will determine

whether received data bit is a “0” or “1”, based on amplitude.

Bit Period - Fig 1.(D) is a capture of the horizontal opening of

an eye pattern at the crossing points of the eye, and it is

usually captured within picoseconds for a digital high-speed

signal.

Eye Height - Fig 1.(E) is the vertical opening of an eye pattern.

Ideally, an eye height would equal the eye amplitude.

Eye Width - Fig 1.(F) is a capture of the horizontal opening of

an eye pattern. It is computed as the difference between the

statistical averages of the crossing points of the eye.

Eye Crossing Percentage - Fig 1.(G) shows duty cycle

distortion or pulse symmetry problems. An ideal signal is 50

percent, as the percentage deviates, the eye closes and

indicates degradation of the signal. The eye crossing

percentage is then computed using the following formula:

Eye Crossing % = Cross level − Zero level

One level − Zero level

For an ideal transmission system, the eye should be as

wide and open as possible. Figure 2 shows additional

measurements on an actual eye diagram.

Fig 2. Real World Eye Diagram [1]

Rise Time - Fig 2.(A) is the average transition time of the data

bit on the upward slope of an eye pattern. The rise time should

be as small as possible.

Fall Time - Fig 2.(B) is the average transition time of the data

bit on the downward slope of an eye pattern. The fall time

should be as small as possible.

Distortion - The width of the logic high value is the amount of

Fig 2.(C), which is determined by the signal to noise ratio.

SNR (Signal to noise ratio) - Fig 2.(D) of the signal difference

in logic high to low relative to the noise present at both levels.

Jitter - Fig 2.(E) is the time bias from the ideal timing of a

data-bit event and is the most important indicator of a digital

high-speed signal. The jitter is computed by measuring the

time bias of the interim of the rise and fall edges at the

crossing point of an eye diagram.

Decision Point - Fig 2.(F) is the most opening part of the eye,

which is the best signal to noise ratio.

Because of noise and jitter in signal, the blank area on the

eye diagram becomes smaller, as shown in Figure 3. Generally,

the more open of the eye pattern, the lower the possibility that

the Rx port in the transmission system will mistake a logic

high for a logic low.

Fig 3. Voltage noise and jitter [1]

M-PCIE

The M-PCIe standard extends the current PCIe

architecture to the mobile world. MIPI M-PHY provides the

physical technology of high-performance and low-power

required to perform the needs of today's mobile devices. The

use of the PCIe protocol through the M-PHY physical layer

for the mobile industry has brought a scalable solution to

achieve a variety of device interoperability and consistent user

experience. The M-PCIe has three grades of transmission rate,

with the first at 1.25-1.45 Gbps, the second at 2.5-2.9 Gbps,

and the third at 5.0-5.8 Gbps, which implies the slowest rate at

156 MB / s and the fastest rate at 725 MB / s.

The MIPI Alliance's interface content, which can be

classified under four major categories of the standard

architecture, provides technologies that can effectively

interconnect the mobile device. The four categories include:

Multimedia, Chip-to-Chip Inter-process Communications,

Control / Data, and Debug / Trace.

Multimedia interface is popular in the market, with

support for camera, monitors, audio codec, microphone,

speakers, memory, FM radio, near field communication (NFC),

bluetooth and GPS applications. For example, the camera

serial interface (CSI) and the display serial interface (DSI) are

designed for their specifications to support high-resolution

images, improve the image transmission speed, and satisfy

consumers’ need for mobile devices with high-quality image

capability. The chip-to-chip interface is widely used. This

high-speed transmission interface provides inter-process

communication (IPC) functionality between application

processors and 4G LTE or Wi-Fi microcontrollers. The control

and data interface is used in batteries, sensors, and RF

front-end equipment. For example, the sensor interface "I3C"

in this category is able to reduce design challenges and

integrate effectively the increasing number of sensors.

In addition, the M-PCIe/M-PHY hybrid channel can be

used between SoC processors and WLAN wireless modules,

WiGig/Wireless HD wireless display modules, baseband,

auxiliary and bridged chips. The M-PHY physical layer can be

used for SoC processors with the camera, display, large

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storage area equipment, baseband, and RFIC, as shown in

Figure 4 [2]. MIPI Alliance’s M-PHY has proven to be the

preferred physical layer standard for meeting high

performance and low power requirements for tablets and

smartphones. PCI-SIG works with the new M-PCIe standard

to deliver product in a significantly shorter development and

verification cycle for users. The standard allows them to focus

on the physical layer interface for the mobile device.

To further lower power consumption, the M-PCIe system

can achieve asymmetric link that allows dissimilar numbers of

transmitters and receivers on the circuit loop. The PCI Express

specification enables the device to have four transmitters and

four receivers to meet their need for four channels of PCIe to

cellular bandwidth. In cases where PCI Express has an equal

number of transmitter receivers to accommodate its unilateral

maximum bandwidth, M-PCIe allows the device to reduce the

required number of transmitters, and in this case only 2

channels, as shown in Figure 5 [3].

Although the M-PCIe standard allows system to consume

less power than PCIe, PCIe delivers faster than M-PCIe. The

M-PHY of M-PCIe has three gears designed for the signal rate.

In very common terms, one can consider that M-PHY Gear M

as being the same bandwidth as the relevant Generation (M-1)

of PCIe signaling. See Table 1. In this case, selecting an

M-PHY for its low power consumption both decreases the

maximum trace lengths which can be used in an M-PCIe

design and limits link speeds to less than what could be

attained with PCIe 3.0 - 8GT/s signaling – to meet for current

M-PHY (M-3).

EXPERIMENT RESULT

PCIe has been widely used in a variety of electronic

products and become more adaptable to development of

mobile device with the M-PCIe architecture as the technology

advances. In this section, several methods to improve the

M-PCIe signal integrity were proposed for actual application

on a mobile device to measure the signal integrity of the

M-PCIe in eye diagram with an oscilloscope and a differential

probe. The experimental equipment was listed in Table 2. The

bandwidth of the oscilloscope should be greater than 12 GHz

[4]. This study used the Agilent-90804A oscilloscope, the

differential probe model 1131A, and the application, U7238A

MIPI D-PHY Test App.

In this study, differential receiver input voltage is 150 mV

and a bit time is about 150 ns. According to PCIe-SIG,

determine the mask of M-PICE eye high is 150 mV, eye width

is 125 ns.

Case I : Improve PCIe Jitter by coupling capacitor

The coupling capacitor, which helped to improve the

integrity of PCIe transmission signal has been widely studied.

Wang proposed in 2013 the patent structure for PCIe to add

AC coupling capacitors for the communication between the

chips on the same platform [5]. AC coupling capacitors are

necessary for blocking DC and delivering AC. Signal integrity

is set to zero level by AC coupling capacitors. Unfortunately,

jitter increase while AC coupling capacitance is not large

enough. There is a component reduction because coupling

capacitors present the inductive in high-speed. The

Type of oscilloscope

Max

bandwidth

Sample

rate

Noise floor

@100mV/div

Tektronic-91604A

Agilent-90804A

Agilent-91204A

16 GHz

13 GHz

12 GHz

80 GSa/s

40 GSa/s

40 GSa/s

2.68 mV

3.37 mV

2.80 mV

Table 2. This study is for high-speed signal, the max bandwidth of oscilloscope should be over 12 GHz.

Table 1. M-PCIe vs PCIe Link Speeds

Fig 5. M-PCIe asymmetric links [3]

Fig 4. MIPI Interface Technology System [2]

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capacitance range should be between 75 nF and 500 nF. PCIe

transmission used a differential signal, when designing the

transmitter and the receiver, the two must be close to each

other to reduce EMI interference from other differential signal.

The transmitter and the receiver should be in the same layer

with the impedance of differential signal path (trace) was best

designed to 100 ohms (±15%).

According to Wang's patented structure, the M-PCIe

specification on the mobile device was illustrated in Figure 6.

In this study, the working frequency of M-PCIe is 100 MHz,

impedance of differential signal trace (Xc) is 138 ohms, seen

below Equation (1):

Fequence = 1

2𝜋∙Xc∙𝐶 (1)

Calculation of coupling capacitor between M-PCIe and

the transmission side is 220 nF. Table 3 is showed the jitter of

different capacitors that form 150 to 250 nF were set between

the M-PCIe and the transmitter. When M-PCIe is added 150nF,

200nF, 220 nF and 250nF coupling capacitor, jitters are

produced 72 ns, 43 ns, 30 ns and 46 ns, respectively. 220nF

Coupling capacitor produce jitter is the lowest of all. It is less

than the value (86 ps) which PCIe-SIG defined. We proved

220nF coupling capacitor is the best structure for M-PCIe

signal integrity improvement.

Case II : Analysis the eye-diagram under strengthen

signal

To improve the signal integrity of M-PCIe application on

mobile devices, it was necessary to understand the relationship

between the transmission signal and the strength. Ren et al.

pointed out that as the cross signal passed through the filter [6],

the filter coefficient could be used to convert the output signal

into the equivalent equation, such as shown in Equation (2):

Vout_n = Vin_n-1 *︱c-1︱ + Vin_n *︱c0︱ + Vin_n+1 *︱c+1︱ (2)

c-1, c0and c+1were pre-cursor, cursor, and post-cursor

coefficients, respectively. The Transmitter would use the

default value from the register, or from the recipient value of

the Link Training and Status State Machine (LTSSM) . In

order to clearly quantify the signal transmission status, a new

term was defined in the PCIe 3.0 protocol. Yeung et al., in the

patent report proposed in 2014 that as cross-signals passed

through filter [7], the signals were defined separately as Va, Vb,

Vc and Vd as shown in Figure 7. as quantified De-emphasis,

seen in Equation (3):

De-emphasis = －20 * log10

𝑉𝑎

𝑉𝑏 (3)

Pre-shoot quantification equation (4):

Pre-shoot = 20 * log10

𝑉𝑐

𝑉𝑏 (4)

The two new parameters, Full Swing (FS) and Low

frequency (LF), were defined in the PCIe 3.0 specification to

describe the voltage characteristics. The maximum differential

voltage generated by the transmitter could be described by FS

in order to maintain a constant output voltage. The FS was

given by Equation (5):

FS = ︱c-1︱＋︱c0︱＋︱c+1︱ (5)

The minimum differential voltage generated by the

transmitter could be described by LF, and the flat voltage of

the transmitter must be greater than the minimum differential

voltage. The LF was given by Equation (6):

c0 －︱c-1︱－︱c+1︱≧ LF (6)

The upper limit of Pre-shoot was defined by Equation (7):

︱c-1︱≦ 𝐹𝑆

4 (7)

Corresponding default coefficient values of De-emphasis for

the transmitter, with the use of dynamic equalization for

automatic configuration to achieve the best compensation.

The experiment compared the M-PCIe setting of

De-emphasis at 0 dB and -6 dB on a mobile device to analyze

the transmitter’s eye diagram to obtain the best signal integrity.

Figure 8 shows eye diagram of transmission signal with

M-PCIe setting of De-emphasis at 0 dB and -6 dB for the

transmitter. When De-emphasis was 0 dB, as seen in Fig 8

(a), the eye height of the blue area was 160 mV. When

De-emphasis was -6 dB as seen in Fig 8 (b), the eye height of

the red area was 360 mV. Eye height showed the Voltage noise

tolerance during signal transmission [8]. Therefore, it was

found that the tolerance level for signal transmission was

better with the M-PCIe transmitter’s De-emphasis at -6 dB

than at 0 dB. As shown by Fig 8 (c), the Eye width of blue

Fig 7. Shows Va, Vb,Vc and Vd voltage by the differential signal. [13]

Coupling capacitor (nF)

Jitter (ps)

150 200 220 250

72 43 30 46

Table 3. Showed that form 150 to 250 nF capacitors were set between the M-PCIe and the transmitter.

M-P

CI E

xp

ress Interface

Transmitter

Receiver

Coupling capacitorApplication

Processor

(Host)

M-P

CI E

xp

ress Interface

M-P

CI E

xp

ress Interface

Transmitter

Receiver

Coupling capacitorApplication

Processor

(Host)

Fig 6. Sketch map shows coupling capacitor between M-PCIe and transmitter/receiver.

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area in the eye diagram was 150 ps. In Fig 8 (d), the Eye width

of blue area in the eye diagram was 187 ps. Eye width

reflected the time of signal transmission stability [9]. It

showed that the signal transmission was more stable with the

M-PCIe transmitter’s De-emphasis at -6 dB than at 0 dB.

Since the eye diagram was a multiple map overlap, it was

possible to analyze the amplitude of signal jitter [10]. When

the M-PCIe transmitter’s De-emphasis was -6 dB for signal

transmission, the rise time was significantly faster than the

time with De-emphasis at 0 dB, and the amplitude was smaller

than De-emphasis at 0 dB. The intersection of transmitter’s

positive signal and negative signal formed a cross-point area,

which represented the zero-crossing rate [11][12]. As seen in

Figure 11, the cross-point area for the M-PCIe De-emphasis at

0 dB was Δ@0db. And, the area for the M-PCIe De-emphasis at

-6 dB was Δ@-6db. The result showed areas of Δ@0db and

Δ@-6dbwere respectively 3938 Unit and 1131 Unit. The area of

Δ@-6db, in comparison with the area of Δ@0db, was reduced by

71.3%, proving that the zero-crossing rate of M-PCIe

De-emphasis of -6 dB was smaller than M-PCIe De-emphasis

of 0 dB.

CONCLUSION

PCI has been widely studied since 1992 and applied to all

kinds of electronic products. With technological advancement,

PCIe technology needs a revolutionary innovative

breakthrough. In addition to increasing transmission rate,

structural adjustment to improve signal integrity is an

important part of future development. The purpose of this

study was to improve the signal integrity of the M-PCIe on the

mobile device and to analyze the signal stability with the eye

diagram to achieve optimal transmission efficiency.

AC coupling capacitors are necessary for blocking DC

and delivering AC. Signal integrity is set to zero level by AC

coupling capacitors. However, AC coupling capacitors also

cause jitter. This study design a 220 nF coupling capacitors

between M-PCIe and the transmission side, the result shows

the jitter at rise edge of eye-diagram is 30 ps, which is

significantly lower than 86 ps (Value is defined by PCIe-SIG).

To improve the signal integrity of M-PCIe application on

mobile devices, the Eye Diagrams of De-emphasis of 0 dB and

-6 dB were compared to find that Eye Height at -6dB was 360

mV, which was greater than the Eye Height of 160mV at 0 dB,

proving a better voltage noise tolerance with De-emphasis at

-6 dB. Besides, the Eye Width with De-emphasis of -6 dB was

187 ps, greater than De-emphasis of 0 dB (150 ps), suggesting

a more stable signal transmission on mobile device when

M-PCIe transmitter’s De-emphasis was -6 dB. In addition, the

intersection areas of transmitter’s positive and negative signals,

respectively the Δ@0db and the Δ@-6db, were 3938 Unit and

1131 Unit. The result showed that Δ@-6db was reduced by

71.3%. It proved that the zero-crossing rate for signal

transmission on mobile device was smaller when M-PCIe

Δ@0db

Δ@-6 dbUnit = mV．ps

Area = 1131 Unit

Area = 3938 Unit Δ@-6 db

Δ@0db

Fig 9. The blue area was the intersection of transmitter’s positive and negative signals when De-emphasis was 0 dB. The red area was the intersection of transmitter’s positive and negative signals when De-emphasis was -6 dB.

150 ps

(c)

(d)

187 ps

(a)

160 mV

(b)

360 mV

Fig 8. The single-bits eyes show of M-PCIe TX. (a) Eye height is 160 mV when de-emphasis is 0 dB. (b) Eye height is 360 mV when de-emphasis is -6 dB. (c) Eye width is 150 ps when de-emphasis is 0 dB. (d) Eye width is 187 ps when de-emphasis is -6 dB.

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transmitter’s De-emphasis was -6 dB.

The coupling capacitor designed in this study

successfully improved the jitter at rise edge and from

comparison of eye diagrams for M-PCIe transmitter signal on

mobile device showed the best signal integrity when

De-emphasis was -6 dB. The study proved that M-PCIe could

be a good application on mobile device and used as a protocol

for high-speed transmission module in the future.

REFERENCES

[1] Instrument Fundamentals Digital Timing(2016, DEC 30) www.ni.com/white-paper/3299/en

[2] Chris A. Ciufo (2013, June 25) PCI-SIG “nificant” Changes Brewing in Mobile http://eecatalog.com/caciufo/tag/mipi-alliance/

[3] Richard Solomon, Using M-PCIe for Low-Power PCI Express Designs https://www.synopsys.com/designware-ip/technical-bulletin/m-pcie-express-designs.html

[4] TTC, TTC. "How to Test a MIPI M-PHY High-Speed Receiver Challenges and Agilent Solutions."

[5] F. Wang, “Chip comprising a signal transmitting circuit, communication system between multiple chips and its configuration method”, US Patent, vol. 8, no. 416, pp. 868, 2013.

[6] J. Ren and et al., “A Precursor ISI reduction in high-speed I/O”, IEEE Symposium on VLIS Circuits, pp. 134-135, 2007.

[7] T. Yeung and et al., “Signal conditioning by combining precursor, main, and post cursor signals without a clock signal”, US Patent, vol. 8, no. 755, pp. 474, 2014.

[8] S.Y. Yuan and et al., “A bus-inverted coding scheme to improve data-dependent PCI power integrity”, IEEE Trans. Electromagn. Compat, vol. 50, pp. 985, 2008.

[9] N. Ambasana and et al, “Eye height/width prediction from S–parameters using learning-based models sign in or purchase”, IEEE Trans. Electromagn. Compat, vol., pp. 873, 2016.

[10] A. Laboratories and et al, “Effects of Deterministic Jitter in a Cable on Jitter Tolerance Measurements”, IEEE ITC., vol. 1, pp. 58, 2003.

[11] M. Li and et al, “Paradigm shift for jitter and noise in design and test > Gb/s communication systems (an invited paper for ICCD 2003)”, IEEE, vol. 10, pp. 467, 2003.

[12] M. Li and et al, “Jitter And Signaling Test For High-Speed Links”, IEEE, vol. 10, pp. 65, 2006.

[13] SIGNAL INTEGRITY JOURNAL, Ensuring High Signal Quality in PCIe Gen3 Channels https://www.signalintegrityjournal.com/articles/ 358-ensuring-high-signal-quality-in-pcie-gen3-channels

Acknowledgement

This research was supported by the Ministry of Science and Technology, R.O.C, under Grant MOST-105-2221-E-027-061.