Circuits Intégrés Analogiques - 2014/2015 - Chapitre 4 20/10/2014
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M2 EEA – Systèmes Microélectroniques Polytech’montpellier – MEA 4
Analog Integrated Circuits Design Chapter IV
Basic and Advanced Current Sources
Pascal Nouet / 2014-2015 [email protected]
http://www2.lirmm.fr/~nouet/homepage/lecture_ressources.html
Lecture material download
http://www2.lirmm.fr/~nouet/homepage/lecture_ressources.html
Circuits Intégrés Analogiques - 2014/2015 - Chapitre 4 20/10/2014
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Introduction
• Analog Integrated Circuits are based on elementary stages – Voltage references – Current mirrors – Current sources – Amplifier stages
• Main characteristics of a current mirror – Current flow to Vss (ground) or from Vdd – Coefficient of recopy – Quality of recopy
• High output resistance • Range of output voltages (output dynamic)
Outline
• Elementary current mirror – Principle – Output resistance
• Elementary stages for increased output resistance
• Other elementary current mirrors • Elementary current sources • Overview of advanced current sources • PMOS current sources
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Current mirroring principle
• Biasing (Large Signal Analysis): – T1 is saturated è Iin = Ids1 = f(Vgs1) = f(Veff1) – T2 must be saturated to deliver a constant current
• Veff2=Veff1 à Output dynamic: Vds ≥ Veff
• Small-Signal Analysis à Output resistance
Vs
Iin IS
T1 T2 vs
gm.vgs2 rds2 vgs2
iS
1/gm1
Is = Idsat =µnCox2
WLVeff2 = Iin
vsis= rds2 =
1λIdsat
Elementary current mirror: output resistance
Vs
Iin IS
T1 T2
Impact of Idsat
y = 0,0044x
0,00E+00
5,00E-‐02
1,00E-‐01
1,50E-‐01
2,00E-‐01
2,50E-‐01
3,00E-‐01
3,50E-‐01
4,00E-‐01
4,50E-‐01
5,00E-‐01
0,00E+00 2,00E+01 4,00E+01 6,00E+01 8,00E+01 1,00E+02
gds (µA/V)Linéaire (gds (µA/V))
Ids (µA) Vds (V)
Ids (A)
gds (µA /V ) =1
rds (MΩ)≅ λ(V −1) ⋅ Idsat (µA)
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Elementary current mirror: output resistance
Vs
Iin IS
T1 T2
Impact of transistor length
Vds (V)
Ids (A)
y = 0,093x + 2,718
0,00E+00
2,00E+00
4,00E+00
6,00E+00
8,00E+00
1,00E+01
1,20E+01
1,40E+01
0,00E+00 2,00E+01 4,00E+01 6,00E+01 8,00E+01 1,00E+02
rds (Mohms)
L (µm)
rds ≅Ve(V / µm) ⋅L(µm)
Idsat (A)+ r0
Elementary current mirror: output resistance
Vs
Iin IS
T1 T2
Impact of transistor size (W/L)
Vds (V)
Ids (A)
0,0
0,5
1,0
1,5
2,0
2,5
3,0
3,5
4,0
4,5
0 10 20 30 40 50
rds (Mohms)
W/L
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Elementary current mirror: summary
• Impact of Idsat – Output resistance is divided by two
when current is multiplied by two
• Impact of transistor size – Output resistance doubled when transistor length is
multiplied by two (constant W/L)
• Useful equations – Working with constant Veff
and transistor length
– General case à rds α L
Vs
Iin IS
T1 T2
isvs=1rds=∂Ids∂Vds
≅ λ(V −1) ⋅ Idsat (A)
rds ≅Ve(V / µm) ⋅L(µm)
Idsat (A)+ r0
Outline
• Elementary current mirror • Elementary stages for increased output
resistance – Degenerated source current mirror – Cascode current mirror
• Other elementary current mirrors • Elementary current sources • Overview of advanced current sources • PMOS current sources
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Degenerated source current mirror
• Large-Signal Analysis – T1 always saturated – Output dynamic à saturation of T2
• Small-Signal Analysis – Output resistance
vs
Rs vs2
iS
Rs
gm2.vgs2 rds2 vg2
1/gm1 Iin IS
T1 T2
Rs Rs
effinSS VIRV +>
( )smdss
S Rgriv
22 1+≅Is = Idsat =µnCox2
WLVeff2 = Iin
Degenerated source current mirror
Impact of Rs
50µA IS
T1 T2
Rs Rs
y = 0,9914x + 3,4627
0,0
5,0
10,0
15,0
20,0
25,0
0 5 10 15 20 25
rout (MOhms)
Rs(kΩ)
rout = rds2 + 1+ gm2rds2( )Rs → gm2rds2 ≅2IVeff
1λnI
=2
λnVeff≈1000
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Outline
• Elementary current mirror • Elementary stages for increased output
resistance – Degenerated source current mirror – Cascode current mirror
• Other elementary current mirrors • Elementary current sources • Overview of advanced current sources • PMOS current sources
Cascode current mirror
• Large-Signal Analysis – T1 and T3 are saturated, T2 also – Output dynamic à saturation of T4
• Small-Signal Analysis – Output resistance
Iin IS
T1 T2
T3 T4 vs gm2.vgs2 rds2
vg2
iS
1/gm1
gm4.vgs4 rds4 vg4
1/gm3
vs2
vs4
efftnS VVV ⋅+> 2
424 dsdsmS
S rrgiv
≅
VS
Id1 = Id2 = Id3 = Id 4 = Iin
Is = Idsat =µnCox2
WLVeff2 = Iin
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Cascode current mirror
200µA IS
T1 T2
T3 T4
Impact of W/L
Vds (V)
Ids (A)
0
100
200
300
400
500
600
700
800
1 10 100
rout (MOhms)
W/L
Outline
• Elementary current mirror • Elementary stages for increased output
resistance • Other elementary current mirrors • Elementary current sources • Overview of advanced current sources • PMOS current sources
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Wilson current mirror
• Similar performance to cascode mirror
• Substrate bias effect:
Iin IS
T1 T2
T3 T4 vx
vgs1
ix
1/gm2
gm4.vgs4 rds4 vgs4 1/gm3
gm1.vgs1 rds1
( ) 4144 dsdssms
S rrggiv
+≅⇒
indddd IIIII ==== 4321
Is = Idsat =µnCox2
WLVeff2 = Iin VS >Vtn + 2 ⋅Veff
vSis≅ gm4rds1rds4
PMOS Current Mirrors
• Every NMOS current mirror has a PMOS dual • Caracteristics are identical and easy to
transpose: Vsmin à Vsmax, rout
IS
Iin
Vdd
T2 T1
T4 T3
IS
Iin
Vdd
T2 T1
T4 T3 IS
Iin
Vdd
T2 T1 IS
Iin
Vdd
T2 T1 RS RS
rout ≅ rds
rout ≅ gmrdsrds
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Non-symetrical mirrors
• Different ratio W/L may be used in the output branch (generally X>1 à output current higher than reference current)
• Same Veff for all transistors means current proportionnal to W/L:
Vs
Iin IS
T1 T2
1 : X
Vs
Iin IS
T1 T2
T3 T4
1 : X
Iin IS
T1 T2
T3 T4 Vs
1 : X
in2neff
2out
in2neff
1out
tneff2S
tneff1S
2Sin1S
I.XV
2r
IV
2r
VV.2V
VV.2VXI
II
λ≅
λ≅
+>
+>
==
inn2out
inn1out
eff2Seff1S
2Sin1S
I.X1
rI1
r
VVVVXI
II
λ≅
λ≅
>>
==
;
;
Multiple outputs current mirrors
• One reference branch may be connected to as many output branches as recessary for the application
• Each output may deliver a different ratio of current • Each output may have a different output resistance
Iin VS1
IS1
VS2 IS2
nLW
= nLW
=
nXLW
=
nLW
= nLW
=
nXLW
=
VS1 Iin IS1
nLW
= nLW
=
IS2
nXLW
=
VS2
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1,00E+03
1,00E+04
1,00E+05
1,00E+06
1,00E+07
1,00E+08
1,00E+09
1,00E+10
0,00 0,50 1,00 1,50 2,00 2,50 3,00 3,50
Miroir simple
SD1
SD2
Cascode
Wilson
Overview of output resistance of elementary current mirors
)(ΩoutR
)(VVS
Outline
• Elementary current mirror • Elementary stages for increased output
resistance • Other elementary current mirrors • Elementary current sources
– Resistance biasing – Transistor biasing – Impact of Vdd and T°C
• Overview of advanced current sources • PMOS current sources
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From current mirrors towards current sources
• Analog Integrated Circuits are based on elementary stages – Voltage references – Current mirrors – Current sources – Amplifier stages
Vdd
R
Vs
Iin IS
T1 T2
I=f(V)
T1
Ibias Iout
Vdd
T2
Rp
V1
Current flowing through ground
or from Vdd
Ideal versus actual current sources
Is0
VS
I0
VS
IS
Vmin
ROUT
Vdd ö
Vdd ø
Output Resistance and dynamics
Sensitivity to Vdd and T°C
Power consumption
Rout
ISmin
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Resistance biasing
• NMOS current sources
• Sizing – Output dynamics à Veff – Output current (Iout) à W/L of T2 (T4) – X à Reference current (Iin) à W/L of T1 (T3), Rp
1 : X
T1
Ibias Iout
Vdd
T2
Rp Vout > Veff
V1
Iout
T1 T2
T3 T4
1 : X
Ibias
Vdd
Rp
> Vtn+2Veff
Iout
T1 T2
T3 T4
1 : X
Ibias
Vdd
Rp
> Vtn+2Veff
Output resistance calculation (e.g. Wilson Current Source )
vx
vgs1
ix
1/gm2
gm4.vgs4 rds4 vgs4 1/gm3
gm1.vgs1 rds1
( )
( ) ( ) ( )2
12
14
11
31
114
11
31
1
111
1)(.
1
m
xpm
m
xgsgs
gsgs
mdsp
pdsmppg
gsm
mdsp
dsp
gi
Rggi
AvAv
Avv
grR
RrgRiRv
vg
grR
rRi
+−≅+−=+−=
−=++
−=−=
++=
Iout
T1 T2
T3 T4
1 : X
Ibias
Vdd
Rp
> Vtn+2Veff Rp
( )
( )
( ) ( ) dspmdsm
out
xdsm
mds
mx
gsmxdsm
xx
rRgrAg
r
irgg
Arg
v
vgirgi
v
⋅+≅⋅++=
##$
%&&'
(+++=
−+=
12
42
44
2
4442
221
11
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Transistor biasing
1 : X
T1
Ibias Iout
Vdd
T2
Rp Vout > Veff
V1
Iout
T1 T2
T3 T4
1 : X
Ibias
Vdd
Rp
> Vtn+2Veff
Iout
T1 T2
T3 T4
1 : X
Ibias
Vdd
Rp
> Vtn+2Veff
Ibias
Vdd
Tp Ibias
Vdd
Tp
Ibias
Vdd
Tp
• NMOS Current Sources
– Output dynamics à Veff – Output current (Iout) à W/L of T2 (T4) – X à Reference current (Iin) à W/L of T1 (T3), Tp
Outline
• Elementary current mirror • Elementary stages for increased output
resistance • Other elementary current mirrors • Elementary current sources
– Resistance biasing – Transistor biasing – Impact of Vdd and T°C
• Overview of advanced current sources • PMOS current sources
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Impact of Vdd
I0
VOUT
IS
Vmin
ROUT
Vdd ö
Vdd ø
Vout fixe
Resistance biasing
iout
gm2.v1 rds2 v1
Rp
1/gm1
vdd
)(
2
21
1
21
11
TTIIIVV
R
VLWC
I
VVV
outbias
bias
ddp
effoxn
bias
tneff
==
−=
⋅⋅=
+=
µ
T1
Ibias Iout
Vdd
T2
Rp Vout=2V (>Veff1)
V1
( )
( ) dddd
outpm
ddm
out
out
dd
dd
outpm
ddm
out
out
out
out
pm
ddmmout
VV
IRgVg
II
Vv
IRgVg
Ii
II
Rgv
gvgi
Δ⋅
+=
Δ
⋅+
==Δ
+==
1
2
1
2
1212
1
1
1.
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Transistor biasing
iout
gm2.v1 rds2 v1 1/gm1
vdd
1/gm3
( ))(
2
2
21
2
13
3
21
1
1
11
TTII
VVVLWC
I
VLWC
I
VVV
outbias
tpddoxp
bias
effoxn
bias
tneff
==
−−⋅⋅=
⋅⋅=
+=
µ
µ
T1
Ibias Iout
Vdd
T2
Vout=2V (>Veff1) T3
V1
dd
dd
effeff
dd
out
out
dd
dd
effeff
dd
bias
out
out
out
effeff
bias
mm
mm
mm
ddmmmout
VV
VVV
II
Vv
VVV
Ii
II
VVI
gggg
ggvg
gvgi
Δ⋅
+=
Δ
⋅+
==Δ
+=
+
+==
31
31
3131
32
31
3212
2
2
2
.
Impact of Vdd on Current Sources
Vdd (V)
Iout (A)
T1
Ibias Iout
Vdd
T2
Rp Vout=2V
T1
Ibias Iout
Vdd
T2
Vout=2VT3
dd
dd
out
out
VV
II Δ
⋅=Δ 21,1
dd
dd
out
out
VV
II Δ
⋅=Δ 77,2
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Impact of Vdd on Current Sources
T1
Ibias Iout
Vdd
T2
Rp Vout=2V
dd
dd
out
out
VV
II Δ
⋅=Δ 21,1
Rp Vout=2V
Iout
T1 T2
T4
T3
Vdddd
dd
out
out
VV
II Δ
⋅=Δ 55,1
Vdd (V)
Iout (A)
Resistance biasing and temperature
• An increase in temperature reduces the saturation current of a transistor
T1
Ibias Iout
Vdd
T2
Rp Vout=2V (>Veff1)
V1
9,20E+01
9,40E+01
9,60E+01
9,80E+01
1,00E+02
1,02E+02
1,04E+02
1,06E+02
-‐40,00 -‐20,00 0,00 20,00 40,00 60,00 80,00
Polarisation par résistance
Polarisation par résistance
-0,08 %/°C
)(µAIout
)C.(Temp °
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Resistance biasing and temperature
• Resistance may also change with temperature
T1
Ibias Iout
Vdd
T2
Rp Vout=2V (>Veff1)
V1
-0,08%/°C
( )T.TCR1RR 0pp +=
8,00E+01
8,50E+01
9,00E+01
9,50E+01
1,00E+02
1,05E+02
1,10E+02
1,15E+02
-‐40,00 -‐20,00 0,00 20,00 40,00 60,00 80,00
Résistance fixe
TCR=1e-‐3 /°C
-0,08 %/°C
-0,157 %/°C
)(µAIout
)C.(Temp °
Transistor biasing and temperature
• NMOS et PMOS exhibits same phenomenon
T1
Ibias Iout
Vdd
T2
Vout=2V (>Veff1) T3
V1
8,00E+01
8,50E+01
9,00E+01
9,50E+01
1,00E+02
1,05E+02
1,10E+02
1,15E+02
1,20E+02
-‐40,00 -‐20,00 0,00 20,00 40,00 60,00 80,00
Polarisation par R constantePolarisation par R avec TCR=1e-‐3 /°CPolarisation par PMOS
-0,08 %/°C
-0,157 %/°C
)(µAIout
)C.(Temp °
-0,2 %/°C
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8,50E+01
9,00E+01
9,50E+01
1,00E+02
1,05E+02
1,10E+02
1,15E+02
-‐40,00 -‐20,00 0,00 20,00 40,00 60,00 80,00
Cascode avec R et TCR=1e-‐3 /°CPolarisation par R avec TCR=1e-‐3 /°CCascode pplarisé par PMOS
Cascode Source and temperature
• Feedback may improve results
-0,036 %/°C
-0,157 %/°C
)(µAIout
)C.(Temp °
0,036 %/°C
Rp Vout=2V
Iout
T1 T2
T4
T3
Vdd
Rp Vout=2V
Iout
T1 T2
T4
T3
Vdd
Ibias
Vdd
T3
Outline
• Elementary current mirror • Elementary stages for increased output
resistance • Other elementary current mirrors • Elementary current sources • Overview of advanced current sources
– Vdd-independent current sources – Vdd-independent and increased output resistance – Increasing output dynamic range
• PMOS current sources
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Vdd-independent current sources
• Principle: a resistor implement a feedback that tends to reduce current variations
• Sizing methods – Choice of Ibias and α (generally, 4, 9 or 16)
• Ibias is not sensitive to Vdd variations – Assuming identical currents in T1
and T2 leads to an expression of Ibias depending of T4, T5 et R
T1
T3
Ibias Ibias
Vdd
VA
T5 T4
T2
R
Ibias
VB
4
4
5
5
LW
LW
⋅=α
2
4
42
12!"#
$%&
+−
⋅⋅=αα
αµ W
LRC
Ioxp
bias
Vdd-independent current sources
• Other configurations – Dual circuit in PMOS (current from Vdd) – Increased stability by reduction of Vds2 and Vds5 – Power consumption à asymmetrical current mirror
4
4
5
5
LW
LW
⋅=α
T1
T7
Ibias 10.Ibias
Vdd
VA
T5 T4
T2
R
Ibias
VC
T6 T3
VB VD
T1
T2
R1
Vout
Iout T3 T4
Vdd
T8
1
1
2
2
LW
LW
⋅=α
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Vdd- independent and increased output resistance
• Vdd-independent à R, T4 and T5 to set value of Ibias
independently of Vdd • Reduced power consumption
à asymmetrical current mirror
• High-voltage operation à T3 and T6 are optional
• Increased Rout à Cascode output à Problem à output range of operation
T1
T7
Ibias 10.Ibias
Vdd
VA
T5 T4
T2
R
Ibias
VC
T6 T3
VB VD
T1c
T7c T2c
Outline
• Elementary current mirror • Elementary stages for increased output
resistance • Other elementary current mirrors • Elementary current sources • Overview of advanced current sources
– Vdd-independent current sources – Vdd-independent and increased output resistance – Increasing output dynamic range
• PMOS current sources
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Increasing output dynamic range
• Principle
T1
R
IS
T2
T3 Vs
Ibias
effd
effbiassds
tneffsbiasdsgs
tneffgsds
tngseff
VV
VIRVV
VVVIRVV
VVVV
VVV
.2
.
.
3
32
313
11
≥⇒
≥==⇒
+=−+=
+==
−=
Trade-off between output range of operation and output resistance…
Increasing output dynamic range
• Implementation: large-swing cascode current source with Vdd-independent reference current
T5
Ibias Ibias
Vdd
VA
T7 T6
R
Ibias
VB
T3 T2
T1
9
9
5
5
3
3
2
2
1
1 44LW
LW
LW
LW
LW
⋅=⋅===T9
T8
Ibias
VC
76
76
6
6
7
7
avec
)1(
effeff
biasRReffeff
VV
IRVVVVLW
LW
⋅=
⋅=+=
>⋅=
α
αα
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Increasing output dynamic range: alternative configurations
T5
Ibias Ibias
Vdd
VA
T7 T6
R
Ibias
VB
T3 T2
T4 T1
T9
T8
Ibias VC
T5
Ibias 10.Ibias
Vdd=5V
VA
T7 T6
R
Ibias
T3 T2
T4 T1
T9
T8
Ibias VC
T71 T61 VB
T81
Current sources
• Elementary current mirror • Elementary stages for increased output
resistance • Other elementary current mirrors • Elementary current sources • Overview of advanced current sources • PMOS current sources
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Current sources
• Overview of main characteristics
Impact of Vdd
Output resistance Output range of operation
Basic current source ±25% 625kΩ
> 0,8V
Vdd-independent current source
±2,3%
500kΩ
> 0,9V
Vdd-independent current source with
cascoded output
±0,02%
80MΩ
> 1V
Large-swing Vdd-independent cascoded
current source
±9% ±2,25%
3,54MΩ
4,88MΩ
> 0,3V > 0,3V
Contrôle des connaissances
• 4 Novembre : 3 heures – Analyse de Layout – Source de tension
• Dimensionnement théorique • Ajustement fin • Schéma petit-signal • Sensibilité à Vdd
– Source de courant • Dimensionnement théorique • Ajustement fin • Schéma petit-signal • Résistance de sortie