m29f200bb

7/25/2019 m29f200bb

1/22

1/22

PRELIMINARY DATA

October 1999This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M29F200BTM29F200BB

2 Mbit (256Kb x8 or 128Kb x16, Boot Block)Single Supply Flash Memory

SINGLE 5V 10% SUPPLY VOLTAGE forPROGRAM, ERASE and READ OPERATIONS

ACCESS TIME: 45ns PROGRAMMING TIME 8 s per Byte/Word typical 7 MEMORY BLOCKS

1 Boot Block (Top or Bottom Location) 2 Parameter and 4 Main Blocks

PROGRAM/ERASE CONTROLLER Embedded Byte/Word Program algorithm Embedded Multi-Block/Chip Erase algorithm Status Register Polling and Toggle Bits Ready/Busy Output Pin ERASE SUSPEND and RESUME MODES Read and Program another Block during

Erase Suspend

UNLOCK BYPASS PROGRAM COMMAND Faster Production/Batch Programming TEMPORARY BLOCK UNPROTECTIONMODE

LOW POWER CONSUMPTION

Standby and Automatic Standby 100,000 PROGRAM/ERASE CYCLES perBLOCK

20 YEARS DATA RETENTION

Defectivity below 1 ppm/year

ELECTRONIC SIGNATURE Manufacturer Code: 0020h M29F200BT Device Code: 00D3h M29F200BB Device Code: 00D4h

44

1

TSOP48 (N)12 x 20mm

SO44 (M)

Figure 1. Logic Diagram

AI02912

17

A0-A16

W

DQ0-DQ14

VCC

M29F200BTM29F200BBE

VSS

15

G

RP

DQ15A1

BYTE

RB

7/25/2019 m29f200bb

2/22

M29F200BT, M29F200BB

2/22

Figure 2A. TSOP Connections

DQ3

DQ9DQ2

A6DQ0

W

A3

RB

DQ6A8A9

DQ13

NC

A10 DQ14

A2

DQ12

DQ10

DQ15A1

VCC

DQ4

DQ5

A7

DQ7

NC

NC

AI02913

M29F200BTM29F200BB

12

1

13

24 25

3637

48

DQ8

NCNC

A1

NC

A4A5

DQ1

DQ11

G

A12A13

A16

A11

BYTE

A15

A14 VSS

EA0

RP

VSS

Figure 2B. SO Connections

GDQ0DQ8

A3

A0E

VSS

A2A1

A13

VSS

A14A15

DQ7

A12

A16BYTE

DQ15A1

DQ5DQ2

DQ3VCCDQ11DQ4

DQ14

A9

WRB

A4

NC RP

A7

AI02914

M29F200BTM29F200BB

8

234567

9101112

13141516

3231302928272625242322

20191817DQ1

DQ9

A6A5

DQ6DQ13

44

39383736353433

A11A10

DQ1021

DQ12

40

431

4241

NC A8

Table 1. Signal Names

A0-A16 Address Inputs

DQ0-DQ7 Data Inputs/Outputs

DQ8-DQ14 Data Inputs/Outputs

DQ15A1 Data Input/Output or Address Input

E Chip Enable

G Output Enable

W Write Enable

RP Reset/Block Temporary Unprotect

RB Ready/Busy Output

BYTE Byte/Word Organization Select

VCC Supply Voltage

VSS Ground

NC Not Connected Inte rnally

SUMMARY DESCRIPTIONThe M29F200B is a 2 Mbit (256Kb x8 or 128Kbx16) non-volatile memory that can be read, erasedand reprogrammed. These operations can be per-formed using a single 5V supply. On power-up thememory defaults to its Read mode where it can beread in the same way as a ROM or EPROM. TheM29F200B is fully backward compatible with theM29F200.The memory is divided into blocks that can beerased independently so it is possible to preserve

valid data while old data is erased. Each block canbe protected independently to prevent accidentalProgram or Erase commands from modifying thememory. Program and Erase commands are writ-ten to the Command Interface of the memory. Anon-chip Program/Erase Controller simplifies theprocess of programming or erasing the memory bytaking care of all of the special operations that arerequired to update the memory contents. The endof a program or erase operation can be detectedand any error conditions identified. The commandset required to control the memory is consistentwith JEDEC standards.

7/25/2019 m29f200bb

3/22

3/22


The blocks in the memory are asymmetrically ar-ranged, see Tables 3A and 3B, Block Addresses.The first or last 64 Kbytes have been divided intofour additional blocks. The 16 Kbyte Boot Blockcan be used for small initialization code to start themicroprocessor, the two 8 Kbyte ParameterBlocks can be used for parameter storage and theremaining 32K is a small MainBlock where the ap-

plication may be stored.Chip Enable, Output Enable and Write Enable sig-nals control the bus operation of the memory.They allow simple connection to most micropro-cessors, often without additional logic.The memory is offered in TSOP48 (12 x 20mm)and SO44 packages. Access times of 45ns, 55ns,70ns and 90ns are available. The memory is sup-plied with all the bits erased (set to 1).

SIGNAL DESCRIPTIONSSee Figure 1, Logic Diagram, and Table 1, SignalNames, for a brief overview of the signals connect-ed to this device.Address Inputs (A0-A16). The Address Inputsselect the cells in the memory array to access dur-ing Bus Read operations. During Bus Write opera-tions they control the commands sent to theCommand Interface of the internal state machine.Data Inputs/Outputs (DQ0-DQ7). The Data In-puts/Outputs output the data stored at the selectedaddress during a Bus Read operation. During BusWrite operations they represent the commands

sent to the Command Interface of the internal statemachine.Data Inputs/Outputs (DQ8-DQ14). The Data In-puts/Outputs output the data stored at the selectedaddress during a Bus Read operation when BYTEis High, V IH. When BYTE is Low, V IL, these pinsare not used and are high impedance. During BusWrite operations the Command Register does notuse these bits. When reading the Status Registerthese bits should be ignored.Data Input/Output or Address Input (DQ15A-1).When BYTE is High, V IH, this pin behaves as aData Input/Output pin (as DQ8-DQ14). WhenBYTE is Low, V IL, this pin behaves as an addresspin; DQ15A1 Low will select the LSB of the Wordon the other addresses, DQ15A1 High will selectthe MSB. Throughout the text consider referencesto the Data Input/Output to include this pin whenBYTE is High and references to the Address In-puts to include this pin when BYTE is Low exceptwhen stated explicitly otherwise.

Chip Enable (E). The Chip Enable, E, activatesthe memory, allowing Bus Read and Bus Write op-erations to be performed. When Chip Enable isHigh, V IH, all other pins are ignored.Output Enable (G). The Output Enable, G, con-trols the Bus Read operation of the memory.Write Enable (W). The Write Enable, W, controlsthe Bus Write operation of the memorys Com-mand Interface.

Table 2. Absolute Maximum Ratings (1)

Note: 1. Except for the rating Operating Temperature Range, stresses above those listed in the Table Absolute Maximum Ratings maycause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditionsabove those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevantqual-ity documents.

2. Minimum Voltage may undershoot to 2V during transition and for less than 20ns during transitions.

Symbol Parameter Value Unit

TA

Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 C



TBIAS Temperature Under Bias 50 to 125 C

TSTG Storage Temperature 65 to 150 C

VIO (2) Input or Output Voltage 0.6 to 6 V

VCC Supply Voltage 0.6 to 6 V

VID Identification Voltage 0.6 to 13.5 V

7/25/2019 m29f200bb

4/22


4/22

Table 3A. M29F200BT Block AddressesSize

(Kbytes)Address Range

(x8)Address Range

(x16)

16 3C000h-3FFFFh 1E000h-1FFFFh

8 3A000h-3BFFF h 1D000h-1DFF Fh

8 38000h-39FFF h 1C000h-1CFF Fh

32 30000h-37FFFh 18000h-1BFFFh

64 20000h-2FFFFh 10000h-17FFFh

64 10000h-1FFFFh 08000h-0FFFFh

64 00000h-0FFFFh 00000h-07FFFh

Reset/Block Temporary Unprotect (RP). The Re-set/Block Temporary Unprotect pin can be used toapply a Hardware Reset to the memory or to tem-

porarily unprotect all Blocks that have been pro-tected.A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, V IL, for at leasttPLPX . After Reset/Block temporary unprotect goesHigh, V IH, the memory will be ready for Bus Readand Bus Write operations after t PHEL or t RHEL ,whichever occurs last. See the Ready/Busy Out-put section, Table 14 and Figure 10, Reset/Tem-porary Unprotect AC Characteristics for moredetails.Holding RP at V ID will temporarily unprotect theprotected Blocks in the memory. Program andErase operations on all blocks will be possible.The transition from V IH to V ID must be slower thantPHPHH .Ready/Busy Output (RB). The Ready/Busy pinis an open-drain output that can be used to identifywhen the memory array can be read. Ready/Busyis high-impedance during Read mode, Auto Selectmode and Erase Suspend mode.After a Hardware Reset, Bus Read and Bus Writeoperations cannot begin until Ready/Busy be-comes high-impedance. See Table 14 and Figure10, Reset/Temporary Unprotect AC Characteris-tics.During Program or Erase operations Ready/Busyis Low, V OL. Ready/Busy will remain Low during

Table 3B. M29F200BB Block AddressesSize

(Kbytes)Address Range

(x8)Address Range

(x16)


64 20000h-2FFFFh 10000h-17FFFh


32 08000h-0FFFFh 04000h-07FFFh

8 06000h-07FFFh 03000h-03FFFh

8 04000h-05FFFh 02000h-02FFFh

16 00000h-03FFFh 00000h-01FFFh

Read/Reset commands or Hardware Resets untilthe memory is ready to enter Read mode.The use of an open-drain output allows the Ready/

Busy pins from several memories to be connectedto a single pull-up resistor. A Low will then indicatethat one, or more, of the memories is busy.Byte/Word Organization Select (BYTE). The Byte/ Word Organization Select pin is used to switch be-tween the 8-bit and 16-bit Bus modes of the mem-ory. When Byte/Word Organization Select is Low,VIL, the memory is in 8-bit mode, when it is High,VIH, the memory is in 16-bit mode.VCC Supply Voltage. The V CC Supply Voltagesupplies the power for all operations (Read, Pro-gram, Erase etc.).The Command Interface is disabled when the V CC

Supply Voltage is less than the Lockout Voltage,VLKO. This prevents Bus Write operations from ac-cidentally damaging the data during power up,power down and power surges. If the Program/ Erase Controller is programming or erasing duringthis time then the operation aborts and the memo-ry contents being altered will be invalid.A 0.1 F capacitor should be connected betweenthe V CC Supply Voltage pin and the V SS Groundpin to decouple the current surges from the powersupply. The PCB track widths must be sufficient tocarry the currents required during program anderase operations, I CC4 .Vss Ground. The V SS Ground is the referencefor all voltage measurements.

7/25/2019 m29f200bb

5/22

5/22


Table 4A. Bus Operations, BYTE = V IL

Note: X = V IL or V IH.

Table 4B. Bus Operations, BYTE = V IH

Note: X = V IL or V IH.

Operation E G W Address InputsDQ15A1, A0-A16Data Inputs/Outputs

DQ14- DQ8 DQ7-DQ0

Bus Read V IL VIL VIH Cell Address Hi-Z Data Output

Bus Write VIL VIH VIL Command Address Hi-Z Data Input

Output Disable X VIH VIH X Hi-Z Hi-Z

Standby VIH X X X Hi-Z Hi-Z

Read ManufacturerCode

VIL VIL VIHA0 = V IL, A1 = V IL, A9 = V ID,Others V IL or V IH

Hi-Z 20h

Read Device Code VIL VIL VIHA0 = V IH, A1 = V IL, A9 = V ID,Others V IL or V IH

Hi-Z D3h (M29F200BT)D4h (M29F200BB)

Operation E G W Address InputsA0-A16Data Inputs/OutputsDQ15A1, DQ14-DQ0

Bus Read VIL VIL VIH Cell Address Data Output

Bus Write VIL VIH VIL Command Address Data Input

Output Disable X VIH VIH X Hi-Z

Standby VIH X X X Hi-Z

Read ManufacturerCode VIL VIL VIH

A0 = V IL, A1 = V IL, A9 = V ID,Others V IL or V IH

0020h

Read Device Code VIL VIL VIH A0 = V IH, A1 = V IL, A9 = V ID,Others V IL or V IH00D3h (M29F200BT)00D4h (M29F200BB)

BUS OPERATIONSThere are five standard bus operations that controlthe device. These are Bus Read, Bus Write, Out-put Disable, Standby and Automatic Standby. SeeTables 4A and 4B, Bus Operations, for a summa-ry. Typically glitches of less than 5ns on Chip En-able or Write Enable are ignored by the memoryand do not affect bus operations.

Bus Read. Bus Read operations read from thememory cells, or specific registers in the Com-mand Interface. A valid Bus Read operation in-volves setting the desired address on the AddressInputs, applying a Low signal, V IL, to Chip Enableand Output Enable and keeping Write EnableHigh, V IH. The Data Inputs/Outputs will output thevalue, see Figure 7, Read Mode AC Waveforms,and Table 11, Read AC Characteristics, for detailsof when the output becomes valid.

Bus Write. Bus Write operations write to theCommand Interface. A valid Bus Write operationbegins by setting the desired address on the Ad-dress Inputs. The Address Inputs are latched bythe Command Interface on the falling edge of ChipEnable or Write Enable, whichever occurs last.The Data Inputs/Outputs are latched by the Com-mand Interface on the rising edge of Chip Enableor Write Enable, whichever occurs first. OutputEn-able must remain High, V IH, during the whole BusWrite operation. See Figures 8 and 9, Write ACWaveforms, and Tables 12 and 13, Write ACCharacteristics, for details of the timing require-ments.Output Disable. The Data Inputs/Outputs are inthe high impedance state when Output Enable isHigh, V IH.

7/25/2019 m29f200bb

6/22


6/22

Standby. When Chip Enable is High, V IH, theData Inputs/Outputs pins are placed in the high-impedance state and the Supply Current is re-duced to the Standby level.

When Chip Enable is at V IH the Supply Current isreduced to the TTL Standby Supply Current, I CC2 .To further reduce the Supply Current to the CMOSStandby Supply Current, I CC3 , ChipEnable shouldbe held within V CC 0.2V. For Standby currentlevels see Table 10, DC Characteristics.During program or erase operations the memorywill continue to use the Program/Erase SupplyCurrent, I CC4 , for Program or Erase operationsun-til the operation completes.Automatic Standby. If CMOS levels (V CC 0.2V)are usedto drive the bus and the bus is inactive for150ns or more the memory enters AutomaticStandby where the internal Supply Current is re-duced to the CMOS Standby Supply Current, I CC3 .The Data Inputs/Outputs will still output data if aBus Read operation is in progress.Special Bus OperationsAdditional bus operations can be performed toread the Electronic Signature and also to applyand remove Block Protection. These bus opera-tions are intended for use by programming equip-ment and are not usually used in applications.They require V ID to be applied to some pins.Electronic Signature. The memory has twocodes, the manufacturer code and the devicecode, that can be read to identify the memory.These codes can be read by applying the signalslisted in Tables 4A and 4B, Bus Operations.Block Protection and Blocks Unprotection. Eachblock can be separately protected against acci-dental Program or Erase. Protected blocks can beunprotected to allow data to be changed.There are two methods available for protectingand unprotecting the blocks, one for use on pro-gramming equipment and the other for in-systemuse. For further information refer to ApplicationNote AN1122, Applying Protection and Unprotec-tion to M29 Series Flash.

COMMAND INTERFACEAll Bus Write operations to the memory are inter-preted by the Command Interface. Commandsconsist of one or more sequential Bus Write oper-

ations. Failure to observe a valid sequence of BusWrite operations will result in the memory return-ing to Read mode. The long command sequencesare imposed to maximize data security.The address used for the commands changes de-pending on whether the memory is in 16-bit or 8-bit mode. See either Table 5A, or 5B, dependingon the configuration that is being used, for a sum-mary of the commands.Read/Reset Command. The Read/Reset com-mand returns the memory to its Read mode whereit behaves like a ROM or EPROM. It also resetsthe errors in the Status Register. Either one orthree Bus Write operations can be used to issuethe Read/Reset command.If the Read/Reset command is issued during aBlock Erase operation or following a Programmingor Erase error then the memory will take upto 10 sto abort. During the abort period no valid data canbe read f rom the memory. Issuing a Read/Resetcommand during a Block Erase operation willleave invalid data in the memory.Auto Select Command. The Auto Select com-mand is used to read the Manufacturer Code, theDevice Code and the Block Protection Status.Three consecutive Bus Write operations are re-quired to issue the Auto Select command. Oncethe Auto Select command is issued the memoryremains in Auto Select mode until another com-mand is issued.From the Auto Select mode the ManufacturerCode can be read using a Bus Read operationwith A0 = V IL and A1 = V IL. The other address bitsmay be set to either V IL or V IH. The ManufacturerCode for STMicroelectronics is 0020h.The Device Code can be read using a Bus Readoperation with A0 = V IH and A1 = V IL. The otheraddress bits may be set to either V IL or V IH. TheDevice Code for the M29F200BT is 00D3h and forthe M29F200BB is 00D4h.

7/25/2019 m29f200bb

7/22

7/22


Table 5A. Commands, 16-bit mode, BYTE = V IH

Table 5B. Commands, 8-bit mode, BYTE = V IL

Note: X Dont Care, PA Program Address, PD Program Data, BA Any address in the Block.All values in the table are in hexadecimal.The Command I nterface only uses A1, A 0-A10 and DQ0-DQ7 to verify the commands; A11-A16, DQ8-DQ14 and DQ15 are Dont Care.DQ15A1 is A1 when BYTE is V IL or DQ15 when BYTE is V IH.Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the P rogram/EraseController completes and the memory returns to Read Mode. Add additional B locks during B lock Erase Command with additional Bus WriteOperations until the Timeout Bit is set.Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued.Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commandson non-erasing blocks as normal.Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/ Erase Controller completes and the memory returns to Read Mode.

Command L e n g t h

Bus Write Operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset1 X F0

3 555 AA 2AA 55 X F0

Auto Select 3 555 AA 2AA 55 555 90

Program 4 555 AA 2AA 55 555 A0 PA PD

Unlock Bypass 3 555 AA 2AA 55 555 20

Unlock BypassProgram 2 X A0 PA PD

Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30

Erase Suspend 1 X B0

Erase Resume 1 X 30

Command L e n g t h

Bus Write Operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset1 X F0

3 AAA AA 555 55 X F0

Auto Select 3 AAA AA 555 55 AAA 90

Program 4 AAA AA 555 55 AAA A0 PA PD

Unlock Bypass 3 AAA AA 555 55 AAA 20

Unlock BypassProgram 2 X A0 PA PD

Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10

Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30

Erase Suspend 1 X B0

Erase Resume 1 X 30

7/25/2019 m29f200bb

8/22


8/22

The Block Protection Status of each block can beread using a Bus Read operation with A0 = V IL,A1 = V IH, and A12-A16 specifying the address ofthe block. The other address bits may be set toei-ther V IL or V IH. If the addressed block is protect-ed then 01h is output on Data Inputs/OutputsDQ0-DQ7, otherwise 00h is output.Program Command. The Program commandcan be used to program a value to one address inthe memory array at a time. The command re-quires fourBus Write operations, the final write op-eration latches the address and data in the internal

state machine and starts the Program/Erase Con-troller.If the address falls in a protected block then theProgram command is ignored, the data remainsunchanged. The Status Register is never read andno error condition is given.During the program operation the memory will ig-nore all commands. It is not possible to issue anycommand to abort or pause the operation. Typicalprogram times are given inTable 6. Bus Read op-erations during the program operation will outputthe Status Register on the Data Inputs/Outputs.See the section on the Status Register for moredetails.After the program operation has completed thememory will return to the Read mode, unless anerror has occurred. When an error occurs thememory will continue to output the Status Regis-ter. A Read/Reset command must be issued to re-set the error condition and return to Read mode.

Note that the Program command cannot change abit set at 0 back to 1 and attempting to do so willcause an error. One of the Erase Commands mustbe used to set all the bits in a blockor in the wholememory from 0 to 1.Unlock Bypass Command. The Unlock Bypasscommand is used in conjunction with the UnlockBypass Program command to program the memo-ry. When the access time to the device is long (aswith some EPROM programmers) considerabletime saving can be made by using these com-mands. Three Bus Write operations are required

to issue the Unlock Bypass command.Once the Unlock Bypass command has been is-sued the memory will only accept the Unlock By-pass Program command and the Unlock BypassReset command. The memory can be read as if inRead mode.Unlock Bypass Program Command. The Un-lock Bypass Program command can be used toprogram one address in memory at a time. Thecommand requires two Bus Write operations, thefinal write operation latches the address and datain the internal state machine and starts the Pro-gram/Erase Controller.The Program operation using the Unlock BypassProgram command behaves identically to the Pro-gram operation using the Program command. Aprotected block cannot be programmed; the oper-ation cannot be aborted and the Status Register isread. Errors must be reset using the Read/Resetcommand, which leaves the device in Unlock By-pass Mode. See the Program command for detailson the behavior.

Table 6. Program, Erase Times and Program, Erase Endurance Cycles(TA = 0 to 70 C, 40 to 85 C or 40 to 125 C)

Note: 1. T A = 25 C, V CC = 5V.

Parameter Min Typ (1) Typical after100k W/E Cycles (1)

Max Unit

Chip Erase (All bits in the memory set to 0) 0.8 0.8 sec

Chip Erase 2.5 2.5 10 sec

Block Erase (64 Kbytes) 0.6 0.6 4 sec

Program (Byte or Word) 8 8 150 s

Chip Program (Byte by Byte) 2.3 2.3 9 sec

Chip Program (Word by Word) 1.2 1.2 4.5 sec

Program/Erase Cycles (per Block) 100,000 cycles

7/25/2019 m29f200bb

9/22

9/22


Unlock Bypass Reset Command. The UnlockBypass Reset command can be used to return toRead/Reset mode f rom Unlock Bypass Mode.Two Bus Write operations are required to issue the

Unlock Bypass Reset command.Chip Erase Command. The Chip Erase com-mand can be used to erase the entire chip. Six BusWrite operations are required to issue the ChipErase Command and start the Program/EraseController.If any blocks are protected then these are ignoredand all the other blocks are erased. If all of theblocks are protected the Chip Erase operation ap-pears to start but will terminate within about 100 s,leaving the data unchanged. No error condition isgiven when protected blocks are ignored.During the erase operation the memory will ignoreall commands. It is not possible to issue any com-mand to abort the operation. Typical chip erasetimes are given in Table 6. All Bus Read opera-tions during the Chip Erase operation will outputthe Status Register on the Data Inputs/Outputs.See the section on the Status Register for moredetails.After the Chip Erase operation has completed thememory will return to the Read Mode, unless anerror has occurred. When an error occurs thememory will continue to output the Status Regis-ter. A Read/Reset command must be issued to re-set the error condition and return to Read Mode.The Chip Erase Command sets all of the bits in un-protected blocks of the memory to 1. All previousdata is lost.Block Erase Command. The Block Erase com-mand can be used to erase a list of one or moreblocks. Six Bus Write operations are required toselect the first block in the list. Each additionalblock in the list can be selected by repeating thesixth Bus Write operation using the address of theadditional block. The Block Erase operation startsthe Program/Erase Controller about 50 s after thelast Bus Write operation. Once the Program/EraseController starts it is not possible to select anymore blocks. Each additional block must thereforebe selected within 50 s of the last block. The 50 stimer restarts when an additional block is selected.The Status Register can be read after the sixthBus Write operation. See the Status Register fordetails on how to identify if the Program/EraseController has started the Block Erase operation.If any selected blocks are protected then these areignored and all the other selected blocks are

erased. If all of the selected blocks are protectedthe Block Erase operation appears to start but willterminate within about 100 s, leaving the data un-changed. No error condition is given when protect-

ed blocks are ignored.During the Block Erase operation the memory willignore all commands except the Erase Suspendand Read/Reset commands. Typical block erasetimes are given in Table 6. All Bus Read opera-tions during the Block Erase operation will outputthe Status Register on the Data Inputs/Outputs.See the section on the Status Register for moredetails.After the Block Erase operation has completed thememory will return to the Read Mode, unless anerror has occurred. When an error occurs thememory will continue to output the Status Regis-ter. A Read/Reset command must be issued to re-set the error condition and return to Read mode.The Block Erase Command sets all of the bits inthe unprotected selected blocks to 1. All previousdata in the selected blocks is lost.Erase Suspend Command. The Erase SuspendCommand may be used to temporarily suspend aBlock Erase operation and return the memory toRead mode. The command requires one BusWrite operation.The Program/Erase Controller will suspend within15 s of the Erase Suspend Command being is-sued. Once the Program/Erase Controller hasstopped the memory will be set to Read mode andthe Erase will be suspended. If the Erase Suspendcommand is issued during the period when thememory is waiting for an additional block (beforethe Program/Erase Controller starts) then theErase is suspended immediately and will start im-mediately when the Erase Resume Command isissued. It will not be possible to select any furtherblocks for erasure after the Erase Resume.During Erase Suspend it is possible to Read andProgram cells in blocks that are not being erased;both Read and Program operations behave asnormal on these blocks. Reading from blocks thatare being erased will output the Status Register. Itis also possible to enter the Auto Select mode: thememory will behave as in the Auto Select mode onall blocks until a Read/Reset command returns thememory to Erase Suspend mode.Erase Resume Command. The Erase Resumecommand must be used to restart the Program/ Erase Controller from Erase Suspend. An erasecan be suspended and resumed more than once.

7/25/2019 m29f200bb

10/22


10/22

STATUS REGISTERBus Read operations from any address alwaysread the Status Register during Program andErase operations. It is also read during Erase Sus-pend when an address within a block being erasedis accessed.

The bits in the Status Register are summarized inTable 7, Status Register Bits.Data Polling Bit (DQ7). The Data Polling Bit canbe used to identify whether the Program/EraseController has successfully completed its opera-tion or if it has responded to an Erase Suspend.The Data Polling Bit is output on DQ7 when theStatus Register is read.During Program operations the Data Polling Bitoutputs the complement of the bit being pro-grammed to DQ7. After successful completion ofthe Program operation the memory returns toRead mode and Bus Read operations from the ad-dress just programmed output DQ7, not its com-plement.During Erase operations the Data Polling Bit out-puts 0, the complement of the erased state ofDQ7. After successful completion of the Erase op-eration the memory returns to Read Mode.In Erase Suspend mode the Data Polling Bit willoutput a 1 during a Bus Read operation within ablock being erased. The Data Polling Bit willchange from a 0 to a 1 when the Program/EraseController has suspended the Erase operation.Figure 3, Data Polling Flowchart, gives an exam-ple of how to use the Data Polling Bit. A Valid Ad-

dress is the address being programmed or anaddress within the block being erased.Toggle Bit (DQ6). The Toggle Bit can be used toidentify whether the Program/Erase Controller hassuccessfully completed its operation or if it has re-sponded to an Erase Suspend. The Toggle Bit is

output on DQ6 when the Status Register is read.During Program and Erase operations the ToggleBit changes from 0 to 1 to 0, etc., with succes-sive Bus Read operations at any address. Aftersuccessful completion of the operation the memo-ry returns to Read mode.During Erase Suspend mode the Toggle Bit willoutput when addressing a cell within a block beingerased. The Toggle Bit will stop toggling when theProgram/Erase Controller has suspended theErase operation.Figure 4, Data Toggle Flowchart, gives an exam-ple of how to use the Data Toggle Bit.

Error Bit (DQ5). The Error Bit can be used toidentify errors detected by the Program/EraseController. The Error Bit is set to 1 when a Pro-gram, Block Erase or Chip Erase operation fails towrite the correct data to the memory. If the ErrorBit is set a Read/Reset command must be issuedbefore other commands are issued. The Error bitis output onDQ5 when the Status Register is read.Note that the Program command cannot change abit set at 0 back to 1 and attempting to do so willcause an error. One of the Erase commands mustbe used to set all the bits in a blockor in the wholememory from 0 to 1.

Table 7. Status Register Bits

Note: Unspecified data bits should be ignored.

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB

Program Any Address DQ7 Toggle 0 0

Program During EraseSuspend Any Address DQ7 Toggle 0 0

Program Error Any Address DQ7 Toggle 1 0

Chip Erase Any Address 0 Toggle 0 1 Toggle 0

Block Erase beforetimeout

Erasing Block 0 Toggle 0 0 Toggle 0

Non-Erasing Block 0 Toggle 0 0 No Toggle 0

Block EraseErasing Block 0 Toggle 0 1 Toggle 0

Non-Erasing Block 0 Toggle 0 1 No Toggle 0

Erase SuspendErasing Block 1 No Toggle 0 1 Toggle 1

Non-Erasing Block Data read as normal 1

Erase ErrorGood Block Address 0 Toggle 1 1 No Toggle 0

Faulty Block Address 0 Toggle 1 1 Toggle 0

7/25/2019 m29f200bb

11/22

11/22


Figure 3. Data Polling Flowchart

READ DQ5 & DQ7at VALID ADDRESS

START

READ DQ7

FAIL PASS

AI01369

DQ7=

DATAYES

NO

YES

NO

DQ5= 1

DQ7=

DATAYES

NO

Figure 4. Data Toggle Flowchart

READDQ5 & DQ6

START

READ DQ6

FAIL PASS

AI01370

DQ6=

TOGGLENO

NO

YES

YES

DQ5= 1

NO

YES

DQ6=

TOGGLE

Erase Timer Bit (DQ3). The Erase Timer Bit canbe used to identify the start of Program/EraseController operation during a Block Erase com-mand. Once the Program/Erase Controller startserasing the Erase Timer Bit is set to 1. Before theProgram/Erase Controller starts the Erase TimerBit is set to 0 and additional blocks to be erasedmay be written to the Command Interface. TheErase Timer Bit is output on DQ3 when the StatusRegister is read.Alternative Toggle Bit (DQ2). The Alternative

Toggle Bit can be used to monitor the Program/ Erase controller during Erase operations. The Al-ternative Toggle Bit is output on DQ2 when theStatus Register is read.During Chip Erase and Block Erase operations theToggle Bit changes from 0 to 1 to 0, etc., withsuccessive Bus Read operations from addresses

within the blocks being erased. Once the operationcompletes the memory returns to Read mode.During Erase Suspend the Alternative Toggle Bitchanges from 0 to 1 to 0, etc. with successiveBus Read operations from addresses within theblocks being erased. Bus Read operations to ad-dresses within blocks not being erased will outputthe memory cell data as if in Read mode.After an Erase operation that causes the Error Bitto be set the Alternative Toggle Bit can be used toidentify which block or blocks have caused the er-

ror. The Alternative Toggle Bit changes from 0 to1 to 0, etc. with successive Bus Read Opera-tions from addresses within blocks that have noterased correctly. The Alternative Toggle Bit doesnot change if the addressed block has erased cor-rectly.

7/25/2019 m29f200bb

12/22


12/22

Figure 5. AC Testing Input Output Waveform

AI01275B

3V

High Speed

0V

1.5V

2.4V

Standard

0.45V

2.0V

0.8V

Figure 6. AC Testing Load Circuit

AI03027

1.3V

OUT

CL = 30pF or 100pF

CL includes JIG capacitance

3.3k

1N914

DEVICEUNDER

TEST

Table 9. Capacitance(TA = 25 C, f = 1 MHz)

Note: Sampled only, not 100% tested.

Symbol Parameter Test Condition Min Max Unit

C IN Input Capacitance V IN = 0V 6 pF

COUT Output Capacitance VOUT = 0V 12 pF

Table 8. AC Measurement Conditions

ParameterM29F200B

45 / 55 70 / 90

AC Test Conditions High Speed Standard

Load Capacitance (C L) 30pF 100pF

Input Rise and Fall Times 10ns 10ns

Input Pulse Voltages 0 to 3V 0.45 to 2.4V

Input and Output Timing Ref. Voltages 1.5V 0.8V and 2.0V

7/25/2019 m29f200bb

13/22

13/22


Table 10. DC Characteristics(TA = 0 to 70 C, 40 to 85 C or 40 to 125 C)

Note: 1. Sampled only, not 100% tested.

2. T A = 25 C, V CC = 5V.

Symbol Parameter Test Condition Min Typ (2) Max Unit

ILI Input Leakage Current 0V VIN VCC 1 AILO Output Leakage Current 0V VOUT VCC 1 A

ICC1 Supply Current (Read) E = V IL, G = V IH,

f = 6MHz 6 20 mA

ICC2 Supply Current (Standby) TTL E = V IH 1 mA

ICC3 Supply Current (Standby) CMOS E = V CC 0.2V,

RP = V CC 0.2V 30 100 A

ICC4 (1) Supply Current (Program/Erase) Program/Erase

Controller active 20 mA

VIL Input Low Voltage 0.5 0.8 V

VIH Input High Voltage 2 VCC + 0.5 V

VOL Output Low Voltage IOL = 5.8mA 0.45 V

VOHOutput High Voltage TTL IOH = 2.5mA 2.4 V

Output High Voltage CMOS I OH = 100 A VCC 0.4 V

VID Identification Voltage 11.5 12.5 V

IID Identification Current A9 = V ID 100 A

VLKO (1) Program/Erase Lockout Supply

Voltage 3.2 4.2 V

7/25/2019 m29f200bb

14/22


14/22

Figure 7. Read Mode AC Waveforms

AI02915

tAVAV

tAVQV tAXQX

tELQX tEHQZ

tGLQV

tGLQX tGHQX

VALID

A0-A16/

A1

G

DQ0-DQ7/

DQ8-DQ15

E

tELQV tEHQX

tGHQZ

VALID

tBHQV

tELBL/tELBH tBLQZ

BYTE

Table 11. Read AC Characteristics(TA = 0 to 70 C, 40 to 85 C or 40 to 125 C)


Symbol Alt Parameter Test ConditionM29F200B

Unit

45 55 70 / 90

tAVAV tRC Address Valid to Next Address Valid E = V IL,

G = V ILMin 45 55 70 ns

tAVQV tACC Address Valid to Output Valid E = V IL,

G = V ILMax 45 55 70 ns

tELQX (1) tLZChip Enable Low to OutputTransition

G = V IL Min 0 0 0 ns

tELQV tCE Chip Enable Low to Output Valid G = V IL Max 45 55 70 ns

tGLQX (1) tOLZOutput Enable Low to OutputTransition

E = V IL Min 0 0 0 ns

tGLQV tOE Output Enable Low to Output Valid E = V IL Max 25 30 30 nstEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = V IL Max 15 18 20 ns

tGHQZ (1) tDF Output Enable High to Output Hi-Z E = V IL Max 15 18 20 ns

tEHQXtGHQXtAXQX

tOHChip Enable, Output Enable orAddress Transition to OutputTransition

Min 0 0 0 ns

tELBLtELBH

tELFLtELFH

Chip Enable to BYTE Low or High Max 5 5 5 ns

tBLQZ tFLQZ BYTE Low to Output Hi-Z Max 15 15 20 ns

tBHQV tFHQV BYTE High to Output Valid Max 30 30 30 ns

7/25/2019 m29f200bb

15/22

15/22


Figure 8. Write AC Waveforms, Write Enable Controlled

AI01991

E

G

W

A0-A16/

A1

DQ0-DQ7/

DQ8-DQ15

VALID

VALID

VCC

tVCHEL

tWHEH

tWHWL

tELWL

tAVWL

tWHGL

tWLAX

tWHDX

tAVAV

tDVWH

tWLWHtGHWL

RB

tWHRL

Table 12. Write AC Characteristics, Write Enable Controlled(TA = 0 to 70 C, 40 to 85 C or 40 to 125 C)


Symbol Alt ParameterM29F200B

Unit

45 55 70 / 90tAVAV tWC Address Valid to Next Address Valid Min 45 55 70 ns

tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 0 ns

tWLWH tWP Write Enable Low to Write Enable High Min 40 40 45 ns

tDVWH tDS Input Valid to Write Enable High Min 25 25 30 ns

tWHDX tDH Write Enable High to Input Transition Min 0 0 0 ns

tWHEH tCH Write Enable High to Chip Enable High Min 0 0 0 ns

tWHWL tWPH Write Enable High to Write Enable Low Min 20 20 20 ns

tAVWL tAS Address Valid to Write Enable Low Min 0 0 0 ns

tWLAX tAH Write Enable Low to Address Transition Min 40 40 45 ns

tGHWL Output Enable High to Write Enable Low Min 0 0 0 ns

tWHGL tOEH Write Enable High to Output Enable Low Min 0 0 0 ns

tWHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 30 30 ns

tVCHEL tVCS VCC High to Chip Enable Low Min 50 50 50 s

7/25/2019 m29f200bb

16/22


16/22

Table 13. Write AC Characteristics, Chip Enable Controlled(TA = 0 to 70 C, 40 to 85 C or 40 to 125 C)



Unit

45 55 70 / 90tAVAV tWC Address Valid to Next Address Valid Min 45 55 70 ns

tWLEL tWS Write Enable Low to Chip Enable Low Min 0 0 0 ns

tELEH tCP Chip Enable Low to Chip Enable High Min 40 40 45 ns

tDVEH tDS Input Valid to Chip Enable High Min 25 25 30 ns

tEHDX tDH Chip Enable High to Input Transition Min 0 0 0 ns

tEHWH tWH Chip Enable High to Write Enable High Min 0 0 0 ns

tEHEL tCPH Chip Enable High to Chip Enable Low Min 20 20 20 ns

tAVEL tAS Address Valid to Chip Enable Low Min 0 0 0 ns

tELAX tAH Chip Enable Low to Address Transition Min 40 40 45 ns

tGHEL Output Enable High Chip Enable Low Min 0 0 0 ns

tEHGL tOEH Chip Enable High to Output Enable Low Min 0 0 0 ns

tEHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 30 30 ns

tVCHWL tVCS VCC High to Write Enable Low Min 50 50 50 s

Figure 9. Write AC Waveforms, Chip Enable Controlled

AI01992

E

G

W

A0-A16/

A1

DQ0-DQ7/

DQ8-DQ15

VALID

VALID

VCC

tVCHWL

tEHWH

tEHEL

tWLEL

tAVEL

tEHGL

tELAX

tEHDX

tAVAV

tDVEH

tELEHtGHEL

RB

tEHRL

7/25/2019 m29f200bb

17/22

17/22


Table 14. Reset/Block Temporary Unprotect AC Characteristics(TA = 0 to 70 C, 40 to 85 C or 40 to 125 C)



Unit

45 55 70 / 90tPHWL (1)

tPHELtPHGL (1)

tRHRP High to Write Enable Low, Chip EnableLow, Output Enable Low Min 50 50 50 ns

tRHWL (1)

tRHEL (1)

tRHGL (1)tRB

RB High to Write Enable Low, Chip EnableLow, Output Enable Low Min 0 0 0 ns

tPLPX tRP RP Pulse Width Min 500 500 500 ns

tPLYH (1) tREADY RP Low to Read Mode Max 10 10 10 s

tPHPHH

(1) tVIDR RP Rise Time to V ID Min 500 500 500 ns

Figure 10. Reset/Block Temporary Unprotect AC Waveforms

AI02931

RB

W,

RPtPLPX

tPHWL, tPHEL, tPHGL

tPLYH

tPHPHH

E, G

tRHWL, tRHEL, tRHGL

7/25/2019 m29f200bb

18/22


18/22

Table 15. Ordering Information Scheme

Note: The last two characters of the ordering code may be replaced by a letter code for preprogrammedparts, otherwise devices are shipped from the factory with the memory content erased (to FFFFh).

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-vice, please contact the ST Sales Office nearest to you.

Example: M29F200BB 55 N 1 T

Device Type

M29

Operating Voltage

F = V CC = 5V 10%

Device Function

200B = 2 Mbit (256Kb x8 or 128Kb x16), Boot Block

Array MatrixT = Top Boot

B = Bottom Boot

Speed

45 = 45 ns

55 = 55 ns

70 = 70 ns

90 = 90 ns

PackageN = TSOP48: 12 x 20 mm

M = SO44

Temperature Range

1 = 0 to 70 C

3 = 40 to 125 C

6 = 40 to 85 C

Option

T = Tape & Reel Packing

7/25/2019 m29f200bb

19/22

19/22


Table 16. Revision HistoryDate Revision Details

July 1999 First Is sue

10/08/99

Chip Erase Max. specification added (Table 6)Block Erase Max. specification added (Table 6)Program Max. specification added (Table 6)Chip Program Max. specification added (Table 6)ICC1 Typ. specification added (Table 10)ICC3 Typ. specification added (Table 10)ICC3 Test Condition changed (Table 10)

7/25/2019 m29f200bb

20/22


20/22

Table 17. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data

Symbolmm inches

Typ Min Max Typ Min Max

A 1.20 0.047A1 0.05 0.15 0.002 0.006

A2 0.95 1.05 0.037 0.041

B 0.17 0.27 0.007 0.011

C 0.10 0.21 0.004 0.008

D 19.80 20.20 0.780 0.795

D1 18.30 18.50 0.720 0.728

E 11.90 12.10 0.469 0.476

e 0.50 0.020

L 0.50 0.70 0.020 0.028

0 5 0 5

N 48 48

CP 0.10 0.004

Figure 11. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

Drawing is not to scale.

TSOP-a

D1

E

1 N

CP

B

e

A2

A

N/2

D

DIE

C

LA1

7/25/2019 m29f200bb

21/22

21/22


Figure 12. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline

Drawing is not to scale.

SO-b

E

N

CPB

e

A2

D

C

LA1

H

A

1

Table 18. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data

Symbolmm inches

Typ Min Max Typ Min Max

A 2.42 2.62 0.095 0.103

A1 0.22 0.23 0.009 0.010

A2 2.25 2.35 0.089 0.093

B 0.50 0.020

C 0.10 0.25 0.004 0.010

D 28.10 28.30 1.106 1.114

E 13.20 13.40 0.520 0.528

e 1.27 0.050

H 15.90 16.10 0.626 0.634

L 0.80 0.031

3 3

N 44 44

CP 0.10 0.004

7/25/2019 m29f200bb

22/22


22/22

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is grantedby implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subjectto change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are notauthorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics 1999 STMicroelectronics - All Rights Reserved

All other names are the property of their respective owners.

STMicroelectronics GROUP OF COMPANIESAustralia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -

Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A .http://www.st.com

Date post:	26-Feb-2018
Category:	Documents
Upload:	thong-chan
View:	215 times
Download:	0 times

m29f200bb

Documents