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M5235EVBUM/D5/2004REV 1
M523xEVB User’s Manual
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HOW TO REACH US:USA/EUROPE/LOCATIONS NOT LISTED:
Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130JAPAN:
Motorola Japan Ltd.; SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573, Japan81-3-3440-3569ASIA/PACIFIC:
Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre, 2 Dai King Street Tai Po Industrial Estate, Tai Po, N.T., Hong Kong852-26668334TECHNICAL INFORMATION CENTER:
1-800-521-6274HOME PAGE: http://motorola.com/semiconductors/
Information in this document is provided solely to enable system andsoftware implementers to use Motorola products. There are no expressor implied copyright licenses granted hereunder to design or fabricateany integrated circuits or integrated circuits based on the informationin this document.
Motorola reserves the right to make changes without further notice toany products herein. Motorola makes no warranty, representation, orguarantee regarding the suitability of its products for any particularpurpose, nor does Motorola assume any liability arising out of theapplication or use of any product or circuit, and specifically disclaimsany and all liability, including without limitation consequential orincidental damages. “Typical” parameters which may be provided inMotorola data sheets and/or specifications can and do vary in differentapplications and actual performance may vary over time. All operatingparameters, including “Typicals,” must be validated for each customerapplication by customer’s technical experts. Motorola does not conveyany license under its patent rights nor the rights of others. Motorolaproducts are not designed, intended, or authorized for use ascomponents in systems intended for surgical implant into the body, orother applications intended to support or sustain life, or for any otherapplication in which the failure of the Motorola product could create asituation where personal injury or death may occur. Should Buyerpurchase or use Motorola products for any such unintended orunauthorized application, Buyer shall indemnify and hold Motorola andits officers, employees, subsidiaries, affiliates, and distributorsharmless against all claims, costs, damages, and expenses, andreasonable attorney fees arising out of, directly or indirectly, any claim
Motorola and the Stylized M Logo are registered in the U.S. Patent andTrademark Office. All other product or service names are the property oftheir respective owners. Motorola, Inc. is an Equal Opportunity/AffirmativeAction Employer.
© Motorola, Inc. 2004
M5235EVBUM/D 5/2004 REV 1
of personal injury or death associated with such unintended orunauthorized use, even if such claim alleges that Motorola wasnegligent regarding the design or manufacture of the part.
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MOTOROLA M523xEVB User’s Manual iiiPRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
EMC Information on M523xEVB
1. This product as shipped from the factory with associated power supplies and cables, has been tested and meets with requirements of EN5022 and EN 50082-1: 1998 as a CLASS A product.
2. This product is designed and intended for use as a development platform for hardware or software in an educational or professional laboratory.
3. In a domestic environment this product may cause radio interference in which case the user may be required to take adequate measures.
4. Anti-static precautions must be adhered to when using this product.
5. Attaching additional cables or wiring to this product or modifying the products operation from the factory default as shipped may effect its performance and also cause interference with other apparatus in the immediate vicinity. If such interference is detected, suitable mitigating measures should be taken.
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WARNINGThis board generates, uses, and can radiate radio frequency energy and, ifnot installed properly, may cause interference to radio communications.As temporarily permitted by regulation, it has not been tested forcompliance with the limits for class a computing devices pursuant toSubpart J of Part 15 of FCC rules, which are designed to providereasonable protection against such interference. Operation of this productin a residential area is likely to cause interference, in which case the user,at his/her own expense, will be required to correct the interference.
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CONTENTSParagraphNumber Title Page
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Chapter 1 M523xEVB
1.1 MCF5235 Microprocessor .................................................................................. 1-31.2 System Memory .................................................................................................. 1-61.2.1 External Flash ................................................................................................. 1-61.2.2 SDRAM .......................................................................................................... 1-71.2.3 ASRAM .......................................................................................................... 1-71.2.4 Internal SRAM................................................................................................ 1-71.2.5 M523xEVB Memory Map.............................................................................. 1-71.2.5.1 Reset Vector Mapping ................................................................................ 1-81.3 Support Logic ..................................................................................................... 1-91.3.1 Reset Logic ..................................................................................................... 1-91.3.2 Clock Circuitry ............................................................................................. 1-111.3.3 Watchdog Timer ........................................................................................... 1-111.3.4 Exception Sources......................................................................................... 1-111.3.5 TA Generation .............................................................................................. 1-121.3.6 User’s Program ............................................................................................. 1-131.4 Communication Ports ....................................................................................... 1-131.4.1 UART0 and UART1 Ports............................................................................ 1-131.4.2 UART2/FlexCAN1 Port ............................................................................... 1-141.4.3 FlexCAN0 Port ............................................................................................. 1-141.4.4 10/100T Ethernet Port................................................................................... 1-151.4.5 eTPU ............................................................................................................. 1-171.4.6 BDM/JTAG Port........................................................................................... 1-181.4.7 I2C ................................................................................................................ 1-191.4.8 QSPI.............................................................................................................. 1-201.4.9 USB Host and Device ................................................................................... 1-201.5 Connectors and User Components.................................................................... 1-211.5.1 Daughter Card Expansion Connectors.......................................................... 1-211.5.2 Reset Switch (SW6)...................................................................................... 1-251.5.3 User LEDs..................................................................................................... 1-261.5.4 Other LEDs................................................................................................... 1-26
Chapter 2 Initialization and Setup
2.1 System Configuration ......................................................................................... 2-12.2 Installation and Setup.......................................................................................... 2-32.2.1 Unpacking....................................................................................................... 2-32.2.2 Preparing the Board for Use ........................................................................... 2-32.2.3 Providing Power to the Board......................................................................... 2-3
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2.2.4 Power Switch (SW4) ...................................................................................... 2-42.2.5 Power Status LEDs and Fuse.......................................................................... 2-42.2.6 Selecting Terminal Baud Rate ........................................................................ 2-52.2.7 The Terminal Character Format ..................................................................... 2-52.2.8 Connecting the Terminal ................................................................................ 2-52.2.9 Using a Personal Computer as a Terminal...................................................... 2-52.3 System Power-up and Initial Operation.............................................................. 2-82.4 Using The BDM Port .......................................................................................... 2-8
Chapter 3 Using the Monitor/Debug Firmware
3.1 What Is dBUG?................................................................................................... 3-13.2 Operational Procedure ........................................................................................ 3-33.2.1 System Power-up ............................................................................................ 3-33.2.2 System Initialization ....................................................................................... 3-43.2.2.1 External RESET Button.............................................................................. 3-43.2.2.2 ABORT Button........................................................................................... 3-43.2.2.3 Software Reset Command .......................................................................... 3-43.3 Command Line Usage ........................................................................................ 3-53.4 Commands .......................................................................................................... 3-53.5 TRAP #15 Functions ........................................................................................ 3-403.5.1 OUT_CHAR ................................................................................................. 3-403.5.2 IN_CHAR ..................................................................................................... 3-413.5.3 CHAR_PRESENT........................................................................................ 3-413.5.4 EXIT_TO_dBUG.......................................................................................... 3-41
Appendix A Configuring dBUG for Network Downloads
A.1 Required Network Parameters ............................................................................ 1-1A.2 Configuring dBUG Network Parameters............................................................ 1-2A.3 Troubleshooting Network Problems................................................................... 1-3
Appendix B Schematics
Appendix C Evaluation Board BOM
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ILLUSTRATIONSFigureNumber Title Page
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1-1 M523xEVB Block Diagram ......................................................................................... 1-31-2 MCF5235 Block Diagram ............................................................................................ 1-51-3 External Memory Scheme ............................................................................................ 1-61-4 J1- BDM Connector Pin Assignment ......................................................................... 1-192-1 Minimum System Configuration .................................................................................. 2-22-2 2.1mm Power Connector .............................................................................................. 2-42-3 2-Lever Power Connector ............................................................................................. 2-42-4 Pin Assignment for Female (Terminal) Connector....................................................... 2-62-5 Jumper Locations .......................................................................................................... 2-73-1 Flow Diagram of dBUG Operational Mode ................................................................. 3-3
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TABLESTable Title Page
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Number Number1-1 M523x Product Family ................................................................................................. 1-11-2 The M523xEVB Default Memory Map........................................................................ 1-81-3 D[20:19] External Boot Chip Select Configuration ..................................................... 1-91-4 SW7-1 RCON ............................................................................................................... 1-91-5 SW7-2 JTAG_EN ......................................................................................................... 1-91-6 SW7-[4:3] Encoded Clock Mode ............................................................................... 1-101-7 SW7-5 Chip Configuration Mode............................................................................... 1-101-8 SW7-[7:6] Boot Device .............................................................................................. 1-101-9 SW7-8 Bus Drive Strength ......................................................................................... 1-101-10 SW7-[10:9] Address/Chip Select Mode ..................................................................... 1-101-11 M523xEVB Clock Source Selection .......................................................................... 1-111-12 UART2/FlexCAN1 Jumper Configuration................................................................. 1-141-13 FlexCAN1 Jumper Configuration............................................................................... 1-141-14 FlexCAN0 Jumper Configuration............................................................................... 1-151-15 CAN Bus Connector Pinout........................................................................................ 1-151-16 Ethernet/eTPU Jumper Configuration ........................................................................ 1-161-17 eTPU Header Pin Assignment .................................................................................... 1-171-18 USB DMA Enable and Disable Settings .................................................................... 1-211-19 J7................................................................................................................................. 1-211-20 J8................................................................................................................................. 1-221-21 J9................................................................................................................................. 1-231-22 J10............................................................................................................................... 1-241-23 User LEDs................................................................................................................... 1-261-24 LED Functions ............................................................................................................ 1-262-1 Power LEDs.................................................................................................................. 2-52-2 Pin Assignment for Female (Terminal) Connector....................................................... 2-63-1 dBUG Command Summary.......................................................................................... 3-6C-1 MCF523xEVB BOM.................................................................................................... 3-1
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Number Number
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Chapter 1 M523xEVB This document details the setup and configuration of the ColdFire M523xEVB evaluationboard (hereafter referred to as the EVB). The EVB is intended to provide a mechanism foreasy customer evaluation of the MCF523x family of ColdFire microprocessors and tofacilitate hardware and software development. The EVB can be used by software andhardware developers to test programs, tools, or circuits without having to develop acomplete microprocessor system themselves. All special features of the MCF523x familyare supported.
The heart of the evaluation board is the MCF5235, all the other M523x family membershave a subset of the MCF5235 specification and can therefore be fully emulated using theMCF5235 device. Table 1-1 below details the full product family.
All of the devices in the same package are pin compatible.
The EVB provides for low cost software testing with the use of a ROM resident debugmonitor, dBUG, programmed into the external Flash device. Operation allows the user toload code in the on-board RAM, execute applications, set breakpoints, and display ormodify registers or memory. No additional hardware or software is required for basicoperation.
Table 1-1. M523x Product Family
Part Number Package eTPU FEC CRYPTO CAN
MCF5232CAB80 160 QFP 16-channel No No 1
MCF5232CVM100 196 MAPBGA 16-channel No No 1
MCF5232CVM150 196 MAPBGA 16-channel No No 1
MCF5233CVM100 256 MAPBGA 32-channel No No 2
MCF5233CVM150 256 MAPBGA 32-channel No No 2
MCF5234CVM100 256 MAPBGA 16-channel Yes No 1
MCF5234CVM150 256 MAPBGA 16-channel Yes No 1
MCF5235CVM100 256 MAPBGA 16-channel Yes Yes 2
MCF5235CVM150 256 MAPBGA 16-channel Yes Yes 2
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Specifications
• Motorola MCF5235 Microprocessor (150 MHz max core frequency)
• External Clock source: 25 MHz
• Operating temperature: 0°C to +70°C
• Power requirement: 6–14V DC @ 300 ma Typical
• Power output: 5V, 3.3V and 1.5V regulated supplies
• Board Size: 10.00 × 5.40 inches, 8 layers
Memory Devices:
• 16-Mbyte SDRAM
• 2-Mbyte (512K × 16) Page Mode FLASH or 4-Mbyte (512K × 32) Page mode FLASH
• 1-Mbyte ASRAM (optional)
• 64-Kbyte SRAM internal to MCF523x device
Peripherals:
• Ethernet port 10/100Mb/s (Dual-Speed Fast Ethernet Transceiver, with MII)
• UART0 (RS-232 serial port for dBUG firmware)
• UART1 (auxiliary RS-232 serial port)
• UART2 (auxiliary1 RS-232 serial port jumper selectable with FlexCAN1)
• Enhanced Time Processor Unit (eTPU)
• I2C interface
• QSPI interface to ADC
• FlexCan0 interface
• USB Host and Device Interface
• BDM/JTAG interface
User Interface:
• Reset logic switch (debounced)
• Boot logic selectable (dip switch)
• Abort/IRQ7 logic switch (debounced)
• PLL Clocking options - Oscillator, Crystal or SMA for external clocking signals
• LEDs for power-up indication, general purpose I/O, and timer output signals
• Expansion connectors for daughter card
• UNI-3 connector for motor control cards
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MCF5235 Microprocessor
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Software:
• Resident firmware package that provides a self-contained programming and operating environment (dBUG)
*There is a jumper that allows the option of choosing between 16 eTPU channelsand Ethernet or 32 eTPU channels and no Ethernet
Figure 1-1. M523xEVB Block Diagram
1.1 MCF5235 MicroprocessorThe microprocessor used on the EVB is the highly integrated Motorola MCF5235 32-bitColdFire variable-length RISC processor. The MCF5235 implements a ColdFire Version 2core with a maximum core frequency of 150 MHz and external bus speed of 75 MHz.Features of the MCF5235 include:
• V2 ColdFire core with enhanced multiply-accumulate unit (EMAC) providing 144 Dhrystone 2.1MIPS @ 150 MHz
ColdFire MCF523X
RS-232 transceivers (2)
DB-9 (2) connector
Ethernet Transceiver*
RJ-45 connector
25 MHz Osc.
(4) 60 pin Daughter Card expansion connectors
Dat
a [3
1:0]
Add
ress
[23
:0]
Con
trol
Sig
nals
SDRAM 16 Mbytes
Flash 2-4 Mbytes
ASRAM 1 Mbyte
Peri
pher
al s
igna
ls
CAN Transceiver DB-9 connector
RS-232 / CAN Transceiver
DB-9 connector
26-pin Debug Header
Clocking circuitry
25 MHz Osc.
ADC
USB 2.0 Host & Device
ETPU Headers*
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MCF5235 Microprocessor
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• eTPU with 16 or 32 channels, 6 Kbytes of code memory and 1.5 Kbytes of data memory with Nexus debug support
• 64 Kbytes of internal SRAM
• External bus speed of one half the CPU operating frequency (75 MHz bus @ 150 MHz core)
• 10/100 Mbps bus-mastering Ethernet controller
• 8 Kbytes of configurable instruction/data cache
• Three universal asynchronous receiver/transmitters (UARTs) with DMA support
• Controller area network 2.0B (FlexCAN module)
— Optional second FlexCAN module multiplexed with the third UART
• Inter-integrated circuit (I2C) bus controller
• Queued serial peripheral interface (QSPI) module
• Hardware cryptography accelerator (optional)
— Random number generator
— DES/3DES/AES block cipher engine
— MD5/SHA-1/HMAC accelerator
• Four channel 32-bit direct memory access (DMA) controller
• Four channel 32-bit input capture/output compare timers with optional DMA support
• Four channel 16-bit periodic interrupt timers (PITs)
• Programmable software watchdog timer
• Interrupt controller capable of handling up to 126 interrupt sources
• Clock module with Phase Locked Loop (PLL)
• External bus interface module including a 2-bank synchronous DRAM controller
• 32-bit non-multiplexed bus with up to 8 chip select signals that support page-mode FLASH memories
The MCF5235 communicates with external devices over a 32-bit wide data bus, D[31:0].The MCF5235 can address a 32 bit address range. However, only 24 bits are available onthe external bus A[23:0]. There are internally generated chip selects to allow the full 32 bitaddress range to be selected. There are regions that can be decoded to allow supervisor,user, instruction, and data each to have the 32-bit address range.
All the processor's signals are available via daughter card expansion connectors. Refer tothe schematic (Appendix B) for their pin assignments.
The MCF5235 processor has the capability to support both BDM and JTAG. These portsare multiplexed and can be used with third party tools to allow the user to download code
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MCF5235 Microprocessor
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to the board. The board is configured to boot up in the normal/BDM mode of operation. TheBDM signals are available at the port labeled BDM.
Figure 1-2 shows the MCF5235 processor block diagram.
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MCF5235 Microprocessor
(To
C
]
]
]
:0]
]
(To
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Figure 1-2. MCF5235 Block Diagram
64 KbytesSRAM
(8Kx16)x4
EIM
ETHERNET
V2 ColdFire CPU
INTC0
Watchdog
PIT0
JTAG
TAP
CACHE(1Kx32)x2
PIT1 PIT2 PIT3
4 CH DMA
UART0
UART1 I2C QSPI
DTIM0
DTIM1
DTIM2
DTIM3
TimerP
AD
I
PLLCLKGEN
UART2
8 Kbytes
EdgePort
SDRAMC
CHIP
EBI
SELECTS
/From PADI)
(To/From
FAST
CONTROLLER(FEC)
FEC
TnIN
TnOUT
UnRXD
UnTXD
SDA
SCL
SDRAM
QSPI
UnRTS
UnCTS
PORTSCIM(GPIO)
D[31:0
A[23:0
R/W
CS[3:0
TA
TSIZ[1
TEA
BS[3:0
DIV EMAC
DREQ[2:0]
INTC1Arbiter
(To/From SRAM backdoor)
(To/From Arbiter)
SKHA
RNGA
MDHA
/From PADI)
CryptographyModules
DACK[2:0]
BD
M
(To/From INTC)
MU
X
PADI)
JTAG_EN
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System Memory
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1.2 System MemoryThe following diagram shows the external memory implementation on the EVB.
Figure 1-3. External Memory Scheme
Note: The external bus interface signals to the external ASRAM and FLASH (and USB) are buffered. This is in order not to exceed the maximum output load capacitance of the microprocessor on the EVB.
The signals to the expansion connectors remain unbuffered to provide a “true” interface to the user.
1.2.1 External Flash
The EVB is fitted with a single 512K × 16 page-mode FLASH memory (U19) giving a totalmemory space of 2Mbytes. Alternatively a footprint is available for the EVB user toupgrade this device to a 512K × 32 page-mode FLASH memory (U35), doubling thememory size to 4Mbytes. Either U19 OR U35 should be fitted on the board - both devicescannot be populated at the same time. Refer to the specific device data sheet and samplesoftware provided for configuring the FLASH memory.
Users should note that the debug monitor firmware is installed in this flash device.Development tools or user application programs may erase or corrupt the debug monitor. Ifthe debug monitor becomes corrupted and it’s operation is desired, the firmware must beprogrammed into the flash by applying a development port tool such as BDM. Users shoulduse caution to avoid this situation. The M523xEVB dBUG debugger/monitor firmware is
ExpansionConnectors
SDRAM(16 Mbytes)
ASRAM(1 Mbyte)
Flash(512K × 16
or512K × 32)
BuffersMPU
Data
Address
Control
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System Memory
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programmed into the lower sectors of Flash (0xFFE0_0000 to 0xFFE2_FFFF for 2Mbytesof FLASH or 0xFFC0_0000 to 0xFFC2_FFFF for 4 Mbytes of FLASH).
By default with U19 fitted on the EVB, jumper 64 (JP64) provides an alternative hardwaremechanism for write protection.
If the user has replaced U19 with the 32-bit FLASH device (U35), jumper 31 (JP31) hasthe same functionality as JP64. U35 also has it’s own hardware write protect pin (C5) whichprotects the bottom boot sector when pulled to ground.
1.2.2 SDRAM
The EVB is populated with 16 Mbytes of SDRAM. This is done with two devices (MicronMT48LC4M16A2TG) each with a 16 bit data bus. Each device is organized as 1 Meg × 16× 4 banks with a 16 bit data bus. One device stores the upper 16-bit word and the other thelower 16 bit word of the MCF523x 32 bit data bus.
1.2.3 ASRAM
The EVB has a footprint for two 512K × 16 Asynchronous SRAM devices (CypressSemiconductor - CY7C1041CV3310ZC). These memory devices (U1 and U2) may bepopulated by the user for benchmarking purposes.
Also see Section 1.2.5, “M523xEVB Memory Map”.
1.2.4 Internal SRAM
The MCF5235 processor has 64-Kbytes of internal SRAM memory which may be used asdata or instruction memory. This memory is mapped to 0x2000_0000 and configured asdata space but is not used by the dBUG monitor except during system initialization. Aftersystem initialization is complete, the internal memory is available to the user. The memoryis relocatable to any 32-Kbyte boundary within the processor’s four gigabyte address space.
1.2.5 M523xEVB Memory Map
Interface signals to support the interface to external memory and peripheral devices aregenerated by the memory controller. The MCF5235 supports 8 external chip selects,CS[1:0] are used with external memories, CS2 is used for the USB controller and CS[7:3]are easily accessible to users via the daughter card expansion connectors. CS0 alsofunctions as the global (boot) chip-select for booting out of external flash.
Since the MCF5235 chip selects are fully programmable, the memory banks may be locatedat any 64-Kbyte boundary within the processor’s four gigabyte address space.
The default memory map for this board as configured by the Debug Monitor located in theexternal FLASH bank can be found in table 1-2. The internal memory space of the
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System Memory
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MCF5235 is detailed further in the MCF5235 Reference Manual. Chip Selects 0 and 1 canbe changed by user software to map the external memory in different locations but the chipselect configuration such as wait states and transfer acknowledge for each memory typeshould be maintained.
Chip Select Usage:
External FLASH Memory CS0
External ASRAM Memory CS1
Table 1-2 shows the M523xEVB memory map.
1.2.5.1 Reset Vector Mapping
Asserting the reset input signal to the processor causes a reset exception. The resetexception has the highest priority of any exception; it provides for system initialization andrecovery from catastrophic failure. Reset also aborts any processing in progress when thereset input is recognized. Processing cannot be recovered.
The reset exception places the processor in the supervisor mode by setting the S-bit anddisables tracing by clearing the T bit in the SR. This exception also clears the M-bit and setsthe processor’s interrupt priority mask in the SR to the highest level (level 7). Next, theVBR is initialized to zero (0x00000000). The control registers specifying the operation ofany memories (e.g., cache and/or RAM modules) connected directly to the processor aredisabled.
Once the processor is granted the bus, it then performs two longword read bus cycles. Thefirst longword at address 0 is loaded into the stack pointer and the second longword ataddress 4 is loaded into the program counter. After the initial instruction is fetched frommemory, program execution begins at the address in the PC. If an access error or addresserror occurs before the first instruction is executed, the processor enters the fault-on-faulthalted state.
The Memory that the MCF5235 accesses at address 0 is determined at reset by samplingD[20:19].
Table 1-2. The M523xEVB Default Memory Map
Address Range Signal and Device
0x0000_0000–0x00FF_FFFF 16 Mbyte SDRAM
0x2000_0000–0x2000_FFFF 64 Kbytes Internal SRAM
0x3000_0000–0x300F_FFFF External ASRAM (not fitted)
0xFFE0_0000–0xFFFF_FFFFor0xFFC0_0000–0xFFFF_FFFF
2 Mbytes External Flashor4 Mbytes External Flash
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1.3 Support Logic
1.3.1 Reset Logic
The reset logic provides system initialization. Reset occurs during power-on or viaassertion of the signal RESET which causes the MCF5235 to reset. RESET is triggered bythe reset switch (SW6) which resets the entire processor/system.
dBUG configures the MCF5235 microprocessor internal resources during initialization.The contents of the exception table are copied to address 0x0000_0000 in the SDRAM. TheSoftware Watchdog Timer is disabled, the Bus Monitor is enabled, and the internal timersare placed in a stop condition. A memory map for the entire board can be seen in Table 1-2.
If the external RCON pin is asserted (SW7-1 ON) during reset, then various chip functions,including the reset configuration pin functions after reset, are configured according to thelevels driven onto the external data pins. See tables below on settings for resetconfigurations.
If the RCON pin is not asserted (SW7-1 OFF) during reset, the chip configuration and thereset configuration pin functions after reset are determined by the RCON register or fixeddefaults, regardless of the states of the external data pins.
Table 1-3. D[20:19] External Boot Chip Select Configuration
D[19:18] Boot Device/Data Port Size
00 External (32-bit)
01 External (16-bit)
10 External (8-bit)
11 External (32-bit)
Table 1-4. SW7-1 RCON
SW7-1 Reset Configuration
OFF RCON not asserted, Default Chip configuration or RCON register settings
ON RCON is asserted, Chip functions, including the reset configuration after reset,are configured according to the levels driven onto the external data pins.
Table 1-5. SW7-2 JTAG_EN
SW1-2 JTAG Enable
OFF JTAG interface enabled
ON BDM interface enabled
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Table 1-6. SW7-[4:3] Encoded Clock Mode
SW7-3 SW7-4 Clock Mode
OFF OFF External clock mode- (PLL disabled)
OFF ON 1:1 PLL
ON OFF Normal PLL mode with external clock reference
ON ON Normal PLL mode w/crystal oscillator reference
Table 1-7. SW7-5 Chip Configuration Mode
SW7-5 RCON (SW7-1) Mode
OFF ON Reserved
ON ON Master
X OFF Master
Table 1-8. SW7-[7:6] Boot Device
SW7-6 SW7-7 RCON (SW7-1) Boot Device
OFF OFF ON External (32-bit)
OFF ON ON External (16-bit)
ON OFF ON External (8-bit)
ON ON ON External (32-bit)
X X OFF External (32-bit)
Table 1-9. SW7-8 Bus Drive Strength
SW7-8 RCON (SW7-1) Drive Strength
OFF ON Partial Bus Drive
ON ON Full Bus Drive
X OFF Partial Bus Drive
Table 1-10. SW7-[10:9] Address/Chip Select Mode
SW7-9 SW7-10 RCON (SW7-1) Mode
OFF OFF ON PF[7:5] = /CS[6:4]
OFF ON ON PF[7] = /CS6, PF[6:5] = A[22:21]
ON OFF ON PF[7:6] = /CS[6:5], PF[5] = A21
ON ON ON PF[7:5] = A[23:21]
X X OFF PF[7:5] = A[23:21]
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1.3.2 Clock Circuitry
The are three options to provide the clock to the CPU. These options can be configured bysetting JP[35:37]. See Table 1-11 below.
The 25-MHz oscillator (U23) also feeds the Ethernet chip (U11).
There is also a 12-MHz crystal feeding the USB controller (U33).
1.3.3 Watchdog Timer
The dBUG Firmware does NOT enable the watchdog timer on the MCF5235.
1.3.4 Exception Sources
The ColdFire® family of processors can receive seven levels of interrupt priorities. Whenthe processor receives an interrupt which has a higher priority than the current interruptmask (in the status register), it will perform an interrupt acknowledge cycle at the end ofthe current instruction cycle. This interrupt acknowledge cycle indicates to the source of theinterrupt that the request is being acknowledged and the device should provide the propervector number to indicate where the service routine for this interrupt level is located. If thesource of interrupt is not capable of providing a vector, its interrupt should be set up as anautovector interrupt which directs the processor to a predefined entry in the exception table(refer to the MCF523x User's Manual).
The processor goes to an exception routine via the exception table. This table is stored inthe Flash EEPROM. The address of the table location is stored in the VBR. The dBUGROM monitor writes a copy of the exception table into the RAM starting at $00000000. Toset an exception vector, the user places the address of the exception handler in theappropriate vector in the vector table located at $00000000 and then points the VBR to$00000000.
The MCF5235 microprocessor has seven external interrupt request lines IRQ[7:1]. Theinterrupt controller is capable of providing up to 63 interrupt sources. These sources are:-
• External interrupt signals IRQ[7:1] (EPORT)
• Software watchdog timer module
• Timer modules
Table 1-11. M523xEVB Clock Source Selection
JP35 JP36 JP37 Clock Selection
1-2 1-2 ON 25 MHz Oscillator (default setting)
2-3 1-2 ON 25 MHz External Clock
X 2-3 OFF 25 MHz Crystal (not populated)
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• UART modules 0, 1 and 2
• I2C module
• DMA module
• QSPI module
• FEC module
• PIT
• Security module
• FlexCAN0 and FlexCAN1
• eTPU
All external interrupt inputs are edge sensitive. The active level is programmable. Aninterrupt request must be held valid until an IACK cycle starts to guarantee correctprocessing. Each interrupt input can have it’s priority programmed by setting the xIPL[2:0]bits in the Interrupt Control Registers.
No interrupt sources should have the same level and priority as another. Programming twointerrupt sources with the same level and priority can result in undefined operation.
The M523xEVB hardware uses IRQ7 to support the ABORT function using the ABORTswitch (SW5). This switch is used to force an interrupt (level 7, priority 3) if the user'sprogram execution should be aborted without issuing a RESET (refer to Chapter 2 for moreinformation on ABORT). Since the ABORT switch is not capable of generating a vector inresponse to a level seven interrupt acknowledge from the processor, the dBUG programsthis interrupt request for autovector mode.
Refer to MCF523x User’s Manual for more information about the interrupt controller.
1.3.5 TA Generation
The processor starts a bus cycle by asserting CSx with the other control signals. Theprocessor then waits for a transfer acknowledgment (TA) either from within (Autoacknowledge - AA mode) or from the externally addressed device before it can completethe bus cycle. -TA is used to indicate the completion of the bus cycle. It also allows deviceswith different access times to communicate with the processor properly asynchronously.The MCF5235 processor, as part of the chip-select logic, has a built-in mechanism togenerate TA for all external devices which do not have the capability to generate this signal.For example the Flash ROM cannot generate a TA signal. The chip-select logic isprogrammed by the dBUG ROM Monitor to generate TA internally after a pre-programmednumber of wait states. In order to support future expansion of the M523xEVB, the TA inputof the processor is also connected to the Processor Expansion Bus (J9, pin 44). This allowsany expansion boards to assert this line to provide a TA signal to the processor. On theexpansion boards this signal should be generated through an open collector buffer with no
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pull-up resistor; a pull-up resistor is included on this board. All TA signals from expansionboards should be connected to this line.
1.3.6 User’s Program
JP64 on the 16Mbit FLASH (U19) or JP31 if using 32Mbit FLASH (U35) allows users totest code from boot/POR without having to overwrite the ROM Monitor.
When the jumper is set between pins 1 and 2, the behavior of the system is normal, dBUGboots and then runs from 0xFFE00000 (0xFFC00000). When the jumper is set betweenpins 2 and 3, the board boots from the top half of the FLASH (0xFFF00000).
Procedure:
1. Compile and link as though the code was to be placed at the base of the flash.
2. Set up the jumper JP64 (JP31) for Normal operation, pin1 connected to pin 2.
3. Download to SDRAM (If using serial or ethernet, start the ROM Monitor first. If using BDM via a wiggler cable, download first, then start ROM Monitor by pointing the program counter (PC) to 0xFFE00400(0xFFC00400) and run.)
4. In the ROM Monitor, execute the ’FL write <dest> <src> <bytes>’ command.
5. Move jumper JP64 (JP31) to pin 2 connected to pin 3 and push the reset button (S2). User code should now be running from reset/POR.
1.4 Communication PortsThe EVB provides external communication interfaces for two UART serial ports, aUART/FlexCAN1 port, FlexCan0 port, QSPI, I2C port, 10/100T ethernet port, eTPU port(including UNI3 and HS/ENCO connectors for auxiliary motor control cards), USB Hostport, USB Device port, and BDM/JTAG port.
1.4.1 UART0 and UART1 Ports
The MCF5235 device has three built in UARTs, each with its own software programmablebaud rate generator. Two of these UART interfaces are brought out to RS232 transceivers.One channel is the ROM Monitor to Terminal output and the other is available to the user.The ROM Monitor programs the interrupt level for UART0 to Level 3, priority 2 andautovector mode of operation. The interrupt level for UART1 is programmed to Level 3,priority 1 and autovector mode of operation. The signals from these channels are availableon expansion connectors J7 and J8. The signals of UART0 and UART1 are passed throughthe RS-232 transceivers (U30) & (U31) and are available on DB-9 connectors (P4) and(P5).
Refer to the MCF523x User’s Manual for programming the UART’s and their registermaps.
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1.4.2 UART2/FlexCAN1 Port
The third UART on the MCF5235 is multiplexed with the second FlexCAN (FlexCAN1)module. As these two modules are multiplexed such that the user has access to one or theother, the functionality on the EVB is jumper selectable. Table 1-12 shows the jumperconfiguration to activate UART2 or FlexCAN1.
The signals of UART2 are passed through RS-232 transceiver U32 and are jumperselectable (for settings see Table 1-12) on DB-9 connector P6.
The CAN1TX and CAN1RX signals from FlexCAN1 are brought out to a 3.3-V CANtransceiver (Texas Instruments - SN65HVD230D) and are jumper selectable (for settingssee Table 1-12) on DB-9 connector P6. Jumpers JP3 and JP4 control the CAN hardwareconfiguration.
1.4.3 FlexCAN0 Port
The EVB provides 1 dedicated CAN transceiver. The CAN0TX and CAN0RX signals arebrought out to a 3.3V CAN transceiver (Texas Instruments - SN65HVD230D). Jumper JP1and JP2 control the CAN hardware configuration.
Table 1-12. UART2/FlexCAN1 Jumper Configuration
Jumper UART2 Setting FlexCAN1 Setting
JP7 1-2 2-3
JP12 1-2 2-3
JP25 2-3 X
JP26 2-3 X
JP50 2-3 1-2
JP51 2-3 1-2
JP52 2-3 1-2
Table 1-13. FlexCAN1 Jumper Configuration
Jumper Function ON OFF
JP3 Transceiver mode Standby High Speed (No Slope Control)
JP4 CAN Termination Terminating resistor between CANL and CANH
No terminating resistor
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The CANL and CANH signals are brought out from the CAN transceiver to a female DB-9connector (P1) in the configuration below.
1.4.4 10/100T Ethernet Port
The MCF5235 microprocessor populated on the EVB is a superset device of the MCF523xfamily. The upper 16 eTPU channels are multiplexed with the ethernet port giving the EVBuser the choice of utilizing either the full 32-channels of eTPU or 16-channels of eTPU withthe Fast Ethernet Controller (FEC) activated. Pin M4 on the MCF5235 configures theinternal functionality of these 16 pins. If the user is using the FEC, pin M4 must be pulledlow by setting SW7-11 to the ON position.
These 16 pins are also jumper selectable between the eTPU and the FEC in order to isolatethe external circuitry required to implement the functionality of these modules. Table 1-16lists the appropriate jumper settings to enable eTPU or FEC functionality on these pins.
The MCF5235 device performs the full set of IEEE 802.3/Ethernet CSMA/CD mediaaccess control and channel interface functions. The MCF5235 Ethernet Controller requiresan external interface adaptor and transceiver function to complete the interface to theethernet media. The MCF5235 Ethernet module also features an integrated fast (100baseT)Ethernet media access controller (MAC).
The Fast Ethernet controller (FEC) incorporates the following features:
• Support for three different Ethernet physical interfaces:
— 100-Mbps IEEE 802.3 MII
— 10-Mbps IEEE 802.3 MII
— 10-Mbps 7-wire interface (industry standard)
• IEEE 802.3 full duplex flow control
Table 1-14. FlexCAN0 Jumper Configuration
Jumper Function ON OFF
JP1 Transceiver mode Standby High Speed (No Slope Control)
JP2 CAN Termination Terminating resistor between CANL and CANH
No terminating resistor
Table 1-15. CAN Bus Connector Pinout
DB-9 pin Signal
1,4-6,7-9 Not Connected
2 CANL
3 Ground
7 CANH
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• Programmable max frame length supports IEEE 802.1 VLAN tags and priority
• Support for full-duplex operation (200Mbps throughput) with a minimum system clock rate of 50 MHz
• Support for half-duplex operation (100Mbps throughput) with a minimum system clock rate of 25 MHz
• Retransmission from transmit FIFO following a collision (no processor bus utilization)
• Automatic internal flushing of the receive FIFO for runts (collision fragments) and address recognition rejects (no processor bus utilization)
• Address recognition
— Frames with broadcast address may be always accepted or always rejected
— Exact match for single 48-bit individual (unicast) address
— Hash (64-bit hash) check of individual (unicast) addresses
— Hash (64-bit hash) check of group (multicast) addresses
— Promiscuous mode
For more details see the MCF523x User’s Manual. The on board ROM MONITOR isprogrammed to allow a user to download files from a network to memory in differentformats. The current compiler formats supported are S-Record, COFF, ELF or Image.
Table 1-16. Ethernet/eTPU Jumper Configuration
Jumper PinEthernet Setting
Ethernet Signal
eTPU Setting
eTPU Channel
JP5 D5 2-3 ERXER 1-2 23
JP9 C5 2-3 ETXCLK 1-2 22
JP10 B5 2-3 ETXD2 1-2 18
JP11 A5 2-3 ETXD1 1-2 17
JP13 D6 2-3 ETXEN 1-2 21
JP14 C6 2-3 ETXER 1-2 20
JP15 B6 2-3 ETXD3 1-2 19
JP16 C4 2-3 ERXD0 1-2 24
JP17 B7 2-3 ETXD0 1-2 16
JP18 C3 2-3 ERXD1 1-2 25
JP19 D4 2-3 ERXD2 1-2 26
JP20 D3 2-3 ERXD3 1-2 27
JP21 E3 2-3 ERXCLK 1-2 29
JP22 E4 2-3 ERXDV 1-2 28
JP23 F3 2-3 ECOL 1-2 31
JP24 F4 2-3 ECRS 1-2 30
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1.4.5 eTPU
The eTPU is an intelligent programmable I/O controller with its own core and memorysystem, allowing it to perform complex timing and I/O management independently of theCPU. The eTPU is essentially a co-processor designed for timing control, I/O handling,serial communications, motor control. and engine control applications and accesses datawithout the host CPU’s intervention. Consequently, the host CPU setup and service timesfor each timer event are minimized or eliminated.
The eTPU is an enhanced version of the TPU module implemented on the MC68332 andMPC500 products. Enhancements of the eTPU include a more powerful processor whichhandles high-level C code efficiently and allows for more functionality and increasedperformance. Although there is no compatibility at microcode level, the eTPU maintainsseveral features of older TPU versions and is conceptually almost identical. The eTPUlibrary is a superset of the standard TPU library functions modified to take advantage ofenhancements in the eTPU. These, along with a C compiler, make it relatively easy to portolder applications. By providing source code for the Motorola library, it is possible for theeTPU to support the users own function development.
The eTPU has up to 32 timer channels in addition to having 6 Kbytes of code memory and1.5 Kbytes of data memory that stores software modules downloaded at boot time and thatcan be mixed and matched as required for any specific application.
As mentioned in Section 1.4.4, “10/100T Ethernet Port,” the upper 16-channels of theeTPU are multiplexed with the Fast Ethernet Controller.
Refer to Table 1-16 to set the appropriate jumpers to enable 16 or 32-channels.
To configure the device to operate with the top 16-channels of the eTPU activated, pin M4must be pulled high by setting SW7-11 to the OFF position.
All 32 eTPU channels are available on a 0.1” 2x20 Molex connector providing easy accessto the eTPU for the EVB user.
Table 1-17. eTPU Header Pin Assignment
Pin eTPU Signal Pin eTPU Signal
1 +3.3V 2 +5V
3 TPUCH16 4 UTPUODIS
5 TPUCH17 6 LTPUODIS
7 TPUCH18 8 TPUCH0
9 TPUCH19 10 TPUCH1
11 TPUCH20 12 TPUCH2
13 TPUCH21 14 TPUCH3
15 TPUCH22 16 TPUCH4
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There is a UNI3 connector and HS/ENCO connector on the EVB for connection to anauxiliary card.
The auxiliary card is intended for evaluation of the eTPU functionality.
1.4.6 BDM/JTAG Port
The MCF5235 processor has a Background Debug Mode (BDM) port, which supportsReal-Time Trace and Real-Time Debug. The signals which are necessary for debug areavailable at connector (J1). Figure 1-4 shows the (J1) Connector pin assignment.
17 TPUCH23 18 TPUCH5
19 TPUCH24 20 TPUCH6
21 TPUCH25 22 TPUCH7
23 TPUCH26 24 TPUCH8
25 TPUCH27 26 TPUCH9
27 TPUCH28 28 TPUCH10
29 TPUCH29 30 TPUCH11
31 TPUCH30 32 TPUCH12
33 TPUCH31 34 TPUCH13
35 GND 36 TPUCH14
37 TCRCLK 38 TPUCH15
39 GND 40 GND
Table 1-17. eTPU Header Pin Assignment (continued)
Pin eTPU Signal Pin eTPU Signal
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Figure 1-4. J1- BDM Connector Pin Assignment
The BDM connector can also be used to interface to JTAG signals. On reset, the JTAG_ENsignal selects between multiplexed debug module and JTAG signals. See Table 1-5.
1.4.7 I2C
The MCF5235’s I2C module includes the following features:
• Compatibility with the I2C bus standard version 2.1
• Multi master operation
• Software programmable for one of 50 different clock frequencies
• Software selectable acknowledge bit
• Interrupt driven byte by byte data transfer
• Arbitration-lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Start and stop signal generation and detection
• Repeated start signal generation
• Acknowledge bit generation and detection
• Bus busy detection
Please see the MCF523x User’s Manual for more detail. The I2C signals from theMCF5235 device are brought out to expansion connector (J13).
1
3
5
7
9
11
13
15
17
19
21
23
25
2
4
6
8
10
12
14
16
18
20
22
24
26
BKPT
DSCLK
DEVELOPER RESERVED
DSI
DSO
PST3
PST1
DDATA3
DDATA1
GND
MOTOROLA RESERVED
PSTCLK
TA
GND
GND
RESET
GND
PST2
PST0
DDATA2
DDATA0
MOTOROLA RESERVED
GND
Core Voltage
DEVELOPER RESERVED
I/O or Pad Voltage
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The I2C functionality of the MCF5235 is multiplexed on the same pins as the QSPI.Jumpers JP6 and JP8 are used to connect/disconnect the I2C signals, SDA and SCL. Toenable I2C JP6 and JP8 should be set between pins 2 and 3.
1.4.8 QSPI
The QSPI (Queued Serial Peripheral Interface) module provides a serial peripheralinterface with queued transfer capability. It will support up to 16 stacked transfers at onetime, minimizing CPU intervention between transfers. Transfer RAMs in the QSPI areindirectly accessible using address and data registers.
Functionality is very similar, but not identical, to the QSPI portion of the QSM (QueuedSerial Module) implemented in the MC68332 processor.
• Programmable queue to support up to 16 transfers without user intervention
• Supports transfer sizes of 8 to 16 bits in 1-bit increments
• Four peripheral chip-select lines for control of up to 15 devices
• Baud rates from 147.1-Kbps to 18.75-Mbps at 75 MHz.
• Programmable delays before and after transfers
• Programmable QSPI clock phase and polarity
• Supports wrap-around mode for continuous transfers
Please see the MCF523x User’s Manual for more detail. The QSPI signals from theMCF5235 device are brought out to expansion connector (J12).
Some of the QSPI signals are multiplexed with the I2C module. JP6 and JP8 should be setbetween pins 1 and 2 to enable the QSPI module.
The EVB features an A to D converter (ADC) interfaced to the CPU via the QSPI. TheADC uses QSPI chip select 0. This chip select has a jumper that can be removed if the EVBuser is not using the ADC and wishes to connect QSPI_CS0 to an alternative device.
1.4.9 USB Host and Device
The EVB features a USB controller interfaced externally to the MCF5235 via the DMA andexternal bus modules. The USB controller can be configured to run in Host or Device mode.
There is a series “A” connector (Host) and a series “B” connector (Device) populated onthe EVB. Either one or the other can be used depending on whether the USB controller isconfigured to run in Host or Device mode. JP56 must be set between pins 2 and 3 if thecontroller is configured in Host mode and between pin 1 and 2 if the controller is configuredin Device mode.
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The USB controller also has On-The-Go (OTG) functionality. There is a footprint on theEVB for an OTG Mini-AB connector if the user wants to utilize USB OTG. If using OTGJP55 must be fitted.
For more details see the Philips Semiconductor datasheet for the ISP1362 USB OTGcontroller.
There are a series of jumpers connected to the USB controller that allow the user todisconnect the DMA and interrupt signals between the CPU and the USB controller if theUSB controller is not in use. This gives the user access to the DMA timer module channels1 and 2 and an extra interrupt signal if they do not require USB functionality. Table 1-18details these jumper settings.
1.5 Connectors and User Components
1.5.1 Daughter Card Expansion Connectors
Four, 60-way SMT connectors (J7, J8, J9 and J10) provide access to all MCF5235 signals.These connectors are ideal for interfacing to a custom daughter card or for simple probingof processor signals. Below is a pinout description of these connectors.
Table 1-18. USB DMA Enable and Disable Settings
Jumper Functionality when Jumper is Fitted Functionality when Jumper is NOT Fitted
JP57 USB DMA request signal DMA Timer 1 input enabled
JP58 USB DMA request signal DMA Timer 2 input enabled
JP59 USB DMA acknowledge signal DMA Timer 1 output enabled
JP60 USB DMA acknowledge signal DMA Timer 2 output enabled
JP61 Interrupt 4 enabled for USB Interrupt 4 disabled from USB
JP62 DACK1 not in use - pulled high DMA acknowledge 1 enabled
JP63 DACK 2 not in use - pulled high DMA acknowledge 2 enabled
Table 1-19. J7
Pin Signal Pin Signal
1 +5V 2 +5V
3 +3.3V 4 +3.3V
5 +3.3V 6 +3.3V
7 GND 8 GND
9 TPUCH24 10 TPUCH6
11 TPUCH17 12 TPUCH4
13 TPUCH18 14 TPUCH5
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15 TPUCH22 16 TPUCH2
17 TPUCH23 18 TPUCH3
19 TPUCH19 20 TPUCH1
21 TPUCH20 22 TPUCH0
23 TPUCH21 24 GND
25 TPUCH16 26 EMDIO
27 U2CTS 28 EMDC
29 I2C_SCL 30 I2C_SDA
31 QSPI_SCK 32 QSPI_DIN
33 BS3 34 QSPI_DOUT
35 BS2 36 QSPI_PCS0
37 BS1 38 SD_SCKE
39 BS0 40 CAN1RX
41 U2RTS 42 U2RXD
43 QSPI_PCS1 44 U1CTS
45 U1RTS 46 CAN1TX
47 U1RXD 48 U2TXD
49 U1TXD 50 CS2
51 CS3 52 CS7
53 CS6 54 CS5
55 CS1 56 CS0
57 CS4 58 A23
59 GND 60 GND
Table 1-20. J8
Pin Signal Pin Signal
1 +5V 2 +1.5V
3 +3.3V 4 +3.3V
5 TPUCH8 6 TPUCH7
7 TPUCH10 8 TPUCH9
9 TPUCH25 10 TPUCH12
11 TPUCH27 12 TPUCH11
13 TPUCH26 14 TPUCH14
Table 1-19. J7 (continued)
Pin Signal Pin Signal
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15 TPUCH29 16 TPUCH13
17 TPUCH28 18 TCRCLK
19 TPUCH31 20 TPUCH15
21 TPUCH30 22 GND
23 GND 24 U0CTS
25 U0RXD 26 DTOUT0
27 DTIN0 28 U0TXD
29 U0RTS 30 GND
31 CLKMOD0 32 +3.3V
33 CLKMOD1 34 GND
35 GND 36 D28
37 D30 38 D29
39 D31 40 D24
41 D26 42 D25
43 D27 44 D21
45 D23 46 D22
47 EXT_RSTIN 48 D19
49 GND 50 GND
51 D13 52 D20
53 D9 54 D17
55 D12 56 D18
57 D15 58 D16
59 GND 60 GND
Table 1-21. J9
Pin Signal Pin Signal
1 +5V 2 +1.5V
3 +3.3V 4 +3.3V
5 +3.3V 6 +3.3V
7 GND 8 GND
9 A21 10 A22
11 A19 12 A20
13 A17 14 A18
Table 1-20. J8 (continued)
Pin Signal Pin Signal
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15 A16 16 A14
17 A15 18 A11
19 A13 20 GND
21 GND 22 A10
23 A12 24 A8
25 A9 26 A7
27 A6 28 A4
29 A5 30 GND
31 A2 32 A0
33 A3 34 A1
35 GND 36 GND
37 DTIN3 38 UTPUODIS
39 DTOUT3 40 LTPUODIS
41 TIP 42 TEA
43 TS 44 TA
45 CAN0RX 46 SD_WE
47 R/W 48 CAN0TX
49 SD_CAS 50 SD_CS0
51 CLKOUT 52 SD_RAS
53 SD_CS1 54 DDATA3
55 XTAL 56 EXTAL
57 GND 58 GND
59 GND 60 GND
Table 1-22. J10
Pin Signal Pin Signal
1 +5V 2 +1.5V
3 +3.3V 4 +3.3V
5 D14 6 D10
7 D11 8 D6
9 D7 10 D8
11 D5 12 D4
13 GND 14 GND
Table 1-21. J9 (continued)
Pin Signal Pin Signal
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1.5.2 Reset Switch (SW6)
The reset logic provides system initilization. Reset occurs during power-on or via assertionof the signal RESET which causes the MCF5235 to reset. Reset is also triggered by the resetswitch (SW6) which resets the entire processor/system.
A hard reset and voltage sense controller (U25) is used to produce an active low power-onRESET signal. The reset switch SW6 is fed into U25 which generates the signal which isfed to the MCF5235 reset, RESET. The RESET signal is an open collector signal and socan be wire OR’ed with other reset signals from additional peripherals. On the EVB,RESET is wire OR’d with the BDM reset signal and there is a reset signal brought out tothe expansion connectors for use with user hardware.
15 D1 16 D2
17 D3 18 OE
19 D0 20 DTOUT1
21 DTIN1 22 +3.3V
23 +3.3V 24 IRQ6
25 IRQ7 26 TSIZ0
27 TSIZ1 28 IRQ2
29 IRQ3 30 IRQ4
31 IRQ5 32 TCLK/PSTCLK
33 DTOUT2 34 DTIN2
35 IRQ1 36 TDI/DSI
37 TDO/DSO 38 TMS/BKPT
39 TRST/DSCLK 40 GND
41 GND 42 PST3
43 PST1 44 PST2
45 PST0 46 DDATA0
47 DDATA2 48 DDATA1
49 GND 50 GND
51 JTAG_EN 52 RCON
53 GND 54 RSTOUT
55 GND 56 RESET
57 GND 58 GND
59 GND 60 GND
Table 1-22. J10 (continued)
Pin Signal Pin Signal
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dBUG configures the MCF5235 microprocessor internal resources during initialization.The instruction cache is invalidated and disabled. The Vector Base Register, VBR, containsan address which initially points to the Flash memory. The contents of the exception tableare written to address $00000000 in the SDRAM. The Software Watchdog Timer isdisabled, the Bus Monitor is enabled, and the internal timers are placed in a stop condition.The interrupt controller registers are initialized with unique interrupt level/priority pairs.
1.5.3 User LEDs
There are eight LEDs available to the user. Each of these LEDs are pulled to +3.3V througha 10 ohm resistor and can be illuminated by driving a logic “0” on the appropriate signal to“sink” the current. Each of these signals can be disconnected from it’s associated LED witha jumper. The table below details which MCF5235 signal is associated with which LED.
1.5.4 Other LEDs
There are several other LED’s on the M523xEVB to signal to the user variousboard/processor/component state. Below is a list of those LEDs and their functions:
Table 1-23. User LEDs
LED MCF5235 Signal Jumper to disconnect
D25 DTOUT0 JP38
D26 DTIN0 JP39
D27 DTOUT1 JP40
D28 DTIN1 JP41
D29 DTOUT2 JP42
D30 DTIN2 JP43
D31 DTOUT3 JP44
D32 DTIN3 JP45
Table 1-24. LED Functions
LED Function
D1-D4 Ethernet Phy functionality
D5-D12 eTPU functionality
D14 +3.3V Power Good
D17 +5V Power Good
D21 +1.5V Power Good
D23 Abort (IRQ7) asserted
D24 Reset (RSTI) asserted
D25-D32 User LEDs (See Table 1-23)
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Chapter 2 Initialization and Setup
2.1 System ConfigurationThe M523xEVB board requires the following items for minimum system configuration:
• The M523xEVB board (provided).
• Power supply, +6V to 14V DC with minimum of 300 mA.
• RS232C compatible terminal or a PC with terminal emulation software.
• RS232 Communication cable (provided).
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Figure 2-1 displays the minimum system configuration.
Figure 2-1. Minimum System Configuration
+7 to +14VDCInput Power
dBUG>
RS-232 TerminalOr PC
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2.2 Installation and SetupThe following sections describe all the steps needed to prepare the board for operation.Please read the following sections carefully before using the board. When you are preparingthe board for the first time, be sure to check that all jumpers are in the default locations.Default jumper markings are documented on the master jumper table and printed on theunderside of the board. After the board is functional in its default mode, the Ethernetinterface may be used by following the instructions provided in Appendix A.
2.2.1 Unpacking
Unpack the computer board from its shipping box. Save the box for storing or reshipping.Refer to the following list and verify that all the items are present. You should havereceived:
• M523xEVB Single Board Computer
• M523xEVB User's Manual (this document)
• One RS232 communication cable
• One BDM (Background Debug Mode) “wiggler” cable
• MCF5235RM ColdFire Integrated Microprocessor Reference Manual
• ColdFire® Programmers Reference Manual
• A selection of Third Party Developer Tools and Literature
NOTEAvoid touching the MOS devices. Static discharge can and willdamage these devices.
Once you have verified that all the items are present, remove the board from its protectivejacket and anti-static bag. Check the board for any visible damage. Ensure that there are nobroken, damaged, or missing parts. If you have not received all the items listed above orthey are damaged, please contact Freescale Semiconductor immediately. For contactdetails, please see the front of this manual.
2.2.2 Preparing the Board for Use
The board, as shipped, is ready to be connected to a terminal and power supply without anyneed for modification. Figure 2-5 shows the position of the jumpers and connectors.
2.2.3 Providing Power to the Board
The EVB requires an external supply voltage of 7–14 V DC, minimum 1 Amp. This isregulated on board using three switching voltage regulators to provide the necessary EVBvoltages of 5V, 3.3V and 1.5V. There are two different power supply input connectors on
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the EVB. Connector P2 is a 2.1mm power jack (Figure 2-2), P3 a lever actuated connector(Figure 2-3).
Figure 2-2. 2.1mm Power Connector
Figure 2-3. 2-Lever Power Connector
2.2.4 Power Switch (SW4)
Slide switch SW4 can be used to isolate the power supply input from the EVB voltageregulators if required.
Moving the slide switch to the left (towards connector P3) will turn the EVB ON.
Moving the slide switch to the right (away from connector P3) will turn the EVB OFF.
2.2.5 Power Status LEDs and Fuse
When power is applied to the EVB, green power LEDs adjacent to the voltage regulatorsshow the presence of the supply voltage as follows:
V+(7-14V)
GND
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If no LEDs are illuminated when the power is applied to the EVB, it is possible that eitherpower switch SW4 is in the “OFF” position or that the fuse F1 has blown. This can occurif power is applied to the EVB in reverse-bias where a protection diode ensures that the fuseblows rather than causing damage to the EVB. Replace F1 with a 20mm 1A fast blow fuse.
2.2.6 Selecting Terminal Baud Rate
The serial channel UART0 of the MCF5235 is used for serial communication and has abuilt in timer. This timer is used by the dBUG ROM monitor to generate the baud rate usedto communicate with a serial terminal. A number of baud rates can be programmed. Onpower-up or manual RESET, the dBUG ROM monitor firmware configures the channel for19200 baud. Once the dBUG ROM monitor is running, a SET command may be issued toselect any baud rate supported by the ROM monitor.
2.2.7 The Terminal Character Format
The character format of the communication channel is fixed at power-up or RESET. Thedefault character format is 8 bits per character, no parity and one stop bit with no flowcontrol. It is necessary to ensure that the terminal or PC is set to this format.
2.2.8 Connecting the Terminal
The board is now ready to be connected to a PC/terminal. Use the RS-232 serial cable toconnect the PC/terminal to the M523xEVB PCB. The cable has a 9-pin female D-subterminal connector at one end and a 9-pin male D-sub connector at the other end. Connectthe 9-pin male connector to connector P4 on the M523xEVB board. Connect the 9-pinfemale connector to one of the available serial communication channels normally referredto as COM1 (COM2, etc.) on the PC running terminal emulation software. The connectoron the PC/terminal may be either male 25-pin or 9-pin. It may be necessary to obtain a25pin-to-9pin adapter to make this connection. If an adapter is required, refer to Figure 2-4.
2.2.9 Using a Personal Computer as a Terminal
A personal computer may be used as a terminal provided a terminal emulation softwarepackage is available. Examples of this software are PROCOMM, KERMIT, QMODEM,
Table 2-1. Power LEDs
LED Function
D17 Indicates that the +5V regulator is working correctly
D14 Indicates that the +3.3V regulator is working correctly
D21 Indicates that the +1.5V regulator is working correctly
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Windows 95/98/2000/XP Hyper Terminal or similar packages. The board should then beconnected as described in Section 2.2.8, “Connecting the Terminal.”
Once the connection to the PC is made, power may be applied to the PC and the terminalemulation software can be run. In terminal mode, it is necessary to select the baud rate andcharacter format for the channel. Most terminal emulation software packages provide acommand known as "Alt-p" (press the p key while pressing the Alt key) to choose the baudrate and character format. The character format should be 8 bits, no parity, one stop bit. (seesection 1.9.5 The Terminal Character Format.) The baud rate should be set to 19200. Powercan now be applied to the board.
Figure 2-4. Pin Assignment for Female (Terminal) Connector
Pin assignments are as follows:
Figure 2-5 on the next page shows the jumper locations for the board.
Table 2-2. Pin Assignment for Female (Terminal) Connector
DB9 Pin Function
1 Data Carrier Detect, Output (shorted to pins 4 and 6)
2 Receive Data, Output from board (receive refers to terminal side)
3 Transmit Data, Input to board (transmit refers to terminal side)
4 Data Terminal Ready, Input (shorted to pin 1 and 6)
5 Signal Ground
6 Data Set Ready, Output (shorted to pins 1 and 4)
7 Request to Send, Input
8 Clear to send, Output
9 Not connected
1
69
5
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Figure 2-5. Jumper Locations
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System Power-up and Initial Operation
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2.3 System Power-up and Initial OperationWhen all of the cables are connected to the board, power may be applied. The dBUG ROMMonitor initializes the board and then displays a power-up message on the terminal, whichincludes the amount of memory present on the board.
Hard ResetDRAM Size: 16M
Copyright 1995-2004 Motorola, Inc. All Rights Reserved.ColdFire MCF523x EVS Firmware v2e.1a.xx (Build XXX on XXX XX 20XXxx:xx:xx)
Enter ’help’ for help.
dBUG>
The board is now ready for operation under the control of the debugger as described inChapter 2. If you do not get the above response, perform the following checks:
1. Make sure that the power supply is properly configured for polarity, voltage leveland current capability (~1A) and is connected to the board.
2. Check that the terminal and board are set for the same character format and baud.
3. Press the RESET button to insure that the board has been initialized properly.
If you still are not receiving the proper response, your board may have been damaged.Contact Freescale Semiconductor for further instructions, please see the beginning of thismanual for contact details.
2.4 Using The BDM PortThe MCF5235 microprocessor has a built in debug module referred to as BDM(background debug module). In order to use BDM, simply connect the 26-pin debugconnector on the board, J1, to the P&E BDM wiggler cable provided in the kit. No specialsetting is needed. Refer to the ColdFire® User's Manual BDM Section for additionalinstructions.
NOTEBDM functionality and use is supported via third partydeveloper software tools. Details may be found on theCD-ROM included in this kit.
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Chapter 3 Using the Monitor/Debug FirmwareThe M523xEVB single board computer has a resident firmware package that provides aself-contained programming and operating environment. The firmware, named dBUG,provides the user with monitor/debug interface, inline assembler and disassembly, programdownload, register and memory manipulation, and I/O control functions. This chapter is ahow-to-use description of the dBUG package, including the user interface and commandstructure.
3.1 What Is dBUG?dBUG is a traditional ROM monitor/debugger that offers a comfortable and intuitivecommand line interface that can be used to download and execute code. It contains all theprimary features needed in a debugger to create a useful debugging environment.
The firmware provides a self-contained programming and operating environment. dBUGinteracts with the user through pre-defined commands that are entered via the terminal.These commands are defined in Section 3.4, “Commands”.
The user interface to dBUG is the command line. A number of features have beenimplemented to achieve an easy and intuitive command line interface.
dBUG assumes that an 80x24 character dumb-terminal is utilized to connect to thedebugger. For serial communications, dBUG requires eight data bits, no parity, and one stopbit (8-N-1) with no flow control. The default baud rate is 19200 but can be changed afterpower-up.
The command line prompt is “dBUG> ”. Any dBUG command may be entered from thisprompt. dBUG does not allow command lines to exceed 80 characters. Wherever possible,dBUG displays data in 80 columns or less. dBUG echoes each character as it is typed,eliminating the need for any “local echo” on the terminal side.
In general, dBUG is not case sensitive. Commands may be entered either in upper or lowercase, depending upon the user’s equipment and preference. Only symbol names require thatthe exact case be used.
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What Is dBUG?
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Most commands can be recognized by using an abbreviated name. For instance, entering“h” is the same as entering “help”. Thus, it is not necessary to type the entire commandname.
The commands DI, GO, MD, STEP and TRACE are used repeatedly when debugging.dBUG recognizes this and allows for repeated execution of these commands with minimaltyping. After a command is entered, simply press <RETURN> or <ENTER> to invoke thecommand again. The command is executed as if no command line parameters wereprovided.
An additional function called the "System Call" allows the user program to utilize variousroutines within dBUG. The System Call is discussed at the end of this chapter.
The operational mode of dBUG is demonstrated in Figure 3-1. After the systeminitialization, the board waits for a command-line input from the user terminal. When aproper command is entered, the operation continues in one of the two basic modes. If thecommand causes execution of the user program, the dBUG firmware may or may not bere-entered, at the discretion of the user’s program. For the alternate case, the command willbe executed under control of the dBUG firmware, and after command completion, thesystem returns to command entry mode.
During command execution, additional user input may be required depending on thecommand function.
For commands that accept an optional <width> to modify the memory access size, the validvalues are:
• B 8-bit (byte) access
• W 16-bit (word) access
• L 32-bit (long) access
When no <width> option is provided, the default width is.W, 16-bit.
The core ColdFire® register set is maintained by dBUG. These are listed below:
• A0-A7
• D0-D7
• PC
• SR
All control registers on ColdFire® are not readable by the supervisor-programming model,and thus not accessible via dBUG. User code may change these registers, but caution mustbe exercised as changes may render dBUG inoperable.
A reference to “SP” (stack pointer) actually refers to general purpose address registerseven, “A7.”
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Operational Procedure
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3.2 Operational ProcedureSystem power-up and initial operation are described in detail in Chapter 2. This informationis repeated here for convenience and to prevent possible damage.
3.2.1 System Power-up• Be sure the power supply is connected properly prior to power-up.
• Make sure the terminal is connected to TERMINAL (P4) connector.
• Turn power on to the board.
Figure 3-1 shows the dBUG operational mode.
Figure 3-1. Flow Diagram of dBUG Operational Mode
COMMAND LINEINPUT FROM TERMINAL
DOES COMMAND LINECAUSE USER PROGRAM
EXECUTION
NO
YES
YES
EXECUTE COMMANDFUNCTION
INITIALIZE
NO
JUMP TO USERPROGRAM AND
BEGIN EXECUTION
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3.2.2 System Initialization
After the EVB is powered-up and initialized, the terminal will display:Hard Reset
DRAM Size: 16M
ColdFire MCF5235 on the M523xEVB
Firmware vXX.XX.XX (Build X on XXXX)
Copyright 1995-2004 Motorola, Inc. All Rights Reserved.
Enter ’help’ for help.
dBUG>
Other means can be used to re-initialize the M523xEVB firmware. These means arediscussed in the following paragraphs.
3.2.2.1 External RESET Button
External RESET (SW6) is the red button. Depressing this button causes all processes toterminate, resets the MCF5235 processor and board logic and restarts the dBUG firmware.Pressing the RESET button would be the appropriate action if all else fails.
3.2.2.2 ABORT Button
ABORT (SW5) is the button located next to the RESET button. The abort function causesan interrupt of the present processing (a level 7 interrupt on MCF5235) and gives controlto the dBUG firmware. This action differs from RESET in that no processor register ormemory contents are changed, the processor and peripherals are not reset, and dBUG is notrestarted. Also, in response to depressing the ABORT button, the contents of the MCF5235core internal registers are displayed.
The abort function is most appropriate when software is being debugged. The user caninterrupt the processor without destroying the present state of the system. This isaccomplished by forcing a non-maskable interrupt that will call a dBUG routine that willsave the current state of the registers to shadow registers in the monitor for display to theuser. The user will be returned to the ROM monitor prompt after exception handling.
3.2.2.3 Software Reset Command
dBUG does have a command that causes the dBUG to restart as if a hardware reset wasinvoked. The command is “RESET”.
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Command Line Usage
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3.3 Command Line UsageThe user interface to dBUG is the command line. A number of features have beenimplemented to achieve an easy and intuitive command line interface.
dBUG assumes that an 80x24 ASCII character dumb terminal is used to connect to thedebugger. For serial communications, dBUG requires eight data bits, no parity, and one stopbit (8-N-1). The baud rate default is 19200 bps — a speed commonly available fromworkstations, personal computers and dedicated terminals.
The command line prompt is: dBUG>
Any dBUG command may be entered from this prompt. dBUG does not allow commandlines to exceed 80 characters. Wherever possible, dBUG displays data in 80 columns orless. dBUG echoes each character as it is typed, eliminating the need for any local echo onthe terminal side.
The <Backspace> and <Delete> keys are recognized as rub-out keys for correctingtypographical mistakes.
Command lines may be recalled using the <Control> U, <Control> D and <Control> R keysequences. <Control> U and <Control> D cycle up and down through previous commandlines. <Control> R recalls and executes the last command line.
In general, dBUG is not case-sensitive. Commands may be entered either in uppercase orlowercase, depending upon the user’s equipment and preference. Only symbol namesrequire that the exact case be used.
Most commands can be recognized by using an abbreviated name. For instance, entering his the same as entering help. Thus it is not necessary to type the entire command name.
The commands DI, GO, MD, STEP and TRACE are used repeatedly when debugging.dBUG recognizes this and allows for repeated execution of these commands with minimaltyping. After a command is entered, press the <Return> or <Enter> key to invoke thecommand again. The command is executed as if no command line parameters wereprovided.
3.4 CommandsThis section lists the commands that are available with all versions of dBUG. Some boardor CPU combinations may use additional commands not listed below.
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Commands
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Table 3-1. dBUG Command Summary
Mnemonic Syntax Description
ASM asm <<addr> stmt> Assemble
BC bc addr1 addr2 length Block Compare
BF bf <width> begin end data <inc> Block Fill
BM bm begin end dest Block Move
BR br addr <-r> <-c count> <-t trigger> Breakpoint
BS bs <width> begin end data Block Search
DC dc value Data Convert
DI di<addr> Disassemble
DL dl <offset> Download Serial
DLDBUG dldbug Download dBUG
DN dn <-c> <-e> <-i> <-s <-o offset>> <filename> Download Network
FL fl erase addr bytesfl write dest src bytes
Flash Utilities
GO go <addr> Execute
GT gt addr Execute To
HELP help <command> Help
IRD ird <module.register> Internal Register Display
IRM irm module.register data Internal Register Modify
LR lr<width> addr Loop Read
LW lw<width> addr data Loop Write
MD md<width> <begin> <end> Memory Display
MM mm<width> addr <data> Memory Modify
MMAP mmap Memory Map Display
RD rd <reg> Register Display
RM rm reg data Register Modify
RESET reset Reset
SD sd Stack Dump
SET set <option value> Set Configurations
SHOW show <option> Show Configurations
STEP step Step (Over)
SYMBOL symbol <symb> <-a symb value> <-r symb> -C|l|s> Symbol Management
TRACE trace <num> Trace (Into)
UP up begin end filename Upload Memory to File
VERSION version Show Version
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ASM AssemblerUsage: ASM <<addr> stmt>
The ASM command is a primitive assembler. The <stmt> is assembled and the resultingcode placed at <addr>. This command has an interactive and non-interactive mode ofoperation.
The value for address <addr> may be an absolute address specified as a hexadecimal value,or a symbol name. The value for stmt must be valid assembler mnemonics for the CPU.
For the interactive mode, the user enters the command and the optional <addr>. If theaddress is not specified, then the last address is used. The memory contents at the addressare disassembled, and the user prompted for the new assembly. If valid, the new assemblyis placed into memory, and the address incremented accordingly. If the assembly is notvalid, then memory is not modified, and an error message produced. In either case, memoryis disassembled and the process repeats.
The user may press the <Enter> or <Return> key to accept the current memory contents andskip to the next instruction, or a enter period to quit the interactive mode.
In the non-interactive mode, the user specifies the address and the assembly statement onthe command line. The statement is then assembled, and if valid, placed into memory,otherwise an error message is produced.
Examples:
To place a NOP instruction at address 0x00010000, the command is:asm 10000 nop
To interactively assemble memory at address 0x00400000, the command is:asm 400000
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BC Block CompareUsage:BC addr1 addr2 length
The BC command compares two contiguous blocks of memory on a byte by byte basis. Thefirst block starts at address addr1 and the second starts at address addr2, both of lengthbytes.
If the blocks are not identical, the address of the first mismatch is displayed. The value foraddresses addr1 and addr2 may be an absolute address specified as a hexadecimal value ora symbol name. The value for length may be a symbol name or a number convertedaccording to the user defined radix (hexadecimal by default).
Example:
To verify that the data starting at 0x20000 and ending at 0x30000 is identical to the datastarting at 0x80000, the command is:
bc 20000 80000 10000
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BF Block FillUsage:BF<width> begin end data <inc>
The BF command fills a contiguous block of memory starting at address begin, stopping ataddress end, with the value data. <Width> modifies the size of the data that is written. If no<width> is specified, the default of word sized data is used.
The value for addresses begin and end may be an absolute address specified as ahexadecimal value, or a symbol name. The value for data may be a symbol name, or anumber converted according to the user-defined radix, normally hexadecimal.
The optional value <inc> can be used to increment (or decrement) the data value during thefill.
This command first aligns the starting address for the data access size, and then incrementsthe address accordingly during the operation. Thus, for the duration of the operation, thiscommand performs properly-aligned memory accesses.
Examples:
To fill a memory block starting at 0x00020000 and ending at 0x00040000 with the value0x1234, the command is:
bf 20000 40000 1234
To fill a block of memory starting at 0x00020000 and ending at 0x0004000 with a bytevalue of 0xAB, the command is:
bf.b 20000 40000 AB
To zero out the BSS section of the target code (defined by the symbols bss_start andbss_end), the command is:
bf bss_start bss_end 0
To fill a block of memory starting at 0x00020000 and ending at 0x00040000 with data thatincrements by 2 for each <width>, the command is:
bf 20000 40000 0 2
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BM Block MoveUsage:BM begin end dest
The BM command moves a contiguous block of memory starting at address begin andstopping at address end to the new address dest. The BM command copies memory as aseries of bytes, and does not alter the original block.
The values for addresses begin, end, and dest may be absolute addresses specified ashexadecimal values, or symbol names. If the destination address overlaps the block definedby begin and end, an error message is produced and the command exits.
Examples:
To copy a block of memory starting at 0x00040000 and ending at 0x00080000 to thelocation 0x00200000, the command is:
bm 40000 80000 200000
To copy the target code’s data section (defined by the symbols data_start and data_end) to0x00200000, the command is:
bm data_start data_end 200000
NOTERefer to “upuser” command for copying code/data into Flashmemory.
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BR BreakpointsUsage:BR addr <-r> <-c count> <-t trigger>
The BR command inserts or removes breakpoints at address addr. The value for addr maybe an absolute address specified as a hexadecimal value, or a symbol name. Count andtrigger are numbers converted according to the user-defined radix, normally hexadecimal.
If no argument is provided to the BR command, a listing of all defined breakpoints isdisplayed.
The -r option to the BR command removes a breakpoint defined at address addr. If noaddress is specified in conjunction with the -r option, then all breakpoints are removed.
Each time a breakpoint is encountered during the execution of target code, its count valueis incremented by one. By default, the initial count value for a breakpoint is zero, but the -coption allows setting the initial count for the breakpoint.
Each time a breakpoint is encountered during the execution of target code, the count valueis compared against the trigger value. If the count value is equal to or greater than the triggervalue, a breakpoint is encountered and control returned to dBUG. By default, the initialtrigger value for a breakpoint is one, but the -t option allows setting the initial trigger forthe breakpoint.
If no address is specified in conjunction with the -c or -t options, then all breakpoints areinitialized to the values specified by the -c or -t option.
Examples:
To set a breakpoint at the C function main() (symbol _main; see “symbol” command), thecommand is:
br _main
When the target code is executed and the processor reaches main(), control will be returnedto dBUG.
To set a breakpoint at the C function bench() and set its trigger value to 3, the command is:br _bench -t 3
When the target code is executed, the processor must attempt to execute the functionbench() a third time before returning control back to dBUG.
To remove all breakpoints, the command is:br -r
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BS Block SearchUsage:BS<width> begin end data
The BS command searches a contiguous block of memory starting at address begin,stopping at address end, for the value data. <Width> modifies the size of the data that iscompared during the search. If no <width> is specified, the default of word sized data isused.
The values for addresses begin and end may be absolute addresses specified as hexadecimalvalues, or symbol names. The value for data may be a symbol name or a number convertedaccording to the user-defined radix, normally hexadecimal.
This command first aligns the starting address for the data access size, and then incrementsthe address accordingly during the operation. Thus, for the duration of the operation, thiscommand performs properly-aligned memory accesses.
Examples:
To search for the 16-bit value 0x1234 in the memory block starting at 0x00040000 andending at 0x00080000:
bs 40000 80000 1234
This reads the 16-bit word located at 0x00040000 and compares it against the 16-bit value0x1234. If no match is found, then the address is incremented to 0x00040002 and the next16-bit value is read and compared.
To search for the 32-bit value 0xABCD in the memory block starting at 0x00040000 andending at 0x00080000:
bs.l 40000 80000 ABCD
This reads the 32-bit word located at 0x00040000 and compares it against the 32-bit value0x0000ABCD. If no match is found, then the address is incremented to 0x00040004 andthe next 32-bit value is read and compared.
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DC Data ConversionUsage:DC data
The DC command displays the hexadecimal or decimal value data in hexadecimal, binary,and decimal notation.
The value for data may be a symbol name or an absolute value. If an absolute value passedinto the DC command is prefixed by ‘0x’, then data is interpreted as a hexadecimal value.Otherwise data is interpreted as a decimal value.
All values are treated as 32-bit quantities.
Examples:
To display the decimal and binary equivalent of 0x1234, the command is:dc 0x1234
To display the hexadecimal and binary equivalent of 1234, the command is:dc 1234
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DI DisassembleUsage:DI <addr>
The DI command disassembles target code pointed to by addr. The value for addr may bean absolute address specified as a hexadecimal value, or a symbol name.
Wherever possible, the disassembler will use information from the symbol table to producea more meaningful disassembly. This is especially useful for branch target addresses andsubroutine calls.
The DI command attempts to track the address of the last disassembled opcode. If noaddress is provided to the DI command, then the DI command uses the address of the lastopcode that was disassembled.
The DI command is repeatable.
Examples:
To disassemble code that starts at 0x00040000, the command is:di 40000
To disassemble code of the C function main(), the command is:di _main
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DL Download ConsoleUsage:DL <offset>
The DL command performs an S-record download of data obtained from the console,typically a serial port. The value for offset is converted according to the user-defined radix,normally hexadecimal. Please reference the ColdFire Microprocessor FamilyProgrammer’s Reference Manual for details on the S-Record format.
If offset is provided, then the destination address of each S-record is adjusted by offset.
The DL command checks the destination download address for validity. If the destinationis an address outside the defined user space, then an error message is displayed anddownloading aborted.
If the S-record file contains the entry point address, then the program counter is set to reflectthis address.
Examples:
To download an S-record file through the serial port, the command is:dl
To download an S-record file through the serial port, and add an offset to the destinationaddress of 0x40, the command is:
dl 0x40
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DLDBUG Download dBUGUsage:DL <offset>
The DLDBUG command is used to update the dBUG image in Flash. It erases the Flashsectors containing the dBUG image, downloads a new dBUG image in S-record formatobtained from the console, and programs the new dBUG image into Flash.
When the DLDBUG command is issued, dBUG will prompt the user for verification beforeany actions are taken. If the command is affirmed, the Flash is erased and the user isprompted to begin sending the new dBUG S-record file. The file should be sent as a textfile with no special transfer protocol.
Use this command with extreme caution, as any error can render dBUG useless!
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Commands
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DN Download NetworkUsage:DN <-c> <-e> <-i> <-s> <-o offset> <filename>
The DN command downloads code from the network. The DN command handle fileswhich are either S-record, COFF, ELF or Image formats. The DN command uses TrivialFile Transfer Protocol (TFTP) to transfer files from a network host.
In general, the type of file to be downloaded and the name of the file must be specified tothe DN command. The -c option indicates a COFF download, the -e option indicates anELF download, the -i option indicates an Image download, and the -s indicates an S-recorddownload. The -o option works only in conjunction with the -s option to indicate anoptional offset for S-record download. The filename is passed directly to the TFTP serverand therefore must be a valid filename on the server.
If neither of the -c, -e, -i, -s or filename options are specified, then a default filename andfiletype will be used. Default filename and filetype parameters are manipulated using theSET and SHOW commands.
The DN command checks the destination download address for validity. If the destinationis an address outside the defined user space, then an error message is displayed anddownloading aborted.
For ELF and COFF files which contain symbolic debug information, the symbol tables areextracted from the file during download and used by dBUG. Only global symbols are keptin dBUG. The dBUG symbol table is not cleared prior to downloading, so it is the user’sresponsibility to clear the symbol table as necessary prior to downloading.
If an entry point address is specified in the S-record, COFF or ELF file, the program counteris set accordingly.
Examples:
To download an S-record file with the name “srec.out”, the command is:dn -s srec.out
To download a COFF file with the name “coff.out”, the command is:dn -c coff.out
To download a file using the default filetype with the name “bench.out”, the command is:dn bench.out
To download a file using the default filename and filetype, the command is:dn
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FL Flash UtilitiesInfo Usage: FL
Erase Usage: FL erase addr bytes
Write Usage: FL write dest src bytes
The FL command provides a set of flash utilities that will display information about theFlash devices on the EVB, erase a specified range of Flash, or erase and program a specifiedrange of Flash.
When issued with no parameters, the FL command will display usage information as wellas device specific information for the Flash devices available. This information includessize, address range, protected range, access size, and sector boundaries.
When the erase command is given, the FL command will attempt to erase the number ofbytes specified on the command line beginning at addr. If this range doesn’t start and endon Flash sector boundaries, the range will be adjusted automatically and the user will beprompted for verification before proceeding.
When the write command is given, the FL command will program the number of bytesspecified from src to dest. An erase of this region will first be attempted. As with the erasecommand, if the Flash range to be programmed doesn’t start and end on Flash sectorboundaries, the range will be adjusted and the user will be prompted for verification beforethe erase is performed. The specified range is also checked to insure that the entiredestination range is valid within the same Flash device and that the src and dest are notwithin the same device.
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GO ExecuteUsage:GO <addr>
The GO command executes target code starting at address addr. The value for addr may bean absolute address specified as a hexadecimal value, or a symbol name.
If no argument is provided, the GO command begins executing instructions at the currentprogram counter.
When the GO command is executed, all user-defined breakpoints are inserted into the targetcode, and the context is switched to the target program. Control is only regained when thetarget code encounters a breakpoint, illegal instruction, trap #15 exception, or otherexception which causes control to be handed back to dBUG.
The GO command is repeatable.
Examples:
To execute code at the current program counter, the command is:go
To execute code at the C function main(), the command is:go _main
To execute code at the address 0x00040000, the command is:go 40000
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GT Execute ToUsage:GT addr
The GT command inserts a temporary breakpoint at addr and then executes target codestarting at the current program counter. The value for addr may be an absolute addressspecified as a hexadecimal value, or a symbol name.
When the GT command is executed, all breakpoints are inserted into the target code, andthe context is switched to the target program. Control is only regained when the target codeencounters a breakpoint, illegal instruction, or other exception which causes control to behanded back to dBUG.
Examples:
To execute code up to the C function bench(), the command is:gt _bench
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IRD Internal Register DisplayUsage:IRD <module.register>
This command displays the internal registers of different modules inside the MCF5235. Inthe command line, module refers to the module name where the register is located andregister refers to the specific register to display.
The registers are organized according to the module to which they belong. Use the IRDcommand without any parameters to get a list of all the valid modules. Refer to theMCF5235 user’s manual for more information on these modules and the registers theycontain.
Example:ird sim.rsr
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IRM Internal Register ModifyUsage:IRM module.register data
This command modifies the contents of the internal registers of different modules insidethe MCF5235. In the command line, module refers to the module name where the registeris located and register refers to the specific register to modify. The data parameter specifiesthe new value to be written into the register.
.
Example:
To modify the TMR register of the first Timer module to the value 0x0021, the command is:irm timer1.tmr 0021
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HELP HelpUsage:HELP <command>
The HELP command displays a brief syntax of the commands available within dBUG. Inaddition, the address of where user code may start is given. If command is provided, thena brief listing of the syntax of the specified command is displayed.
Examples:
To obtain a listing of all the commands available within dBUG, the command is:help
To obtain help on the breakpoint command, the command is:
help br
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LR Loop ReadUsage:LR<width> addr
The LR command continually reads the data at addr until a key is pressed. The optional<width> specifies the size of the data to be read. If no <width> is specified, the commanddefaults to reading word sized data.
Example:
To continually read the longword data from address 0x20000, the command is:lr.l 20000
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LW Loop WriteUsage:LW<width> addr data
The LW command continually writes data to addr. The optional width specifies the size ofthe access to memory. The default access size is a word.
Examples:
To continually write the longword data 0x12345678 to address 0x20000, the command is:lw.l 20000 12345678
Note that the following command writes 0x78 into memory:lw.b 20000 12345678
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MD Memory DisplayUsage:MD<width> <begin> <end>
The MD command displays a contiguous block of memory starting at address begin andstopping at address end. The values for addresses begin and end may be absolute addressesspecified as hexadecimal values, or symbol names. Width modifies the size of the data thatis displayed. If no <width> is specified, the default of word sized data is used.
Memory display starts at the address begin. If no beginning address is provided, the MDcommand uses the last address that was displayed. If no ending address is provided, thenMD will display memory up to an address that is 128 beyond the starting address.
This command first aligns the starting address for the data access size, and then incrementsthe address accordingly during the operation. Thus, for the duration of the operation, thiscommand performs properly-aligned memory accesses.
Examples:
To display memory at address 0x00400000, the command is:md 400000
To display memory in the data section (defined by the symbols data_start and data_end),the command is:
md data_start
To display a range of bytes from 0x00040000 to 0x00050000, the command is:md.b 40000 50000
To display a range of 32-bit values starting at 0x00040000 and ending at 0x00050000:md.l 40000 50000
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MM Memory ModifyUsage:MM<width> addr <data>
The MM command modifies memory at the address addr. The value for addr may be anabsolute address specified as a hexadecimal value, or a symbol name. Width specifies thesize of the data that is modified. If no <width> is specified, the default of word sized datais used. The value for data may be a symbol name, or a number converted according to theuser-defined radix, normally hexadecimal.
If a value for data is provided, then the MM command immediately sets the contents of addrto data. If no value for data is provided, then the MM command enters into a loop. The loopobtains a value for data, sets the contents of the current address to data, increments theaddress according to the data size, and repeats. The loop terminates when an invalid entryfor the data value is entered, i.e., a period.
This command first aligns the starting address for the data access size, and then incrementsthe address accordingly during the operation. Thus, for the duration of the operation, thiscommand performs properly-aligned memory accesses.
Examples:
To set the byte at location 0x00010000 to be 0xFF, the command is:mm.b 10000 FF
To interactively modify memory beginning at 0x00010000, the command is:mm 10000
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MMAP Memory Map DisplayUsage:mmap
This command displays the memory map information for the M523xEVB evaluation board.The information displayed includes the type of memory, the start and end address of thememory, and the port size of the memory. The display also includes information on how theChip-selects are used on the board and which regions of memory are reserved for dBUGuse (protected).
Here is an example of the output from this command:
Type Start End Port Size
---------------------------------------------------
SDRAM 0x00000000 0x00FFFFFF 32-bit
SRAM (Int) 0x20000000 0x2000FFFF 32-bit
ASRAM (Ext) 0x30000000 0x3007FFFF 32-bit
IPSBAR 0x40000000 0x7FFFFFFF 32-bit
Flash (Ext) 0xFFE00000 0xFFFFFFFF 16-bit
Protected Start End
----------------------------------------
dBUG Code 0xFFE00000 0xFFE3FFFF
dBUG Data 0x00000000 0x0000FFFF
Chip Selects
----------------
CS0 Ext Flash
CS1 Ext ASRAM
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RD Register DisplayUsage:RD <reg>
The RD command displays the register set of the target. If no argument for reg is provided,then all registers are displayed. Otherwise, the value for reg is displayed.
dBUG preserves the registers by storing a copy of the register set in a buffer. The RDcommand displays register values from the register buffer.
Examples:
To display all the registers and their values, the command is:
rd
To display only the program counter:
rd pc
Here is an example of the output from this command:PC: 00000000 SR: 2000 [t.Sm.000...xnzvc]
An: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 01000000
Dn: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
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RM Register ModifyUsage:RM reg data
The RM command modifies the contents of the register reg to data. The value for reg isthe name of the register, and the value for data may be a symbol name, or it is convertedaccording to the user-defined radix, normally hexadecimal.
dBUG preserves the registers by storing a copy of the register set in a buffer. The RMcommand updates the copy of the register in the buffer. The actual value will not be writtento the register until target code is executed.
Examples:
To change register D0 on MC68000 and ColdFire to contain the value 0x1234, thecommand is:
rm D0 1234
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Commands
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RESET Reset the Board and dBUGUsage:RESET
The RESET command resets the board and dBUG to their initial power-on states.
The RESET command executes the same sequence of code that occurs at power-on. If theRESET command fails to reset the board adequately, cycle the power or press the resetbutton.
Examples:
To reset the board and clear the dBUG data structures, the command is:reset
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SD Stack DumpUsage:SD
The SD command displays a back trace of stack frames. This command is useful after someuser code has executed that creates stack frames (i.e. nested function calls). After control isreturned to dBUG, the SD command will decode the stack frames and display a trace of thefunction calls.
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Commands
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SET Set ConfigurationsUsage: SET <option value>
The SET command allows the setting of user-configurable options within dBUG. With noarguments, SET displays the options and values available. The SHOW command displaysthe settings in the appropriate format. The standard set of options is listed below.
baud - This is the baud rate for the first serial port on the board. All communicationsbetween dBUG and the user occur using either 9600 or 19200 bps, eight data bits, no parity,and one stop bit, 8-N-1, with no flow control.
base - This is the default radix for use in converting a number from its ASCII textrepresentation to the internal quantity used by dBUG. The default is hexadecimal (base 16),and other choices are binary (base 2), octal (base 8), and decimal (base 10).
client - This is the network Internet Protocol (IP) address of the board. For networkcommunications, the client IP is required to be set to a unique value, usually assigned byyour local network administrator.
server - This is the network IP address of the machine which contains files accessible viaTFTP. Your local network administrator will have this information and can assist inproperly configuring a TFTP server if one does not exist.
gateway - This is the network IP address of the gateway for your local subnetwork. If theclient IP address and server IP address are not on the same subnetwork, then this optionmust be properly set. Your local network administrator will have this information.
netmask - This is the network address mask to determine if use of a gateway is required.This field must be properly set. Your local network administrator will have thisinformation.
filename - This is the default filename to be used for network download if no name isprovided to the DN command.
filetype - This is the default filetype to be used for network download if no type is providedto the DN command. Valid values are: “srecord”, “coff”, and “elf”.
mac - This is the ethernet Media Access Control (MAC) address (a.k.a hardware address)for the evaluation board. This should be set to a unique value, and the most significantnibble should always be even.
Examples: To set the baud rate of the board to be 19200, the command is:set baud 19200
NOTESee the SHOW command for a display containing the correctformatting of these options.
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SHOW Show ConfigurationsUsage: SHOW <option>
The SHOW command displays the settings of the user-configurable options within dBUG.When no option is provided, SHOW displays all options and values.
Examples:
To display all options and settings, the command is:show
To display the current baud rate of the board, the command is:show baud
Here is an example of the output from a show command:dBUG> show
base: 16
baud: 19200
server: 0.0.0.0
client: 0.0.0.0
gateway: 0.0.0.0
netmask: 255.255.255.0
filename: test.s19
filetype: S-Record
ethaddr: 00:CF:52:82:CF:01
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Commands
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STEP Step OverUsage:STEP
The STEP command can be used to “step over” a subroutine call, rather than tracing everyinstruction in the subroutine. The ST command sets a temporary breakpoint one instructionbeyond the current program counter and then executes the target code.
The STEP command can be used to “step over” BSR and JSR instructions.
The STEP command will work for other instructions as well, but note that if the STEPcommand is used with an instruction that will not return, i.e. BRA, then the temporarybreakpoint may never be encountered and dBUG may never regain control.
Examples:
To pass over a subroutine call, the command is:step
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SYMBOL Symbol Name ManagementUsage:SYMBOL <symb> <-a symb value> <-r symb> <-c|l|s>
The SYMBOL command adds or removes symbol names from the symbol table. If only asymbol name is provided to the SYMBOL command, then the symbol table is searched fora match on the symbol name and its information displayed.
The -a option adds a symbol name and its value into the symbol table. The -r optionremoves a symbol name from the table.
The -c option clears the entire symbol table, the -l option lists the contents of the symboltable, and the -s option displays usage information for the symbol table.
Symbol names contained in the symbol table are truncated to 31 characters. Any symboltable lookups, either by the SYMBOL command or by the disassembler, will only use thefirst 31 characters. Symbol names are case-sensitive.
Symbols can also be added to the symbol table via in-line assembly labels and ethernetdownloads of ELF formatted files.
Examples:
To define the symbol “main” to have the value 0x00040000, the command is:symbol -a main 40000
To remove the symbol “junk” from the table, the command is:symbol -r junk
To see how full the symbol table is, the command is:symbol -s
To display the symbol table, the command is:symbol -l
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TRACE Trace IntoUsage:TRACE <num>
The TRACE command allows single-instruction execution. If num is provided, then numinstructions are executed before control is handed back to dBUG. The value for num is adecimal number.
The TRACE command sets bits in the processors’ supervisor registers to achievesingle-instruction execution, and the target code executed. Control returns to dBUG after asingle-instruction execution of the target code.
This command is repeatable.
Examples:
To trace one instruction at the program counter, the command is:tr
To trace 20 instructions from the program counter, the command is:tr 20
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UP Upload DataUsage:UP begin end filename
The UP command uploads the data from a memory region (specified by begin and end) toa file (specified by filename) over the network. The file created contains the raw binary datafrom the specified memory region. The UP command uses the Trivial File TransferProtocol (TFTP) to transfer files to a network host.
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Commands
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VERSION Display dBUG VersionUsage:VERSION
The VERSION command displays the version information for dBUG. The dBUG version,build number and build date are all given.
The version number is separated by a decimal, for example, “v 2b.1c.1a”.
The version date is the day and time at which the entire dBUG monitor was compiled andbuilt.
Examples:
To display the version of the dBUG monitor, the command is:version
In this example, v 2b . 1c . 1a
{ { {
dBUG commonmajor and minor revision
CPU major and minor revision
board majorand minor revision
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TRAP #15 Functions
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3.5 TRAP #15 FunctionsAn additional utility within the dBUG firmware is a function called the TRAP 15 handler.This function can be called by the user program to utilize various routines within the dBUG,to perform a special task, and to return control to the dBUG. This section describes theTRAP 15 handler and how it is used.
There are four TRAP #15 functions. These are: OUT_CHAR, IN_CHAR,CHAR_PRESENT, and EXIT_TO_dBUG.
3.5.1 OUT_CHAR
This function ( function code 0x0013) sends a character, which is in the lower 8 bits of D1,to the terminal.
Assembly example:/* assume d1 contains the character */
move.l #$0013,d0 Selects the function
TRAP #15 The character in d1 is sent to terminal
C example:void board_out_char (int ch)
{
/* If your C compiler produces a LINK/UNLK pair for this routine,
* then use the following code which takes this into account
*/
#if l
/* LINK a6,#0 -- produced by C compiler */
asm (“ move.l8(a6),d1”); /* put ‘ch’into d1 */
asm (“ move.l#0x0013,d0”); /* select the function */
asm (“ trap#15”); /* make the call */
/* UNLK a6 -- produced by C compiler */
#else
/* If C compiler does not produce a LINK/UNLK pair, the use
* the following code.
*/
asm (“ move.l4(sp),d1”); /* put ‘ch’into d1 */
asm (“ move.l#0x0013,d0”); /* select the function */
asm (“ trap#15”); /* make the call */
#endif
}
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TRAP #15 Functions
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3.5.2 IN_CHAR
This function (function code 0x0010) returns an input character (from terminal) to thecaller. The returned character is in D1.
Assembly example:move.l #$0010,d0 Select the function
trap #15 Make the call, the input character is in d1.
C example:int board_in_char (void)
{
asm (“ move.l#0x0010,d0”); /* select the function */
asm (“ trap#15”); /* make the call */
asm (“ move.ld1,d0”); /* put the character in d0 */
}
3.5.3 CHAR_PRESENT
This function (function code 0x0014) checks if an input character is present to receive. Avalue of zero is returned in D0 when no character is present. A non-zero value in D0 meansa character is present.
Assembly example:move.l #$0014,d0 Select the function
trap #15 Make the call, d0 contains the response (yes/no).
C example:int board_char_present (void)
{
asm (“ move.l#0x0014,d0”); /* select the function */
asm (“ trap#15”); /* make the call */
}
3.5.4 EXIT_TO_dBUG
This function (function code 0x0000) transfers the control back to the dBUG, byterminating the user code. The register context are preserved.
Assembly example:move.l #$0000,d0 Select the function
trap #15 Make the call, exit to dBUG.
C example:
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TRAP #15 Functions
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void board_exit_to_dbug (void)
{
asm (“ move.l#0x0000,d0”); /* select the function */
asm (“ trap#15”); /* exit and transfer to dBUG */
}
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Appendix AConfiguring dBUG for Network DownloadsThe dBUG module has the ability to perform downloads over an Ethernet network usingthe Trivial File Transfer Protocol, TFTP (NOTE: this requires a TFTP server to be runningon the host attached to the board). Prior to using this feature, several parameters arerequired for network downloads to occur. The information that is required and the steps forconfiguring dBUG are described below.
A.1 Required Network ParametersFor performing network downloads, dBUG needs 6 parameters; 4 are network-related, and2 are download-related. The parameters are listed below, with the dBUG designationfollowing in parenthesis.
All computers connected to an Ethernet network running the IP protocol need 3network-specific parameters. These parameters are:
• Internet Protocol, IP, address for the computer (client IP),
• IP address of the Gateway for non-local traffic (gateway IP), and
• Network netmask for flagging traffic as local or non-local (netmask).
In addition, the dBUG network download command requires the following threeparameters:
• IP address of the TFTP server (server IP),
• Name of the file to download (filename),
• Type of the file to download (filetype of S-record, COFF, ELF, or Image).
Your local system administrator can assign a unique IP address for the board, and alsoprovide you the IP addresses of the gateway, netmask, and TFTP server. Fill out the linesbelow with this information.
Client IP: ___.___.___.___ (IP address of the board)Server IP: ___.___.___.___ (IP address of the TFTP server)Gateway: ___.___.___.___ (IP address of the gateway)Netmask: ___.___.___.___ (Network netmask)
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Configuring dBUG Network Parameters
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A.2 Configuring dBUG Network ParametersOnce the network parameters have been obtained, the dBUG Rom Monitor must beconfigured. The following commands are used to configure the network parameters.
set client <client IP>set server <server IP>set gateway <gateway IP>set netmask <netmask>set mac <addr>
For example, the TFTP server is named ‘santafe’ and has IP address 123.45.67.1. Theboard is assigned the IP address of 123.45.68.15. The gateway IP address is 123.45.68.250,and the netmask is 255.255.255.0. The MAC address is chosen arbitrarily and is unique.The commands to dBUG are:
set client 123.45.68.15set server 123.45.67.1set gateway 123.45.68.250set netmask 255.255.255.0set mac 00:CF:52:82:EB:01
The last step is to inform dBUG of the name and type of the file to download. Prior togiving the name of the file, keep in mind the following.
Most, if not all, TFTP servers will only permit access to files starting at a particularsub-directory. (This is a security feature which prevents reading of arbitrary files byunknown persons.) For example, SunOS uses the directory /tftp_boot as the default TFTPdirectory. When specifying a filename to a SunOS TFTP server, all filenames are relativeto /tftp_boot. As a result, you normally will be required to copy the file to download intothe directory used by the TFTP server.
A default filename for network downloads is maintained by dBUG. To change the defaultfilename, use the command:
set filename <filename>
When using the Ethernet network for download, either S-record, COFF, ELF, or Image filesmay be downloaded. A default filetype for network downloads is maintained by dBUG aswell. To change the default filetype, use the command:
set filetype <srecord|coff|elf|image>
Continuing with the above example, the compiler produces an executable COFF file,‘a.out’. This file is copied to the /tftp_boot directory on the server with the command:
rcp a.out santafe:/tftp_boot/a.out
Change the default filename and filetype with the commands:
set filename a.outset filetype coff
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Finally, perform the network download with the ‘dn’ command. The network downloadprocess uses the configured IP addresses and the default filename and filetype for initiatinga TFTP download from the TFTP server.
A.3 Troubleshooting Network ProblemsMost problems related to network downloads are a direct result of improper configuration.Verify that all IP addresses configured into dBUG are correct. This is accomplished via the‘show ’command.
Using an IP address already assigned to another machine will cause dBUG networkdownload to fail, and probably other severe network problems. Make certain the client IPaddress is unique for the board.
Check for proper insertion or connection of the network cable. Is the status LED litindicating that network traffic is present?
Check for proper configuration and operation of the TFTP server. Most Unix workstationscan execute a command named ‘tftp’ which can be used to connect to the TFTP server aswell. Is the default TFTP root directory present and readable?
If ‘ICMP_DESTINATION_UNREACHABLE’ or similar ICMP message appears, then aserious error has occurred. Reset the board, and wait one minute for the TFTP server totime out and terminate any open connections. Verify that the IP addresses for the serverand gateway are correct. Also verify that a TFTP server is running on the server.
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Troubleshooting Network Problems
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Appendix BSchematics
MOTOROLA Appendix B. Schematics B-1PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
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ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
Hie
rarc
hica
l Blo
ck D
iagr
amB
M52
3xE
VB
C
216
Frid
ay, A
pril
30, 2
004
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
Hie
rarc
hica
l Blo
ck D
iagr
amB
M52
3xE
VB
C
216
Frid
ay, A
pril
30, 2
004
Mot
orol
a S
PS
TS
PG
- T
EC
D C
oldF
ire G
roup
She
et 1
5S
eria
l I/O
U2TXD
U1TXD
U0RXD
/U1RTS
/U0CTSU0TXD
/U1CTS
/U0RTS
U2RXD
U1RXD
QSPI_DIN
QSPI_PCS1
QSPI_DOUTQSPI_PCS0
QSPI_SCK
I2C_SCLI2C_SDA
CANH1CANL1
/U2RTS/U2CTS
/RSTOUT/IRQ[7:1]
She
et 3
AS
RA
M
B_A[23:0]
/BS[3:0]
/OE
B_D[31:0]
R/W
/CS[7:0]
She
et 1
3R
eset
Con
fig &
Clo
cks
/RESET/BDM_RSTIN
/EXT_RSTIN
XTALEXTAL
ETH_CLK/IRQ[7:1]
D[31:0]
JTAG_EN/RCON
CLKMOD[1:0]/RSTOUT
CLKOUT
/CS[7:0]
/BS[3:0]
LTPUODISUTPUODIS
/OER/W/TS
/TIP/TA
/TEA
TSIZ0
TSIZ1
DTIN0DTOUT0
DTIN1
DTIN2
DTIN3
DTOUT1
DTOUT2
DTOUT3
TMS/BKPTTDI/DSI
TDO/DSOTRST/DSCLK
ETPU/ETH
She
et 5
CA
N
CAN0RXCAN0TX
CAN1TXCAN1RX
CANH1CANL1
She
et 4
Buf
fers
A[23:0]
B_A[23:0]
D[31:0]
B_D[31:0]
R/W
/CS[7:0]
She
et 7
Deb
ug
DDATA[3:0]
PST[3:0]
TCLK/PSTCLK
TDO/DSO
TMS/BKPT
TDI/DSI
TRST/DSCLK
/TA
BDM_/RSTIN
She
et 1
1F
lash
Mem
ory
B_A[23:0]B_D[31:0]/CS[7:0]
/OE
R/W
She
et 1
4S
DR
AM
/BS[3:0]
/SD_CS0
/SD_WESD_SCKE
D[31:0]
/SD_RAS
A[23:0]
CLKOUT
/SD_CAS
She
et16
US
B
B_D[31:0]
/RSTOUT
B_A[23:0]
/CS[7:0]
/OER/W
/IRQ[7:1]
DTIN1
DTIN2DTOUT1
DTOUT2
She
et 1
0
Exp
ansi
on C
onne
ctor
s
TP
UC
H[1
5:0]
TP
UC
H[3
1:16
]
TC
RC
LK
/U0C
TS
U0R
XD
DT
OU
T0
DT
IN0
U0T
XD
/U0R
TS
CLK
MO
D[1
:0]
D[3
1:0]
/EX
T_R
ST
IN
/OE
DT
OU
T1
DT
IN1
/IRQ
[7:1
]
TS
IZ0
TC
LK/P
ST
CLK
DT
OU
T2
DT
IN2
TD
I/DS
IT
DO
/DS
O
TM
S/B
KP
T
TR
ST
/DS
CLK
PS
T[3
:0]
DD
AT
A[3
:0]
JTA
G_E
N/R
CO
N
/RS
TO
UT
/RE
SE
T
EX
TA
LX
TA
L
/SD
_CS
1
CLK
OU
T
/SD
_CA
S
/SD
_CS
0/S
D_R
AS
R/W
CA
N0T
XC
AN
0RX
/SD
_WE
/TS
/TIP
/TA
/TE
A
DT
OU
T3
DT
IN3
LTP
UO
DIS
UT
PU
OD
IS
A[2
3:0]
/CS
[7:0
]
TS
IZ1
U1T
XD
U1R
XD
/U1R
TS
U2T
XD
/U1C
TS
CA
N1T
X
U2R
XD
CA
N1R
X
SD
_SC
KE
QS
PI_
PC
S1
/BS
[3:0
]
QS
PI_
PC
S0
QS
PI_
DO
UT
QS
PI_
DIN
I2C
_SD
A
QS
PI_
SC
K
I2C
_SC
L
EM
DC
EM
DIO
/U2C
TS
/U2R
TS
She
et 6
CP
U A[2
3:0]
D[3
1:0]
/CS
[7:0
]
U1T
XD
/BS
[3:0
]
/OE
/IRQ
[7:1
]
TS
IZ0
TS
IZ1
CLK
MO
D[1
:0]
DT
OU
T1
DT
IN1
DT
OU
T2
DT
IN2
TC
LK/P
ST
CLK
PS
T[3
:0]
DD
AT
A[3
:0]
XT
AL
EX
TA
L
/SD
_CS
1/S
D_C
S0
JTA
G_E
N
CLK
OU
T
/SD
_RA
S/S
D_C
AS
R/W
CA
N0R
XC
AN
0TX
/SD
_WE
/TS
/TIP
/TA
/TE
A
DT
OU
T3
DT
IN3
LTP
UO
DIS
UT
PU
OD
IS
TP
UC
H[1
5:0]
U0R
XD
QS
PI_
PC
S1
/U1C
TS
/RS
TO
UT
/RC
ON
DT
OU
T0
TD
O/D
SO
/U0C
TS
SD
_SC
KE
/U1R
TS
TR
ST
/DS
CLK
QS
PI_
DO
UT
/U0R
TS
QS
PI_
PC
S0
U1R
XD
TM
S/B
KP
T
U0T
XD
QS
PI_
DIN
U2R
XD
TD
I/DS
I
QS
PI_
SC
K
U2T
XD
DT
IN0
TP
UC
H[3
1:16
]
EM
DIO
EM
DC
TC
RC
LK
/RE
SE
T
CA
N1R
XC
AN
1TX
I2C
_SD
AI2
C_S
CL
ER
XE
R
ET
XD
2E
TX
D1
ET
XE
N
ET
XD
3
ET
XE
R
ER
XD
0E
RX
D1
ER
XD
2E
RX
D3
ER
XC
LK
ER
XD
V
ET
XC
LKE
TX
D0
EC
OL
EC
RS
/U2R
TS
/U2C
TS
ET
PU
/ET
H
She
et 8
Eth
erne
t
/RSTOUT
ETH_CLK
EMDIOEMDC
/IRQ[7:1]
ECOLECRSERXDVERXERERXCLKERXD0ERXD1ERXD2ERXD3ETXENETXERETXCLKETXD0ETXD1ETXD2ETXD3
She
et 1
2P
SU
She
et 9
eTP
U
TCRCLKUTPUODISLTPUODISTPUCH[15:0]TPUCH[31:16]
QSPI_DINQSPI_SCK
QSPI_DOUTQSPI_PCS0
/TIP/TEATSIZ0TSIZ1
For More Information On This Product,
Go to: www.freescale.com
D C B A
Re
v BR
ev B
Re
v B
F
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sca
le S
em
ico
nd
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tor,
I
Freescale Semiconductor, Inc.n
c..
.
5 5
4 4
3 3
2 2
1 1
B_
A[2
3:0
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2
B_
D2
0
B_
A[2
3:0
]
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0/C
S1
B_
A[2
3:0
]
/BS
1
/BS
3
/BS[3:0]
/CS
1
B_
D1
0
B_
D1
8
B_
D1
1
B_
D2
4
B_
D1
6
B_
D1
3
B_
D5
B_
D0
B_
D8
B_
D1
9
B_
D2
5
B_
D1
7
B_
D7
B_
D1
2
B_
D1
B_
D2
8
B_
D3
1
B_
D2
3
B_
D2
6
B_
D[3
1:0
]
B_
D[3
1:0
]
B_
D1
5
B_
D2
2
B_
D2
9
B_
D2
1B
_D
27
B_
D9
B_
D2
B_
D3
B_
D6
B_
D4
B_
D1
4
B_
D3
0
B_
A5
B_
A3
B_
A1
8
B_
A1
8
B_
A9
B_
A7
B_
A4
B_
A1
0B
_A
11
B_
A1
7
B_
A2
B_
A5
B_
A1
9
B_
A1
4
B_
A1
9
B_
A9
B_
A1
5
B_
A1
5
B_
A1
2
B_
A4
B_
A2
B_
A1
0
B_
A7
B_
A1
6
B_
A3
B_
A6
B_
A1
3
B_
A1
2B
_A
11
B_
A1
6B
_A
8
B_
A1
3
B_
A1
7
B_
A6
B_
A8
B_
A1
4
/CS
[7:0
]
B_
A[2
3:0
]
/BS
[3:0
]
/OE
B_
D[3
1:0
]
/CS
[7:0
]
R/W
+3
.3V
+3
.3V
+3
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+3
.3V
V
Titl
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me
nt
Nu
mb
er
Da
te:
Sh
ee
to
f
SC
H-2
03
80
Asy
nch
ron
ou
s S
RA
M
M5
23
xEV
B
B
31
6F
rid
ay,
Ap
ril 3
0,
20
04
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mb
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Da
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SC
H-2
03
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M
M5
23
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B
B
31
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Ap
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0,
20
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f
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H-2
03
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M
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23
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B
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Ap
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AS
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TS
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Do
no
t p
op
ula
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Ea
ch A
SR
AM
is 2
56
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16
bit (
51
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To
tal A
SR
AM
ava
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1M
B
NO
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: A
lte
rna
tive
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RA
M's
with
th
e s
am
e P
CB
fo
otp
rin
t a
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fu
nct
ion
alit
y a
re :
- R
en
esa
s H
M6
2W
16
25
5H
CJP
-12
Mo
toro
la S
PS
TS
PG
- T
EC
D C
old
Fir
e G
rou
p
A0
1
A1
2
A2
3
A3
4
A4
5
/CE
6
I/0
07
I/0
18
I/0
29
I/0
31
0
VC
C1
1
VS
S1
2
I/0
41
3
I/0
51
4
I/0
61
5
I/0
71
6
/WE
17
A5
18
A6
19
A7
20
A8
21
A9
22
A1
02
3A
11
24
A1
22
5A
13
26
A1
42
7N
C2
8I/O
82
9I/O
93
0I/
O1
03
1I/
O1
13
2V
CC
33
VS
S3
4I/
O1
23
5I/
O1
33
6I/
O1
43
7I/
O1
53
8/B
LE
39
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E4
0/O
E4
1A
15
42
A1
64
3A
17
44
U2
CY
7C
10
41
CV
33
10
ZC
U2
CY
7C
10
41
CV
33
10
ZC
1 nF1 nF
C2
1n
FC
21
nF
C3
1n
FC
31
nF
C4
1n
FC
41
nF
A0
1
A1
2
A2
3
A3
4
A4
5
/CE
6
I/0
07
I/0
18
I/0
29
I/0
31
0
VC
C1
1
VS
S1
2
I/0
41
3
I/0
51
4
I/0
61
5
I/0
71
6
/WE
17
A5
18
A6
19
A7
20
A8
21
A9
22
A1
02
3A
11
24
A1
22
5A
13
26
A1
42
7N
C2
8I/O
82
9I/O
93
0I/
O1
03
1I/
O1
13
2V
CC
33
VS
S3
4I/
O1
23
5I/
O1
33
6I/
O1
43
7I/
O1
53
8/B
LE
39
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E4
0/O
E4
1A
15
42
A1
64
3A
17
44
U1
CY
7C
10
41
CV
33
10
ZC
U1
CY
7C
10
41
CV
33
10
ZC
C7
0.1
uF
C7
0.1
uF
C6
0.1
uF
C6
0.1
uF
C5
0.1
uF
C5
0.1
uF
C8
0.1
uF
C8
0.1
uF
D C B A
+3
.3
C 1C 1
For More Information On This Product,
Go to: www.freescale.com
F
ree
sca
le S
em
ico
nd
uc
tor,
I
Freescale Semiconductor, Inc.n
c..
.
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
B_A
18
B_A
15
B_D
17
D7
A0
B_D
8
D18
D28
D[3
1:0]
B_A
17
A18
B_D
16
A11
A7
B_D
30
D10
D23
B_D
21
B_D
10
D30
B_D
1D
2
B_A
19
B_A
4
B_D
18
D20
B_D
[31:
0]
A1
D8
B_D
9
D16
A19
B_D
13
B_D
2
D6
B_D
26
A12
A8
D17
B_D
31
B_D
11
B_D
22
B_A
20
B_A
5
B_D
19
A2
B_D
27
B_D
3
A13
A9
D11
B_D
12
D0
B_A
21
B_A
6
A20
A3
B_A
10
A15
D9
B_D
28
A14
B_A
22
B_A
7
B_D
0
B_D
23
D19
D22
D21
D24
A4
D25
B_A
0
B_A
11
B_D
4
B_A
16
B_A
8
D5
A[2
3:0]
B_D
24
D3
A21
D26
B_A
12
B_A
1
B_D
5
D14
B_A
[23:
0]
B_A
9
D12
B_D
25
B_A
2
B_A
13
B_D
6
D13
D15
A22
A16
B_D
14
A5
B_A
14
B_A
3
D4
B_D
7
D1
D27
A17
B_D
15
A10
A6
B_D
29
B_D
20
D31
D29
B_A
23A
23
/CS
2
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0
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1
D[3
1:0]
B_D
[31:
0]
R/W
A[2
3:0]
B_A
[23:
0]
/CS
[7:0
]
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
Buf
fers
B
M52
3xE
VB
B
416
Frid
ay, A
pril
30, 2
004
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
Buf
fers
B
M52
3xE
VB
B
416
Frid
ay, A
pril
30, 2
004
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
Buf
fers
B
M52
3xE
VB
B
416
Frid
ay, A
pril
30, 2
004
AD
DR
ES
S B
US
BU
FF
ER
S
Add
ress
and
Dat
a B
us b
uffe
rs/tr
ansc
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rs u
sed
to b
uffe
rth
e si
gnal
s fo
r th
e A
SR
AM
and
Fla
sh m
emor
ies
and
the
US
B c
ontr
olle
r.
DA
TA
BU
S T
RA
NS
CE
IVE
RS
AN
D G
ate
Mot
orol
a S
PS
TS
PG
- T
EC
D C
oldF
ire G
roup
1B1
2
1B2
3
1B3
5
1B4
6
1B5
8
1B6
9
1B7
11
1B8
12
2B1
13
2B2
14
2B3
16
2B4
17
2B5
19
2B6
20
2B7
22
2B8
23
1DIR
1
1OE
48
2OE
25
2DIR
24
GN
D4
GN
D1
0
GN
D1
5
GN
D2
1
GN
D2
8
GN
D3
4
GN
D3
9
GN
D4
5
1A1
47
1A2
46
1A3
44
1A4
43
1A5
41
1A6
40
1A7
38
1A8
37
2A1
36
2A2
35
2A3
33
2A4
32
2A5
30
2A6
29
2A7
27
2A8
26
VC
C7
VC
C1
8
VC
C3
1
VC
C4
2
U3
MC
74LC
X16
245D
T
U3
MC
74LC
X16
245D
T
1B1
2
1B2
3
1B3
5
1B4
6
1B5
8
1B6
9
1B7
11
1B8
12
2B1
13
2B2
14
2B3
16
2B4
17
2B5
19
2B6
20
2B7
22
2B8
23
1DIR
1
1OE
48
2OE
25
2DIR
24
GN
D4
GN
D1
0
GN
D1
5
GN
D2
1
GN
D2
8
GN
D3
4
GN
D3
9
GN
D4
5
1A1
47
1A2
46
1A3
44
1A4
43
1A5
41
1A6
40
1A7
38
1A8
37
2A1
36
2A2
35
2A3
33
2A4
32
2A5
30
2A6
29
2A7
27
2A8
26
VC
C7
VC
C1
8
VC
C3
1
VC
C4
2
U6
MC
74LC
X16
245D
T
U6
MC
74LC
X16
245D
T
1B1
2
1B2
3
1B3
5
1B4
6
1B5
8
1B6
9
1B7
11
1B8
12
2B1
13
2B2
14
2B3
16
2B4
17
2B5
19
2B6
20
2B7
22
2B8
23
1DIR
1
1OE
48
2OE
25
2DIR
24
GN
D4
GN
D1
0
GN
D1
5
GN
D2
1
GN
D2
8
GN
D3
4
GN
D3
9
GN
D4
5
1A1
47
1A2
46
1A3
44
1A4
43
1A5
41
1A6
40
1A7
38
1A8
37
2A1
36
2A2
35
2A3
33
2A4
32
2A5
30
2A6
29
2A7
27
2A8
26
VC
C7
VC
C1
8
VC
C3
1
VC
C4
2
U4
MC
74LC
X16
245D
T
U4
MC
74LC
X16
245D
T
T/R
1
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
GN
D1
0
VC
C2
0
OE
19
B0
18
B1
17
B2
16
B3
15
B4
14
B5
13
B6
12
B7
11
U7
MC
74LC
X24
5DT
U7
MC
74LC
X24
5DT
C13
1nF
C13
1nF
C9
0.1u
FC
90.
1uF
C10
0.1u
FC
100.
1uF
11
22
33
44
55
66
77
88
RP
2
4x 4
.7K
RP
2
4x 4
.7K
A GN
DB
CV
CC Y
U5
SN
74LV
C1G
11
U5
SN
74LV
C1G
11
11
22
33
44
55
66
77
88
RP
1
4x 4
.7K
RP
1
4x 4
.7K
C11
0.1u
FC
110.
1uF
C12
1nF
C12
1nF
C15
1nF
C15
1nF
C14
1nF
C14
1nF
For More Information On This Product,
Go to: www.freescale.com
F
ree
sca
le S
em
ico
nd
uc
tor,
I
Freescale Semiconductor, Inc.n
c..
.
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
CA
NL1
CA
NH
1
CA
N1R
X
CA
N1T
X
CA
N0R
X
CA
N0T
X
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
CA
N T
rans
ceiv
ers
B
M52
3xE
VB
B
516
Frid
ay, A
pril
30, 2
004
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
CA
N T
rans
ceiv
ers
B
M52
3xE
VB
B
516
Frid
ay, A
pril
30, 2
004
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
CA
N T
rans
ceiv
ers
B
M52
3xE
VB
B
516
Frid
ay, A
pril
30, 2
004
Def
ault
setti
ng fo
r JP
2 is
fitte
d.
Def
ault
setti
ng fo
r JP
4 is
fitte
d.
Def
ault
setti
ng fo
r JP
1 is
NO
T fi
tted.
CA
N B
us C
onne
ctor
-
9 w
ay D
-typ
e(F
emal
e)
CA
N1
and
UA
RT
2 sh
are
the
sam
eD
B9
conn
ecto
r on
She
et 1
5
Def
ault
setti
ng fo
r JP
3 is
NO
T fi
tted.
CA
N C
hann
el 0
CA
N C
hann
el 1
Tra
nsce
iver
Mod
e
CA
N T
erm
inat
ion
CA
N T
erm
inat
ion
Tra
nsce
iver
Mod
e
Mot
orol
a S
PS
TS
PG
- T
EC
D C
oldF
ire G
roup
12
JP1
JP1
R3
1KR3
1K
R2
62R2
62
D1
GN
D2
VC
C3
R4
VR
EF
5C
AN
L6
CA
NH
7R
S8
U9
SN
65H
VD
230D
U9
SN
65H
VD
230D
5 9 4 8 3 7 2 6 1
P1
P1
C16
0.1u
FC
160.
1uF
C17
0.1u
FC
170.
1uF
12
JP3
JP3
C18
1nF
C18
1nF
R1
1KR1
1K
C19
1nF
C19
1nF
R4
62R4
62
12
JP2
JP2
12
JP4
JP4
D1
GN
D2
VC
C3
R4
VR
EF
5C
AN
L6
CA
NH
7R
S8
U8
SN
65H
VD
230D
U8
SN
65H
VD
230D
For More Information On This Product,
Go to: www.freescale.com
F
ree
sca
le S
em
ico
nd
uc
tor,
I
Freescale Semiconductor, Inc.n
c..
.
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
CLK
MO
D[1
:0]
A[2
3:0]
PST0
/IRQ3
D31
TP
UC
H11
TP
UC
H10
/CS
[7:0
]
/CS7
A10
A5
A1
A3
/IRQ1
D3
D17
CLK
MO
D1
/BS0
A16
D21
D29
A23
/CS3
DDATA0
D5
CLK
MO
D0
TP
UC
H14
D[31:0]
A[23:0]
D27
TP
UC
H8
D14
/BS3/BS2
A14
/IRQ7
D18
D23
A20
A15
A0
D0
D1
D6
A8
D8
D15
D13
D20
TP
UC
H13
/BS
[3:0
]
A19
A12
A13
A7
DD
AT
A[3
:0]
PST1
D11
D9
/CS6
/CS4
A17
D19
D26
D30
TP
UC
H12
PS
T[3
:0]
/BS1
A6
/IRQ5/IRQ4
D10
D16
D12
D28
/IRQ
[7:1
]
D[3
1:0]
A21
A18
PST2
D2
A11
A9
A2
D22
D24
TP
UC
H15
TP
UC
H7
PST3/CS0
/CS1/CS5
TP
UC
H4
TP
UC
H0
TP
UC
H3
TP
UC
H1
TP
UC
H5
TP
UC
H6
TP
UC
H2
TPUCH[15:0]
DDATA3
TP
UC
H19
TP
UC
H29
TP
UC
H28
TP
UC
H31
TPUCH[31:16]
TP
UC
H16
TP
UC
H23
TP
UC
H22
TP
UC
H27
TP
UC
H26
TP
UC
H17
TP
UC
H18
TP
UC
H21
TP
UC
H20
TP
UC
H25
TP
UC
H24
TP
UC
H30
A4
DDATA1
D7
/IRQ2
D4
D25
A22
DDATA2
/IRQ6
/CS2
TP
UC
H9
A[2
3:0]
D[3
1:0]
/CS
[7:0
]
U1TXD
/BS
[3:0
]
/OE
/IRQ
[7:1
]
TSIZ0TSIZ1
CLK
MO
D[1
:0]
DTOUT1DTIN1
DTOUT2DTIN2
TCLK/PSTCLK
PS
T[3
:0]
DD
AT
A[3
:0]
XT
AL
EX
TA
L
/SD
_CS
1
/SD
_CS
0
JTA
G_E
N
CLK
OU
T
/SD
_RA
S/S
D_C
AS
R/W
CA
N0R
XC
AN
0TX
/SD
_W
E
/TS
/TIP
/TA
/TE
AD
TO
UT
3
DT
IN3
LTP
UO
DIS
UT
PU
OD
IS
TP
UC
H[1
5:0]
U0R
XD
QSPI_PCS1
/U1CTS
/RSTOUT
/RCON
DT
OU
T0
TDO/DSO
/U0C
TS
SD_SCKE
/U1RTS
TRST/DSCLK
QSPI_DOUT
/U0R
TS
QSPI_PCS0
U1RXD
TMS/BKPT
U0T
XD
QS
PI_
DIN
TDI/DSI
QS
PI_
SC
K
DT
IN0
EMDIOEMDC
TC
RC
LK
/RESET
U2R
XD
CA
N1R
X
U2T
XD
CA
N1T
X
ET
XC
LK
ET
XD
1
ER
XE
R
ET
XE
N
ET
XD
2
ET
XE
R
ET
XD
3
ET
XD
0
ER
XD
0
ER
XD
1
ER
XD
2
ER
XD
3
ER
XC
LK
ER
XD
V
EC
OL
EC
RS
TP
UC
H[3
1:16
]
I2C
_SD
AI2
C_S
CL
/U2C
TS
/U2R
TS
ET
PU
/ET
H
+1.5
VP
+3.3
VP
+3.3
VP
VS
SP
LLV
SS
PLL
VS
SP
LL
+3.3
VP
+3.3
VP
+1.5
VP
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
CP
UB
M52
3xE
VB
C
616
Frid
ay, A
pril
30, 2
004
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
CP
UB
M52
3xE
VB
C
616
Frid
ay, A
pril
30, 2
004
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
CP
UB
M52
3xE
VB
C
616
Frid
ay, A
pril
30, 2
004
NO
TE
: Pla
ce C
33, C
34 &
L1
as c
lose
to p
ins
P15
& R
15 a
s po
ssib
le u
sing
ase
para
te g
roun
d pl
ane.
Pla
ce R
5 as
clos
e to
pin
C10
as p
ossi
ble.
Pla
ce R
6 as
clos
e to
pin
N15
as p
ossi
ble.
Pla
ce R
P3
as c
lose
to p
ins,
L13,
M13
, M14
& M
15 a
spo
ssib
le.
PLL Filter Circuit
eTP
U/E
ther
net E
nabl
e-
see
page
13
256M
apB
GA
Def
ault
setti
ng fo
r JP
5, J
P9,
JP
10,
JP11
, JP
13-2
4 is
2 &
3 c
onne
cted
Def
ault
setti
ng fo
rJP
6 &
JP
8 is
pin
s 1&
2D
efau
lt se
tting
for
JP7
& J
P11
is p
ins
2&3
Def
ault
setti
ng fo
r JP
25 &
JP26
is b
ewte
en p
ins
1&2
Mot
orol
a S
PS
TS
PG
- T
EC
D C
oldF
ire G
roup
Mot
orol
a C
old
Fire
Mic
ropr
oces
sor
MC
F52
35
TM
12
3
JP21
JP21
C18
5
0.1u
F
C18
5
0.1u
F
R5
22R
522
12
3
JP6
JP6
12
3
JP9
JP9
12
3
JP14
JP14
C30
0.1u
F
C30
0.1u
F
R6
22R6
22
C32
10uF
TA
NT
.C
3210
uF T
AN
T.
12
3
JP18
JP18
C18
4
0.1u
F
C18
4
0.1u
F
12
3
JP22
JP22
12
3
JP25
JP25
C26
1nF
C26
1nF
C28
0.1u
F
C28
0.1u
F
C24
1nF
C24
1nF
C34
1000
pFC
3410
00pF
12
3
JP7
JP7
C18
3
1nF
C18
3
1nF
12
3
JP8
JP8
1
VIA
2V
IA2
C20
100p
F
C20
100p
F
12
3
JP10
JP10
C31
0.1u
F
C31
0.1u
F
C21
100p
F
C21
100p
F
12
3
JP15
JP15
12
3
JP19
JP19
C22
100p
F
C22
100p
F
12
3
JP23
JP23
12
3
JP26
JP26
C25
1nF
C25
1nF
C29
0.1u
F
C29
0.1u
F
C18
1
100p
F
C18
1
100p
F
C18
2
1nF
C18
2
1nF
12
3
JP12
JP12
C18
0
100p
F
C18
0
100p
F
12
3
JP11
JP11
1VIA
1V
IA1
12
3
JP17
JP17
C18
6
0.1u
F
C18
6
0.1u
F
12
3
JP20
JP20
C23
100p
F
C23
100p
F
12
3
JP24
JP24
VS
SA
1
TP
UC
H8
B1
TP
UC
H7
B2
TP
UC
H10
C1
TP
UC
H9
C2
TP
UC
H25
/ER
XD
1C
3
TP
UC
H12
D1
TP
UC
H11
D2
TP
UC
H27
/ER
XD
3D
3
TP
UC
H26
/ER
XD
2D
4
TP
UC
H14
E1
TP
UC
H13
E2
TP
UC
H29
/ER
XC
LKE
3
TP
UC
H28
/ER
XD
VE
4
TC
RC
LKF
1
TP
UC
H15
F2
TP
UC
H31
/EC
OL
F3
TP
UC
H30
/EC
RS
F4
U0C
TS
G1
U0R
XD
G2
DT
OU
T0
G3
DT
IN0
G4
Cor
e V
DD
H1
U0T
XD
H2
U0R
TS
H3
NC
H4
VS
SJ1
CLK
MO
D0
J2
CLK
MO
D1
J3
D28
K1
D29
K2
D30
K3
D31
K4
D24
L1
D25
L2
D26
L3
D27
L4
D21
M1
D22
M2
D23
M3
D19
N1
D20
N2
D13
N3
D9 N4
D17
P1
D18
P2
D12 P3
D16
R1
D15 R2
VSS T1
D14 T2
D10 T3
D11 R3
D6 T4
D7 R4
D8 P4
Core VDD T5
D4 R5
D5 P5
VSS T6
D1 R6
D2 P6
D3 N6
OE T7
DTOUT1 R7
DTIN1 P7
D0 N7
IRQ6 T8
IRQ7 R8
TE
ST
J4
eTP
U/E
thE
NB
M4
NC N5
TSIZ0 P8
TSIZ1 N8
IRQ2 T9
IRQ3 R9
IRQ4 P9
IRQ5 N9
TCLK/PSTCLK T10
DTOUT2 R10
DTIN2 P10
IRQ1 N10
TDI/DSI T11
TDO/DSO R11
TMS/BKPT P11
TRST/DSCLK N11
PST3 T12
PST2 R12
PST1 P12
PST0 N12
DDATA1 T13
DDATA0 R13
RCON P13
RSTOUT T14
PLL_TEST R14
RESET T15VS
ST
16
XT
AL
R16
VS
SP
LLR
15
EX
TA
LP
16
VD
DP
LLP
15
DD
AT
A2
P14
VS
SN
16
SD
_CS
1N
15
DD
AT
A3
N14
JTA
G_E
NN
13
CLK
OU
TM
16
SD
_CA
SM
15S
D_R
AS
M14
SD
_CS
0M
13
R/W
L16
I2C
_SD
A/C
AN
0RX
L15
I2C
_SC
L/C
AN
0TX
L14
SD
_WE
L13
TSK
16T
IPK
15TA
K14
TE
AK
13
DT
OU
T3/
U2R
TS
J16
DT
IN3/
U2C
TS
J15
LTP
UO
DIS
J14
UT
PU
OD
ISJ1
3
A3
H16
A2
H15
A1
H14
A0
H13
Cor
e V
DD
G16
A6
G15
A5
G14
A4
G13
VS
SF
16
A9
F15
A8
F14
A7
F13
A13
E16
A12
E15
A11
E14
A10
E13
A16
D16
A15
D15
A14
D14
CS0D13
A17
C16
A18
C15
A22C14
A19
B16
A20B15
VSSA16
A21A15
CS4A14
A23B14
CS6A13CS1B13CS5C13
U1TXDA12
CS3B12 CS7C12CS2D12
U1RXDA11U1RTSB11 U1CTSC11
U2TXD/CAN1TXD11
BS0A10
QSPI_PCS1B10
SD_SCKEC10
U2RXD/CAN1RXD10
BS1A9BS2B9 BS3C9
QSPI_PCS0D9
Core VDDA8
QSPI_SCK/I2C_SCLB8QSPI_DIN/I2C_SDAC8
QSPI_DOUTD8
TPUCH0A7TPUCH16/ETXD0B7
EMDIOC7EMDCD7
TPUCH1A6 TPUCH19/ETXD3B6TPUCH20/ETXERC6 TPUCH21/ETXEND6
TPUCH17/ETXD1A5 TPUCH18/ETXD2B5TPUCH22/ETXCLKC5TPUCH23/ERXERD5 TPUCH2A4
TPUCH3B4 TPUCH24/ERXD0C4TPUCH4A3TPUCH5B3 TPUCH6A2
VS
SE
5
VD
DF
5
VS
SF
6
VD
DG
5
VD
DG
6
VS
SG
7
VD
DH
5
VD
DH
6
VS
SH
7
VS
SH
8
VD
DJ5
VD
DJ6
VS
SJ7
VD
DK
5
VD
DK
6
VD
DL5
VSS M5
VDD M6
VSS L6
VDD M7
VDD L7
VSS K7
VDD M8
VDD L8
VSS K8
VSS J8
VDD M9
VDD L9
VSS K9
VDD M10
VDD L10
VDD M11
VS
SM
12
VD
DL1
2V
SS
L11
VD
DK
12V
DD
K11
VS
SK
10
VD
DJ1
2V
DD
J11
VS
SJ1
0V
SS
J9
VD
DH
12V
DD
H11
VS
SH
10
VD
DG
12V
DD
G11
VD
DF
12
VSSE12
VDDE11VSSF11
VDDE10 VDDF10VSSG10
VDDE9 VDDF9VSSG9VSSH9
VDDE8 VDDF8VSSG8
VDDE7 VDDF7
VDDE6
U10
MC
F52
35
U10
MC
F52
35
C18
7
0.1u
F
C18
7
0.1u
F
C27
1nF
C27
1nF
1
TP1 PLL Test Point
TP1 PLL Test Point
12
3
JP5
JP5
11
22
33
44
55
66
77
88
RP
3
4x 2
2
RP
3
4x 2
2
12
3
JP13
JP13
L1 10uH
L1 10uH
12
3
JP16
JP16
C33
0.1u
FC
330.
1uF
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ree
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tor,
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.
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
DD
AT
A2
DD
AT
A1
DD
AT
A0
DD
AT
A[3
:0]
PS
T0
DD
AT
A[3
:0]
PS
T3
PS
T2
DD
AT
A3
PS
T1
PS
T[3
:0]
PS
T[3
:0]
DD
AT
A[3
:0]
PS
T[3
:0]
TD
O/D
SO
TM
S/B
KP
T
TD
I/DS
I
TR
ST
/DS
CLK
BD
M_/
RS
TIN
/TA
TC
LK/P
ST
CLK
+1.5
V+3
.3V
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
BD
M/J
TA
G D
ebug
Por
tB
M52
3xE
VB
A
716
Frid
ay, A
pril
30, 2
004
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
BD
M/J
TA
G D
ebug
Por
tB
M52
3xE
VB
A
716
Frid
ay, A
pril
30, 2
004
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
BD
M/J
TA
G D
ebug
Por
tB
M52
3xE
VB
A
716
Frid
ay, A
pril
30, 2
004
Def
ault
setti
ng fo
rJP
27 is
fitte
d.
NO
TE
: JP
27 is
req
uire
d fo
r so
me
of th
e le
gacy
BD
Mca
bles
that
con
nect
pin
s 9
& 2
5 of
the
BD
M in
terf
ace
inte
rnal
ly. M
ore
rece
nt c
able
s su
ppor
t bot
h co
re &
I/O
volta
ges.
Ple
ase
chec
k w
ith y
our
BD
M c
able
sup
plie
r.
Cor
e V
olta
ge
IMP
OR
TA
NT
NO
TE
: ON
LY 3
.3V
BD
M d
ebug
ging
cab
les
can
be u
sed
with
the
MC
F52
3x p
roce
ssor
s.
I/O V
olta
ge
NO
TE
: 4.7
K p
ull u
p re
sist
ors
are
used
on
sign
als
/BK
PT
, DS
CLK
, DS
I, D
SO
& /R
ES
ET
. A 1
K p
ull u
p is
use
d fo
r /T
A. S
ee p
age
13 o
f the
sch
emat
ics.
Def
ault
setti
ng -
FIT
TE
D
Mot
orol
a S
PS
TS
PG
- T
EC
D C
oldF
ire G
roup
R7
10K
R7
10K
12
JP28
JP28
1 3 5 7 9 11 13 15 17 19 21 23 25
2 4 6 8 10 12 14 16 18 20 22 24 26
J1J1
12
JP27
JP27
For More Information On This Product,
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ree
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tor,
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Freescale Semiconductor, Inc.n
c..
.
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
/IRQ
[7:1
]/IR
Q2
/RS
TO
UT
ET
H_C
LK
EM
DIO
EM
DC
/IRQ
[7:1
]
ER
XD
3E
RX
D2
ER
XD
1E
RX
D0
ER
XD
VE
RX
CLK
ER
XE
RE
TX
CLK
ET
XE
RE
TX
EN
ET
XD
0E
TX
D1
ET
XD
2E
TX
D3
EC
OL
EC
RS
+3.
3V
+3.
3V
+2.
5VP
LL+
2.5V
A
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+2.
5VA
+2.
5VA
+2.
5VA
+2.
5VA
+2.
5VA
+2.
5VA
+2.
5VP
LL
+2.
5V
+2.
5V
+2.
5V
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
10/
100B
aseT
Eth
erne
t Tra
nsce
iver
B
M52
3xE
VB
B
816
Frid
ay, A
pril
30, 2
004
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
10/
100B
aseT
Eth
erne
t Tra
nsce
iver
B
M52
3xE
VB
B
816
Frid
ay, A
pril
30, 2
004
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
10/
100B
aseT
Eth
erne
t Tra
nsce
iver
B
M52
3xE
VB
B
816
Frid
ay, A
pril
30, 2
004
Pla
ce s
ilk s
cree
n LE
D la
bels
next
to D
1 th
ru' D
4.
Sep
arat
e R
J45
conn
ecto
rch
assi
s gr
ound
.
NO
TE
: Eth
erne
t Ch.
phy
sica
l add
r. d
efau
lt se
tting
is a
ddr.
=1
sele
cted
via
inte
rnal
res
isto
r bi
asin
g du
ring
rese
t.
Pla
ce R
P4
& R
P5
as c
lose
to U
11 a
s po
ssib
le.
Pla
ce R
P6
& R
P7
as c
lose
to th
eM
CF
523x
(C
PU
) as
pos
sibl
e.Li
nk L
ED
Col
lisio
nLE
D
100B
T L
ED
Ful
l Dup
lex
LED
Ana
log
Eth
erne
t Pla
ne
GR
EE
N
GR
EE
N
GR
EE
N
GR
EE
N
Pla
ce th
e ca
paci
tors
abo
vecl
ose
to p
ins
7 an
d 24
on
U11
.
Pla
ce R
8, R
9, R
10 &
R11
clo
se to
U11
.
NO
TE
: U11
KS
8721
BL
has
an o
n-ch
ip L
DO
that
deriv
es th
e +
2.5V
sup
ply
from
the
+3.
3V s
uppl
y.
Mot
orol
a S
PS
TS
PG
- T
EC
D C
oldF
ire G
roup
NO
TE
: RP
27 is
pre
sent
to e
nsur
eth
e co
rrec
t con
figur
atio
n of
U11
out o
f res
et.
C46
0.1u
FC
460.
1uF
R12
4.7K
R12
4.7K
C39
1nF
C39
1nF
C35
0.1u
FC
350.
1uF
C49
0.1u
F
C49
0.1u
FC
420.
1uF
C42
0.1u
F
1 122
3 344
5 566
7 788
RP
27
4x 1
8K
RP
27
4x 1
8K
C50
10nF
C50
10nF
1 122
3 344
5 566
7 788
RP
7
4x 5
1
RP
7
4x 5
1
R13
6.49
K 1
%
R13
6.49
K 1
%
C43
0.1u
FC
430.
1uF
R18
220
R18
220
11
22
33
44
55
66
77
88
RP
44x
51
RP
44x
51
C38
0.1u
FC
380.
1uF
C51
10uF
C51
10uF
R14
10K
R14
10K
C36
0.1u
FC
360.
1uF
R11
49.9
1%
R11
49.9
1%
C47
0.1u
FC
470.
1uF
12
FB
1
ST
EW
AR
D H
I120
6T50
0R-0
0
FB
1
ST
EW
AR
D H
I120
6T50
0R-0
0
D2
D2
TX
+1
TX
-2
RX
+3
CT
_TX
4
CT
_RX
5
RX
-6
NC
7
GN
D8
J2 Hal
o H
FJ1
1-24
50E
J2 Hal
o H
FJ1
1-24
50E
R8
49.9
1%
R8
49.9
1%
1 122
3 344
5 566
7 788
RP
6
4x 5
1
RP
6
4x 5
1
12
FB
2
ST
EW
AR
D H
I120
6T50
0R-0
0
FB
2
ST
EW
AR
D H
I120
6T50
0R-0
0
C48
0.1u
FC
480.
1uF
11
22
33
44
55
66
77
88
RP
54x
51
RP
54x
51
D1
D1
R16
220
R16
220
C41
47uF
C41
47uF
C40
0.1u
FC
400.
1uF
D3
D3
C44
0.1u
FC
440.
1uF
R10
49.9
1%
R10
49.9
1%
R9
49.9
1%
R9
49.9
1%
MD
IO1
MD
C2
RX
D3/
PH
YA
D1
3
RX
D2/
PH
YA
D2
4
RX
D1/
PH
YA
D3
5
RX
D0/
PH
YA
D4
6
VD
DIO
7
GN
D8
RX
DV
/PC
S_L
PB
K9
RX
C1
0
RX
ER
/ISO
11
GN
D1
2
VDDC 13
TXER 14
TXC/REFCLK 15
TXEN 16
TXD0 17
TXD1 18
TXD2 19
TXD3 20
COL/RMII 21
CRS/RMII_LPBK 22
GND 23
VDDIO 24INT
#/P
HY
AD
02
5LE
D0/
TE
ST
26
LED
1/S
PD
100
27
LED
2/D
UP
LEX
28
LED
3/N
WA
YE
N2
9P
D#
30
VD
DR
X3
1R
X-
32
RX
+3
3F
XS
D/F
XE
N3
4G
ND
35
GN
D3
6
REXT37VDDRCV38
GND39TX-40TX+41
VDDTX42GND43GND44
XO45XI46
VDDPLL47RST#48
U11
KS
8721
BL
U11
KS
8721
BL
R15
220
R15
220
R17
220
R17
220
C37
1nF
C37
1nF
D4
D4
C45
47uF
C45
47uF
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ree
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tor,
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c..
.
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
AN
6
TP
UC
H1
TP
UC
H2
TP
UC
H3
TP
UC
H4
TC
RC
LK
AN
7
TP
UC
H29
TP
UC
H13
TP
UC
H7
LTP
UO
DIS
TP
UC
H22
TP
UC
H30
TP
UC
H4
TP
UC
H16
TP
UC
H19
TP
UC
H10
TP
UC
H5
TP
UC
H12
TP
UC
H31
TP
UC
H7
TP
UC
H9
TP
UC
H5
TP
UC
H23
TP
UC
H20
TP
UC
H26
TP
UC
H8
TP
UC
H2
TP
UC
H11
TP
UC
H24
TP
UC
H12
TP
UC
H11
TP
UC
H10
TP
UC
H27
TP
UC
H8
TP
UC
H17
TP
UC
H6
TP
UC
H1
TP
UC
H3
TP
UC
H25
TP
UC
H9
TP
UC
H21
TP
UC
H28
TP
UC
H0
TP
UC
H15
TP
UC
H10
TP
UC
H13
TP
UC
H6
TP
UC
H18
TP
UC
H14
TP
UC
H[1
5:0]
TP
UC
H8
TP
UC
H9
TP
UC
H11
TP
UC
H12
TP
UC
H13
TP
UC
H4
TP
UC
H3
TP
UC
H2
TP
UC
H1
AN
5
AN
0A
N1
TP
UC
H14
TP
UC
H[1
5:0]
AN
4A
N3
AN
2
TP
UC
H15
TS
IZ1
/TE
A
TS
IZ0
/TIP
QS
PI_
DIN
QS
PI_
SC
K
QS
PI_
DO
UT
TC
RC
LK
UT
PU
OD
IS
TP
UC
H[3
1:16
]
LTP
UO
DIS
TP
UC
H[1
5:0]
QS
PI_
PC
S0
VS
SA
+3.
3V
+5V
+3.
3V+
5V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
VS
SA
VS
SA
+3.
3V+5
VA
+5V
A
VS
SA
+3.
3V
+3.
3V
+3.
3V
VS
SA
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+5V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+5V
+3.
3V
VS
SA
VS
SA
+3.
3V
+3.
3V
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
eT
PU
con
nect
ors
and
AD
CB
M52
3xE
VB
C
916
Frid
ay, A
pril
30, 2
004
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
eT
PU
con
nect
ors
and
AD
CB
M52
3xE
VB
C
916
Frid
ay, A
pril
30, 2
004
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
eT
PU
con
nect
ors
and
AD
CB
M52
3xE
VB
C
916
Frid
ay, A
pril
30, 2
004
Zer
o_cr
oss_
B
She
ildin
g
I_se
nse_
DC
B
PW
M_B
T
Zer
o_cr
oss_
A
PW
M_A
B
BE
MF
_sen
se_C
I_se
nse_
A
UN
I3 c
onne
ctio
n
BE
MF
_sen
se_B
I_se
nse_
BI_
sens
e_C
BE
MF
_sen
se_A
PW
M_C
B
PW
M_A
T
She
ildin
g
She
ildin
g
She
ildin
g
She
ildin
g
Zer
o_cr
oss_
C
PW
M_C
TS
heild
ing
She
ildin
g
V_s
ense
_DC
B_3
.3
PW
M_B
B
Ove
rcur
rent
com
para
tor
Hal
l sen
sors
/Enc
oder
con
nect
or
But
tons
& s
witc
h
Yel
low
led:
PW
M_A
B, P
WM
_BB
, PW
M_C
B
Gre
en le
d: P
WM
_AT
, PW
M_B
T, P
WM
_CT
, LE
D_S
TA
TU
S
Red
led:
I_D
CB
_FA
ULT
Ple
ase
ensu
re th
ere
is th
icke
r ga
uge
copp
er
betw
een
Vou
t on
U13
and
RE
FIN
on
U12
.
Ple
ase
ensu
re V
SS
A h
as a
pla
ne o
f cop
per
unde
r J4
, U11
& U
12.
Pla
ce C
87 a
ndC
88 a
s cl
ose
as p
ossi
ble
topi
ns 1
& 2
on
J6
Usi
ng G
PIO
(se
cond
ary
func
tion
on th
e /T
EA
pin
)
Usi
ng G
PIO
(se
cond
ary
func
tion
on th
e T
SIZ
0 pi
n)
Usi
ng G
PIO
(se
cond
ary
func
tion
on th
e T
SIZ
1 pi
n)
Usi
ng G
PIO
(sec
onda
ry fu
nctio
non
the
/TIP
pin
)
EX
OR
Log
ic G
ate
Inve
rter
Inve
rter
Pla
ce C
86 a
scl
ose
to U
17 a
spo
ssib
le
Pla
ce C
69 a
scl
ose
to U
16as
pos
sibl
e
AN
D G
ate
Logi
c
Pla
ce C
65as
clo
se to
U14
as
poss
ible
Pla
ce C
89as
clo
se to
U18
as
poss
ible
PW
M_A
T
PW
M_A
B
PW
M_B
T
PW
M_C
B
PW
M_C
T
PW
M_B
B
LED
_ST
AT
US
I_D
CB
_FA
ULT
Pla
ce th
ese
resi
stor
s at
an
acce
sibl
epo
int t
o al
low
rem
oval
if re
quire
d.
Pla
ce th
ese
zero
ohm
res
isto
rs a
s cl
ose
to th
e ju
nctio
nw
ith th
e eT
PU
sig
nals
as
poss
ible
and
at a
n ac
cess
ible
poin
t to
allo
w r
emov
al if
req
uire
d.
Pla
ce C
67 a
scl
ose
to U
15as
pos
sibl
e
Pla
ce th
e ca
paci
tors
& r
esis
tors
imm
edia
tely
bel
ow a
s cl
ose
aspo
ssib
le to
the
Vin
X p
ins
on U
12, a
s th
ey r
epre
sent
an
RC
filte
rfo
r th
e A
DC
inpu
ts.
Ple
ase
plac
e H
S/E
NC
0 on
the
silk
scre
en c
lose
to J
6
Ple
ase
plac
e U
NI3
on
the
silk
scre
en c
lose
to J
4
AD
C H
eade
r
eTP
U H
eade
r
HS
/EN
CO
Hea
der
-UP
-DO
WN
Mot
orol
a S
PS
TS
PG
- T
EC
D C
oldF
ire G
roup
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hip
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mpe
r, d
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lt F
ITT
ED
defa
ult F
ITT
ED
R65
1K8
R65
1K8
R44
270
R44
270
C65
100n
FC
6510
0nF
R19
0R
190
C78
0.1u
F
C78
0.1u
F
C86
100n
FC
8610
0nF
D11
D11
R33
120
R33
120
D7
D7
C57
0.1u
F
C57
0.1u
F
C92
470p
FC
9247
0pF
R56
1kR56
1k
R45
270
R45
270
R63
1kR63
1k
R54
1K8
R54
1K8
R53
24R
5324
C84
0.1u
F
C84
0.1u
F
B A GN
D
VC
C Y
U14
NL1
7SZ
08
U14
NL1
7SZ
08
C58
2.2n
F
C58
2.2n
F
C69
100n
FC
6910
0nF
R49
4K7
R49
4K7
C67
100n
FC
6710
0nF
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1
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2
TE
MP
3
GN
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TR
IM5
Vou
t6
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72.
5/3.
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AD
780B
R
U13
AD
780B
R
C89
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FC
8910
0nF
C56
10uF
C56
10uF
1A1
1Y2
2A3
2Y4
3A5
3Y6
GN
D7
4Y8
4A9
5Y10
5A11
6Y12
6A13
VC
C14
U17
SN
74H
C04
D
U17
SN
74H
C04
D
12
JP30
JP30
C80
0.1u
F
C80
0.1u
F
R48
270
R48
270
R64
24R
6424
R58
1K8
R58
1K8
D6
D6
C91
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FC
9147
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Out
putA
1
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tA2
Inpu
tA3
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tB5
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Out
putB
7V
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U15
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3MR37
1MR
371M
C85
0.1u
F
C85
0.1u
F
R32
0R
320
C64
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F
C64
2.2n
F
R50
270
R50
270
+C
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+C
872.
2uF
C63
2.2n
F
C63
2.2n
F
C70
1nF
C70
1nF
C62
2.2n
F
C62
2.2n
F
C55
0.1u
F
C55
0.1u
F
C61
2.2n
F
C61
2.2n
F
C68
100n
FC
6810
0nF
C60
2.2n
F
C60
2.2n
F
R52
1kR52
1k
R34
120
R34
120
C59
2.2n
F
C59
2.2n
F
R35
120
R35
120
C71
1nF
C71
1nF
R47
270
R47
270
R62
1K8
R62
1K8
C72
1nF
C72
1nF
R36
120
R36
120
R24
0R
240
C54
10uF
C54
10uF
C81
0.1u
F
C81
0.1u
F
21 3
SW
1
RU
N/S
TO
P
SW
1
RU
N/S
TO
P
12
JP29
JP29
C73
1nF
C73
1nF
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
J5J5
C88
100n
FC
8810
0nF
12345678910111213141516171819202122232425262728293031323334353637383940J4
Mol
ex/3
9-26
-740
5
J4
Mol
ex/3
9-26
-740
5
C93
470p
FC
9347
0pF
R46
270
R46
270
R30
120
R30
120
R60
4K7
R60
4K7
R61
24R
6124
A1
B1
Y2
GN
D
VC
C Y1
B2
A2
U18
NL2
7WZ
86
U18
NL2
7WZ
86
R25
0R
250
R21
0R
210
C90
470p
FC
9047
0pF
13
2
R41
10K
R41
10K
D8
D8
C53
0.1u
F
C53
0.1u
F
R55
4k7
R55
4k7
C83
0.1u
F
C83
0.1u
F
SC
LK1
DIN
2
CS
3
AG
ND
4
AV
DD
5
AV
DD
6
RE
FIN
7
AG
ND
8
Vin
79
Vin
610
Vin
511
Vin
412
Vin
313
Vin
214
Vin
115
Vin
016
AG
ND
17D
OU
T18
Vdr
ive
19A
GN
D20
U12 AD
7928
BR
U
U12 AD
7928
BR
U
C79
0.1u
F
C79
0.1u
F
R23
0R
230
C17
9
2.2n
F
C17
9
2.2n
F
C66
10nF
C66
10nF
C82
0.1u
F
C82
0.1u
F
R22
0R
220
R43
270
R43
270
R42
270
R42
270
1 2 3 4 5 6
J6J6
1 2 3 4 5 6 7 8 9 10 11 12
J3J3
R59
1kR59
1k
R40
150
R40
150
C76
1nF
C76
1nF
C75
1nF
C75
1nF
R20
0R
200
D9
D9
R31
120
R31
120
D10
D10
C52
0.1u
F
C52
0.1u
F
13
24
SW
3
KS
11R
22C
QD
SW
3
KS
11R
22C
QD
C74
1nF
C74
1nF
R27
120
R27
120
13
24
SW
2
KS
11R
22C
QD
SW
2
KS
11R
22C
QD
R57
24R
5724
R26
120
R26
120
D12
D12
A1
GN
D
A2
Y1
VC
C Y2
U16
NL2
7WZ
04
U16
NL2
7WZ
04
C77
1nF
C77
1nF
R51
1k8
R51
1k8
R38
22K
R38
22K
R39
100
R39
100
D5
D5
For More Information On This Product,
Go to: www.freescale.com
F
ree
sca
le S
em
ico
nd
uc
tor,
I
Freescale Semiconductor, Inc.n
c..
.
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
TP
UC
H7
TP
UC
H8
TP
UC
H12
TP
UC
H11
D28
D24
D25
D19
D16
TP
UC
H26
TP
UC
H29
TP
UC
H28
TP
UC
H31
TP
UC
H30
CLK
MO
D1
D31
D26
D27
D13
A9
A7
A20
A19
A3
DD
AT
A3
A0
A5
A16
A22
A17
A14
A4
A8
/CS2
/CS6
TPUCH20TPUCH21
TPUCH1
TPUCH2
TPUCH24
TPUCH5
TPUCH6
TPUCH16
/BS1
TPUCH23
D7D11
PST1 PST2
/IRQ2
D3
DDATA1
D1
/IRQ1
/IRQ6
DDATA2
D8
DDATA0
D4
D0
D5
TP
UC
H[1
5:0]
TP
UC
H[1
5:0]
TP
UC
H[1
5:0]
TP
UC
H10
TP
UC
H9
TP
UC
H[3
1:16
]T
PU
CH
[31:
16]
TP
UC
H25
TP
UC
H27
TP
UC
H14
TP
UC
H13
TP
UC
H15
CLK
MO
D0
D[3
1:0]
D[3
1:0]
D[3
1:0]
D29
D30
D23
D21
D22
D20
D17
D18
D9
D12
D15
D[3
1:0]
D14 D10D6
D2
/IRQ
[7:1
]
/IRQ
[7:1
]
/IRQ7
/IRQ3 /IRQ4/IRQ5
/IRQ
[7:1
]
PS
T[3
:0]
PS
T[3
:0]
PS
T[3
:0]
PST0
PST3
DD
AT
A[3
:0]
DD
AT
A[3
:0]
DD
AT
A[3
:0]
A[2
3:0]
A[2
3:0]
A[2
3:0]
A2
A1
A12
A6
A10
A11
A13
A15
A18
A21
/CS
[7:0
]
/CS4
/CS
[7:0
]
/CS1
/CS3
A23/CS0/CS5/CS7
/CS
[7:0
]
/BS
[3:0
]
/BS0
/BS2/BS3
TPUCH0TPUCH19
TPUCH22TPUCH18TPUCH17
TPUCH3
TPUCH4
TP
UC
H[1
5:0]
TP
UC
H[3
1:16
]
TC
RC
LK
/U0C
TS
U0R
XD
DT
OU
T0
DT
IN0
U0T
XD
/U0R
TS
CLK
MO
D[1
:0]
D[3
1:0]
/OEDTOUT1
DTIN1
/IRQ
[7:1
]
TSIZ0
TCLK/PSTCLKDTOUT2 DTIN2
TDI/DSITDO/DSO TMS/BKPT
TRST/DSCLK
PS
T[3
:0]
DD
AT
A[3
:0]
JTAG_EN /RCON/RSTOUT
/RESET
EX
TA
LX
TA
L/S
D_C
S1
CLK
OU
T/S
D_C
AS
/SD
_CS
0/S
D_R
AS
R/W
CA
N0T
XC
AN
0RX
/SD
_W
E/T
S/T
IP/T
A/T
EA
DT
OU
T3
DT
IN3
LTP
UO
DIS
UT
PU
OD
IS
A[2
3:0]
/CS
[7:0
]
TSIZ1
U1TXDU1RXD/U1RTS
U2TXD
/U1CTSU2RXD
CAN1RXSD_SCKE
QSPI_PCS1/U2RTS
/BS
[3:0
]
QSPI_PCS0QSPI_DOUT
QSPI_DINI2C_SDA
QSPI_SCKI2C_SCL
EMDCEMDIO
/EX
T_R
ST
IN
CAN1TX
/U2CTS
+3.
3V+
1.5V
+3.
3V+
5V+
3.3V
+1.
5V+
3.3V
+5V
+3.
3V
+1.
5V
+3.
3V +5V
+3.
3V+5V
+1.
5V
+3.
3V
+5V
+3.
3V
+1.
5V
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
Exp
ansi
on C
onne
ctor
sB
M52
3xE
VB
C
1016
Frid
ay, A
pril
30, 2
004
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
Exp
ansi
on C
onne
ctor
sB
M52
3xE
VB
C
1016
Frid
ay, A
pril
30, 2
004
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
Exp
ansi
on C
onne
ctor
sB
M52
3xE
VB
C
1016
Frid
ay, A
pril
30, 2
004
NO
TE
: if d
esig
ning
a d
augh
ter
card
to fi
t the
se e
xpan
sion
con
nect
ors
plea
se e
nsur
e al
l sig
nals
are
buf
fere
d on
the
daug
hter
car
d. Mot
orol
a S
PS
TS
PG
- T
EC
D C
oldF
ire G
roup
C95
10nF
C95
10nF
C96
470p
FC
9647
0pF
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
J8 AM
P 1
7798
3-2
J8 AM
P 1
7798
3-2
2468
1012141618202224262830323436384042444648505254565860
1357911131517192123252729313335373941434547495153555759
J10 AM
P 1
7798
3-2
J10 AM
P 1
7798
3-2
C10
9
470p
F
C10
9
470p
F
C10
8
470p
F
C10
8
470p
F
C10
7
470p
F
C10
7
470p
F
C10
6
470p
F
C10
6
470p
F
C97
470p
FC
9747
0pF
C10
5
10nF
C10
5
10nF
C10
4
10nF
C10
4
10nF
C10
1
0.1u
F
C10
1
0.1u
F
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
J9 AM
P 1
7798
3-2
J9 AM
P 1
7798
3-2
C10
2
10nF
C10
2
10nF
C10
3
10nF
C10
3
10nF
2468
1012141618202224262830323436384042444648505254565860
1357911131517192123252729313335373941434547495153555759
J7 AM
P 1
7798
3-2
J7 AM
P 1
7798
3-2
C94
10nF
C94
10nF
C98
1nF
C98
1nF
C99
1nF
C99
1nF
C10
0
0.1u
F
C10
0
0.1u
F
For More Information On This Product,
Go to: www.freescale.com
F
ree
sca
le S
em
ico
nd
uc
tor,
I
Freescale Semiconductor, Inc.n
c..
.
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
B_D
[31:
0]
B_A
14B
_A2
B_A
21
B_A
8
B_A
19
B_A
9
B_A
20
B_A
17
B_A
6
B_A
4
B_A
7
B_A
5B
_A11
B_A
10
B_A
18
B_A
16
B_A
12
B_A
15
B_A
3
B_A
13
B_A
[23:
0]B
_A[2
3:0]
B_A
[23:
0]
B_D
31B
_D23
B_D
22B
_D29
B_D
21B
_D28
B_D
16B
_D24
B_D
17B
_D25
B_D
18B
_D26
B_D
19B
_D27
B_D
20
B_D3
B_D4
B_D16
B_D26
B_D27
B_D
[31:
0]
B_D10
B_D18
B_D20
B_D11
B_D13
B_D14
B_D24
B_D25
B_D12
B_D
[31:
0]
B_D2
B_D5
B_D15 B_D0
B_D6
B_D22
B_D28
B_D31
B_D21
B_D1
B_D19
B_D7B_D8
B_D9
B_D30
B_D23
B_D29
B_D17
B_D
[31:
0]
B_D
[31:
0]
B_A
1B
_A2
B_A
3B
_A4
B_A
5B
_A6
B_A
7B
_A8
B_A
18B
_A19
/CS
0
B_A
[23:
0]
B_D
30
B_A
9B
_A10
B_A
11B
_A12
B_A
13B
_A14
B_A
15B
_A16
B_A
17
B_A
20
/OE
R/W
B_A
[23:
0]
B_D
[31:
0]/C
S[7
:0]
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
Fla
sh M
emor
y (F
ujits
u S
SO
P O
R A
MD
BG
A)
B
M52
3xE
VB
C
1116
Frid
ay, A
pril
30, 2
004
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
Fla
sh M
emor
y (F
ujits
u S
SO
P O
R A
MD
BG
A)
B
M52
3xE
VB
C
1116
Frid
ay, A
pril
30, 2
004
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
Fla
sh M
emor
y (F
ujits
u S
SO
P O
R A
MD
BG
A)
B
M52
3xE
VB
C
1116
Frid
ay, A
pril
30, 2
004
NO
TE
: The
writ
e pr
otec
t pin
(C
5)sh
ould
not
be
left
float
ing
asin
cons
ista
nt b
ehav
iour
of t
heF
lash
dev
ice
coul
d re
sult.
To
use
hard
war
e pr
otec
t on
the
top/
botto
m b
oot s
ecto
r se
t JP
32be
twee
n pi
ns 2
& 3
. To
disa
ble
hard
war
e pr
otec
t set
bet
wee
npi
ns 1
& 2
(de
faul
t).
Mot
orol
a S
PS
TS
PG
- T
EC
D C
oldF
ire G
roup
32M
Bit
Fla
shB
oot
Def
ault
setti
ng -
JP
31 fi
tted
acro
ss p
ins
1 &
2
Onl
y on
e or
the
othe
r fo
otpr
ints
will
be
popu
late
d -
BG
A (
U35
)O
R S
SO
P (
U19
)
16 M
Bit
Fla
sh B
oot
Def
ault
setti
ng -
JP
64fit
ted
acro
ss p
ins
1 &
2
Mem
ory
Siz
e: 1
M x
16-
bit =
2M
BM
emor
y S
ize:
1M
x 3
2-bi
t = 4
MB
R68
4.7K
R68
4.7K
C11
8
1nF
C11
8
1nF
1
2
3
JP32
JP32
R67
4.7KR67
4.7K
CE
A8
VS
SB
8
NC
A7
WO
RD
B7
OE
C7
WE
A6
NC
B6
NC
C6
NC
A5
AC
CB
5
WP
C5
NC
D5
NC
E5
A1
A4
A2
B4
A3
C4
A0
D4
A4
A3
A5
B3
VC
CB
2
DQ30B9
VCCC9
DQ15C8
DQ13D9
DQ29D8
DQ14D7
DQ31/A-1D6
DQ12E9
DQ28E8
VSSE7
NCE6
DQ27F9
DQ11F8
DQ10F7
NCF6
DQ26G9
VSSG8
DQ25G7
DQ8G6
VCCH9
DQ24H8
DQ9J9
A19
K8
VC
CJ8
A16
K7
A17
J7
A18
H7
A13
K6
A14
J6
A15
H6
NC
K5
NC
J5
NC
H5
NC
G5
NC
F5
A10
K4
A9
J4
A11
H4
A12
G4
A7
K3
A6
J3
A8
H3
VS
SK
2
DQ17 C1
DQ1 C2
VCC D1
VSS D2
DQ16 D3
DQ0 C3
DQ3 E1
DQ19 E2
DQ18 E3
DQ2 E4
DQ20 F1
DQ4 F2
DQ5 F3
NC F4
VSS G1
DQ6 G2
DQ21 G3
VCC H1
DQ22 J1
DQ23 J2
DQ7 H2
U35
Am
29P
L320
D
U35
Am
29P
L320
D
R69
4.7K
R69
4.7K
C11
01n
FC
110
1nF
C11
11n
FC
111
1nF
C11
21n
FC
112
1nF
C11
31n
FC
113
1nF
C12
0
0.1u
F
C12
0
0.1u
F
R66
4.7K
R66
4.7K
WE
#1
A18
2
A17
3
A7
4
A6
5
A5
6
A4
7
A3
8
A2
9
A1
10
A0
11
CE
#12
Vss
13
OE
#14
DQ
015
DQ
816
DQ
117
DQ
918
DQ
219
DQ
1020
DQ
321
DQ
1122
Vcc
23D
Q4
24D
Q12
25D
Q5
26D
Q13
27D
Q6
28D
Q14
29D
Q7
30D
Q15
/A-1
31V
ss32
BY
TE
#33
A16
34A
1535
A14
36A
1337
A12
38A
1139
A10
40A
941
A8
42A
1943
NC
44
U19
AM
D A
m29
PL1
60C
B-6
5RS
U19
AM
D A
m29
PL1
60C
B-6
5RS
C11
60.
1uF
C11
60.
1uF
1
2
3
JP64
JP64
C11
9
0.1u
F
C11
9
0.1u
FC11
50.
1uF
C11
50.
1uF
C11
40.
1uF
C11
40.
1uF
C11
70.
1uF
C11
70.
1uF
1
2
3
JP31
JP31
For More Information On This Product,
Go to: www.freescale.com
F
ree
sca
le S
em
ico
nd
uc
tor,
I
Freescale Semiconductor, Inc.n
c..
.
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
+3.
3VP
+5V
+3.
3V
+3.
3V
+3.
3V+
1.5V
+1.
5V+
1.5V
P
+5V
+1.
5V
VS
SP
LL
VS
SA+5V
+5V
A
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
Pow
er S
uppl
yB
M52
3xE
VB
B
1216
Frid
ay, A
pril
30, 2
004
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
Pow
er S
uppl
yB
M52
3xE
VB
B
1216
Frid
ay, A
pril
30, 2
004
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
Pow
er S
uppl
yB
M52
3xE
VB
B
1216
Frid
ay, A
pril
30, 2
004
Aug
at 2
5V-0
2
+
NO
TE
: the
pos
itive
term
inal
of e
ach
pow
er c
onne
ctor
mus
t be
show
n on
the
silk
scre
en o
f the
PC
B
-
2-w
ay B
are
Wire
Pow
er C
onne
ctor
JP33
SH
OU
LD B
EIN
ST
ALL
ED
DU
RIN
GA
SS
EM
BLY
DC
vol
tage
inpu
t ran
ge +
7 to
+14
V
5.0V
Reg
ulat
or
-
3.3V
Reg
ulat
or
+
Pow
er J
ack
Con
nect
or -
2.1m
m d
iam
eter
NO
TE
: Dio
des
prev
ent e
xces
sive
diffe
renc
e be
twee
n 3.
3V &
1.5
Vra
ils, a
t pow
er u
p
NO
TE
: Sch
ottk
y D
iode
pre
vent
s ex
cess
ive
diffe
renc
e be
twee
n 3.
3V &
1.5
Vra
ils, a
t pow
er d
own
JP34
SH
OU
LD B
EIN
ST
ALL
ED
DU
RIN
GA
SS
EM
BLY
1.5V
Reg
ulat
or
VS
SA
- a
nalo
g gr
ound
for
eTP
U c
hann
els
VS
SP
LL -
filte
red
grou
nd fo
r C
PU
PLL
mod
ule
Filt
ered
gro
und
for
plan
e fo
r et
hern
et R
J45
conn
ecto
r
+5V
A -
filte
red
pow
er fo
r eT
PU
AD
C
Mot
orol
a S
PS
TS
PG
- T
EC
D C
oldF
ire G
roup
1 2
P3
P3
21
D15
MB
RS
340T
3
D15
MB
RS
340T
3
C13
0
0.1u
F
C13
0
0.1u
F
12
FB
5F
B5
12
FB
4F
B4
VIN
3
ADJ 1
VO
UT
2
U22
LT10
86C
MU
22LT
1086
CM
D17
+5V
GR
EE
N P
OW
ER
LE
D
D17
+5V
GR
EE
N P
OW
ER
LE
D
21
D20
MB
RS
340T
3
D20
MB
RS
340T
3
R73
120
R73
120
R71 56
0
R71 56
0
R74
22R
7422
L2 25uH
L2 25uH
C12
133
0uF
C12
133
0uF
C12
20.
1uF
C12
20.
1uF
C12
633
0uF
C12
633
0uF
123
P2
Sw
itchc
raft
RA
PC
712
P2
Sw
itchc
raft
RA
PC
712
12
FB
6F
B6
12
JP33
JP33
54 6
21 3
SW
4
PO
WE
R S
W S
LID
E-S
PS
T(B
oard
Edg
e)
SW
4
PO
WE
R S
W S
LID
E-S
PS
T(B
oard
Edg
e)
21
D13
MB
RS
340T
3D
13M
BR
S34
0T3
VIN
1V
OU
T2
~O
N/O
FF
5
GND 3
FB
4
TAB 6
U20
LM25
96S
-3.3
U20
LM25
96S
-3.3
C12
3
0.1u
F
C12
3
0.1u
F
21
D22
MB
RS
340T
3
D22
MB
RS
340T
3
C12
810
uF T
AN
T.
C12
810
uF T
AN
T.
C12
70.
1uF
C12
70.
1uF
21
D16
MB
RS
340T
3D
16M
BR
S34
0T3
12
JP34
JP34
C12
933
0uF
C12
933
0uF
D18
MR
A40
03T
3
D18
MR
A40
03T
3
D14 +3.
3V G
RE
EN
PO
WE
R L
ED
D14 +3.
3V G
RE
EN
PO
WE
R L
ED
C12
510
00uF
C12
510
00uF
R70
270
R70
270
D21
+1.
5V G
RE
EN
PO
WE
R L
ED
D21
+1.
5V G
RE
EN
PO
WE
R L
ED
D19 M
RA
4003
T3
D19 M
RA
4003
T3
12
FB
3F
B3
L3
25uH
L3
25uH
R72
22R72
22
F1
5A F
ast b
low
.
F1
5A F
ast b
low
.
C12
4
1nF
C12
4
1nF
VIN
1V
OU
T2
~O
N/O
FF
5
GND 3
FB
4
TAB 6
U21
LM25
96S
-5U
21LM
2596
S-5
For More Information On This Product,
Go to: www.freescale.com
F
ree
sca
le S
em
ico
nd
uc
tor,
I
Freescale Semiconductor, Inc.n
c..
.
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
/IRQ
7/IR
Q[7
:1]
D16
D20
D[3
1:0]
D19
D25
D24
D21
CLK
MO
D[1
:0]
CLK
MO
D1
CLK
MO
D0
/IRQ
2
/CS
6/C
S5
/IRQ
7/C
S7
/IRQ
6
/IRQ
[7:1
]
/CS
4/IR
Q5
/CS
3/IR
Q3
/IRQ
1
/CS
2
/IRQ
4
/CS
0
/CS
[7:0
]
/CS
0/C
S1
/BS
[3:0
]
/BS
0/B
S1
/BS
2/B
S3
/RE
SE
T/B
DM
_RS
TIN
/EX
T_R
ST
IN
ET
H_C
LK
XT
AL
/IRQ
[7:1
]
JTA
G_E
N
/RS
TO
UT
D[3
1:0]
/RC
ON
CLK
MO
D[1
:0]
/RS
TO
UT
/CS
[7:0
]
R/W
/BS
[3:0
]
TD
I/DS
I/O
ET
DO
/DS
O
/IRQ
[7:1
]
/TA
TR
ST
/DS
CLK
TS
IZ0
TM
S/B
KP
T
TS
IZ1
CLK
OU
T
/TS
/TA
/CS
[7:0
]
R/W
/OE
/TE
A
/TIP
/TS
EX
TA
L
UT
PU
OD
ISLT
PU
OD
IS
DT
OU
T2
DT
OU
T3
DT
OU
T1
DT
OU
T0
DT
IN2
DT
IN1
DT
IN0
DT
IN3
ET
PU
/ET
H
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V+
3.3V
VS
SP
LL
VS
SP
LL
VS
SP
LL
+3.
3V
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
Res
et C
onfig
urat
ion
& C
lock
sel
ectio
nB
M52
3xE
VB
C
1316
Frid
ay, A
pril
30, 2
004
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
Res
et C
onfig
urat
ion
& C
lock
sel
ectio
nB
M52
3xE
VB
C
1316
Frid
ay, A
pril
30, 2
004
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
Res
et C
onfig
urat
ion
& C
lock
sel
ectio
nB
M52
3xE
VB
C
1316
Frid
ay, A
pril
30, 2
004
AB
OR
T/-
INT
7
DE
BO
UN
CE
D /I
RQ
7S
IGN
AL
HA
RD
RE
SE
T &
VO
LTA
GE
SE
NS
E C
ON
TR
OLL
ER
Buf
fere
d an
d "O
R'd
" /R
ST
I sig
nal t
o th
e C
PU
from
the
BD
M p
ort,
expa
nsio
n co
nnec
tors
or
rese
t sw
itch.
NO
TE
: sig
nal t
rack
leng
ths
betw
een
thes
e cl
ock
circ
uits
and
the
MC
F52
3x s
houl
d be
min
imis
ed.
OS
CIL
LAT
OR
- d
ual l
ayou
t foo
tprin
tfo
r 8
AN
D 1
4 pi
n so
cket
ed D
IL o
sc.'s
D24
D21
D20
D19
D16
CLK
MO
D0
CLK
MO
D1
JTA
G_E
NR
CO
N
IMP
OR
TA
NT
NO
TE
: TH
E /R
ST
OU
T S
IGN
AL
MU
ST
BE
US
ED
TO
DR
IVE
TH
E O
UT
PU
T E
NA
BLE
PIN
S O
F U
7 T
O A
LLO
W T
HE
D16
, D17
, D18
, D19
, D21
, D24
, D25
& D
26 S
IGN
ALS
TO
BE
LA
TC
HE
D C
OR
RE
CT
LY B
YT
HE
MC
F52
3x F
OR
CO
NF
IGU
RA
TIO
N A
T R
ES
ET
.
Clo
sed/
On
Ope
n/O
ff
D25
Enc
oded
Add
ress
/Chi
p S
elec
t Mod
eS
W7-
9
SW
7-10
Mod
e--
----
----
-
--
----
----
-
--
----
----
----
----
----
----
O
FF
OF
F
P
F[7
:5] =
/CS
[6:4
]
OF
F
O
N
PF
7 =
/CS
6, P
F[6
:5] =
A[2
2:21
]
ON
O
FF
PF
[7:6
] = /C
S[6
:5],
PF
[5] =
A21
O
N
ON
P
F[7
:5] =
A[2
3:21
]
NO
TE
: Ple
ase
plac
e th
ese
tabl
es o
n th
e si
lksc
reen
on
the
tops
ide
of th
e P
CB
clo
se to
SW
7.
Enc
oded
Boo
t Dev
ice
(Por
t Siz
e)S
W7-
6
SW
7-7
Mod
e--
----
----
-
--
----
----
-
--
----
----
----
----
----
----
O
FF
O
FF
Ext
erna
l (32
-bit)
O
FF
O
N
E
xter
nal (
16-b
it)
ON
O
FF
Ext
erna
l (8-
bit)
O
N
O
N
E
xter
nal (
32-b
it)
Enc
oded
Ope
ratin
g M
ode
SW
7-5
M
ode
----
----
---
----
----
---
O
FF
Res
erve
d
ON
M
aste
r
Enc
oded
Clo
ck M
ode
SW
7-3
S
W7-
4
M
ode
----
----
---
-
----
----
--
-
----
----
----
----
----
----
----
----
----
----
----
----
-
OF
F
O
FF
Ext
erna
l Clo
ck -
(N
o P
LL)
O
FF
ON
1:
1 P
LL
ON
O
FF
Nor
mal
PLL
ope
ratio
n (E
xt. C
lock
)
ON
O
N
Nor
mal
PLL
ope
ratio
n (E
xt. C
ryst
al)
----
----
----
----
----
----
OF
F -
SW
7 -
ON
-
----
----
----
----
----
---
Chi
p C
onfig
. Off
1
C
hip
Con
fig. O
nJT
AG
Inte
rfac
e E
nabl
ed
2
BD
M In
terf
ace
Ena
bled
Enc
oded
Clo
ck M
ode
3
Enc
oded
Clo
ck M
ode
Enc
oded
Clo
ck M
ode
4
Enc
oded
Clo
ck M
ode
Enc
oded
Ope
r. M
ode
5
Enc
oded
Ope
r. M
ode
Enc
oded
Boo
t Dev
ice
6
E
ncod
ed B
oot D
evic
eE
ncod
ed B
oot D
evic
e
7
Enc
oded
Boo
t Dev
ice
Par
tial B
us D
rive
8
Ful
l Bus
Driv
eE
ncod
ed A
ddre
ss M
ode
9
Enc
oded
Add
ress
Mod
eE
ncod
ed A
ddre
ss M
ode
10
E
ncod
ed A
ddre
ss M
ode
Eth
erne
t Ena
bled
11
e
TP
U E
nabl
ed
Not
e: d
efau
lt se
tting
for
SW
7 is
all
switc
hes
clos
ed/o
n.
Impo
rtan
t Not
e -
all u
ncon
nect
ed p
ull-u
p an
d pu
ll-do
wn
resi
stor
pac
k co
nnec
tions
, on
all s
chem
atic
s pa
ges,
nee
dto
be
conn
ecte
d to
an
unm
aske
d vi
a.
NO
TE
: Pla
ce T
P9,
TP
10, T
P11
& T
P12
at t
he c
orne
rs o
f the
PC
Bto
allo
w e
asy
conn
ectio
n of
'sco
pe p
robe
gro
und
lead
s.
NO
TE
: Ple
ase
plac
e D
25 th
roug
h D
32 to
geth
er in
a li
ne.
DT
IN0
LED
DT
IN1
LED
DT
IN2
LED
DT
IN3
LED
DT
OU
T0
LED
DT
OU
T1
LED
DT
OU
T2
LED
DT
OU
T3
LED
Cry
stal
Ena
ble
Def
ault
setti
ng fo
r JP
38 th
roug
h JP
45 is
fitte
d.
Ext
erna
l Clo
ck In
put (
SM
A c
onne
ctor
)
Pla
ce T
P6
ascl
ose
to E
XT
AL
as p
ossi
ble
Eth
erne
t/eT
PU
Mod
e (e
TP
U c
hann
els
16 to
31)
SW
7-11
M
ode
----
----
---
----
----
---
O
FF
eT
PU
ena
bled
O
N
Eth
erne
t ena
bled
DO
NO
TP
OP
ULA
TE
Mot
orol
a S
PS
TS
PG
- T
EC
D C
oldF
ire G
roup
OE
11
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
GN
D10
O7
11O
612
O5
13O
414
O3
15O
216
O1
17O
018
OE
219
VC
C20
U27
MC
74LC
X54
1DT
U27
MC
74LC
X54
1DT
11
22
33
44
55
66
77
88
RP
10
4x 4
.7K
RP
10
4x 4
.7K
1TP
11
GR
OU
ND
TP
11
GR
OU
ND
SW
6
KS
11R
23C
QD
RE
SE
T
SW
6
KS
11R
23C
QD
RE
SE
T
11
22
33
44
55
66
77
88
RP
11
4x 4
.7K
RP
11
4x 4
.7K
OE
1
GN
D7
CLK
8
VD
D14
OE
4V
DD
11
U23
25M
Hz
U23
25M
Hz
1TP
10
GR
OU
ND
TP
10
GR
OU
ND
R78
270
R78
270
12
JP40
JP40
11
22
33
44
55
66
77
88
RP
12
4x 4
.7K
RP
12
4x 4
.7K
1 122
3 344
5 566
7 788
RP
13
4x 1
0K
RP
13
4x 1
0K1
2
3
JP35
JP35
11
22
33
44
55
66
77
88
RP
20
4x 4
.7K
RP
20
4x 4
.7K
D32
D32
SW
5
KS
11R
22C
QD
SW
5
KS
11R
22C
QD
MR
1
VC
C2
GN
D3
PF
I4
PF
O5
N.C
.6
RE
SE
T7
RE
SE
T8
U25
AD
M70
8SA
R
U25
AD
M70
8SA
R
11
22
33
44
55
66
77
88
RP
16
4x 4
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RP
16
4x 4
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MR
1
VC
C2
GN
D3
PF
I4
PF
O5
N.C
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RE
SE
T7
RE
SE
T8
U24
AD
M70
8SA
R
U24
AD
M70
8SA
R
1TP9
GR
OU
ND
TP9
GR
OU
ND
11
22
33
44
55
66
77
88
RP
15
4x 4
.7K
RP
15
4x 4
.7K
11
22
33
44
55
66
77
88
RP
9
4x 4
.7K
RP
9
4x 4
.7K
1
2345
J11
J11
SW
7
Con
figur
atio
n D
IP s
witc
h -
Gra
yhill
78R
B12
SW
7
Con
figur
atio
n D
IP s
witc
h -
Gra
yhill
78R
B12
11
22
33
44
55
66
77
88
RP
14
4x 4
.7K
RP
14
4x 4
.7K
D28
D28
D29
D29
12
JP44
JP44
D23
RE
D -
INT
7 L
ED
D23
RE
D -
INT
7 L
ED
R75
270
R75
270
12
JP38
JP38
A GN
DB
CV
CC Y
U26
SN
74LV
C1G
11
U26
SN
74LV
C1G
11
D25
D25
R77
100
R77
100
R80
1KR80
1K
R76
10K
R76
10K
1 122
3 344
5 566
7 788
RP
19
4x 1
0
RP
19
4x 1
0
Y1 25
MH
z
Y1 25
MH
z
C13
210
pFC
132
10pF
12
JP39
JP39
12
JP42
JP42
1TP5
CH
IP S
ELE
CT
0
TP5
CH
IP S
ELE
CT
0
12
JP41
JP41
12
JP43
JP43
1TP7
TR
AN
SF
ER
AC
KN
OW
LED
GE
TP7
TR
AN
SF
ER
AC
KN
OW
LED
GE
C13
110
pFC
131
10pF
12
JP45
JP45
D30
D30
1TP3
OU
TP
UT
EN
AB
LE
TP3
OU
TP
UT
EN
AB
LE
1TP
12
GR
OU
ND
TP
12
GR
OU
ND
D31
D31
1TP2
TR
AN
SF
ER
ST
AR
T
TP2
TR
AN
SF
ER
ST
AR
T
1
2
3
JP36
JP36
11
22
33
44
55
66
77
88
RP
21
4x 4
.7K
RP
21
4x 4
.7K
1TP4
RE
AD
NO
T W
RIT
E
TP4
RE
AD
NO
T W
RIT
E
D24
RE
D R
ES
ET
LE
DD
24R
ED
RE
SE
T
LED
R79
100
R79
100
12
JP37
JP37
11
22
33
44
55
66
77
88
RP
8
4x 4
.7K
RP
8
4x 4
.7K
11
22
33
44
55
66
77
88
RP
22
4x 4
.7K
RP
22
4x 4
.7K
1TP6
CP
U C
LOC
K I/
P
TP6
CP
U C
LOC
K I/
P
D26
D26
D27
D27
11
22
33
44
55
66
77
88
RP
17
4x 4
.7K
RP
17
4x 4
.7K
1TP8
CP
U C
LOC
K O
/P
TP8
CP
U C
LOC
K O
/P
1 122
3 344
5 566
7 788
RP
18
4x 1
0
RP
18
4x 1
0
For More Information On This Product,
Go to: www.freescale.com
F
ree
sca
le S
em
ico
nd
uc
tor,
I
Freescale Semiconductor, Inc.n
c..
.
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
A13
D5 A
23
D27
D2
D13
D20
D[3
1:0]
A20
D4
A11
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[3:0
]
A17
D23
A[2
3:0]
D24
D3 A
12A
11
A12
D6
D25
A21
A17
A9
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3 /BS
1
D17
D28
D9
D11
D8
D19
A13
D21
D26
/BS
2
A14
D16
A22
/BS
0
D7
A10
D0A
20
D15
A19
D10
D31
A19
D14
A22
A10
D30
D12
A[2
3:0]
A15
A23
D29
D18 D
1
A18
D[3
1:0]
A9
A21
A14
A15
A18
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[3:0
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0
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SC
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UT
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S
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3:0]
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3:0]
+3.
3V
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3V
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3V+
3.3V
+3.
3V
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
SD
RA
MB
M52
3xE
VB
B
1416
Frid
ay, A
pril
30, 2
004
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
SD
RA
MB
M52
3xE
VB
B
1416
Frid
ay, A
pril
30, 2
004
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
SD
RA
MB
M52
3xE
VB
B
1416
Frid
ay, A
pril
30, 2
004
SD
RA
M U
pper
16-
bit W
ord.
SD
RA
M L
ower
16-
bit W
ord.
NO
TE
: Mem
ory
size
: Eac
h S
DR
AM
mem
ory
is c
onfig
ured
4M
x 1
6bit
(8M
B).
Tot
al a
vaila
ble
SD
RA
M is
16M
B.
NO
TE
: Alte
rnat
ive
SD
RA
M's
with
the
sam
e P
CB
foot
prin
t are
:S
amsu
ng K
4S64
1632
EH
yund
ai H
Y57
V64
1620
HG
Tos
hiba
TC
59S
6416
CF
TIn
fineo
n H
YB
39S
6416
0ET
Win
bond
W98
6416
DH
Mot
orol
a S
PS
TS
PG
- T
EC
D C
oldF
ire G
roup
C13
31n
FC
133
1nF
C13
41n
FC
134
1nF
C13
51n
FC
135
1nF
C13
61n
FC
136
1nF
VD
D1
DQ
02
VD
DQ
3
DQ
14
DQ
25
VS
SQ
6
DQ
37
DQ
48
VD
DQ
9
DQ
51
0
DQ
61
1
VS
SQ
12
DQ
71
3
VD
D1
4
DQ
ML
15
WE
#1
6
CA
S#
17
RA
S#
18
CS
#1
9
BA
02
0
BA
12
1
A10
22
A0
23
A1
24
A2
25
A3
26
VD
D2
7V
SS
28
A4
29
A5
30
A6
31
A7
32
A8
33
A9
34
A11
35
NC
36
CK
E3
7C
LK
38
DQ
MH
39
NC
40
VS
S4
1D
Q8
42
VD
DQ
43
DQ
94
4D
Q10
45
VS
SQ
46
DQ
114
7D
Q12
48
VD
DQ
49
DQ
135
0D
Q14
51
VS
SQ
52
DQ
155
3V
SS
54
U28
MT
48LC
4M16
A2T
G (
TS
OP
II 4
00 m
il)
U28
MT
48LC
4M16
A2T
G (
TS
OP
II 4
00 m
il)
VD
D1
DQ
02
VD
DQ
3
DQ
14
DQ
25
VS
SQ
6
DQ
37
DQ
48
VD
DQ
9
DQ
51
0
DQ
61
1
VS
SQ
12
DQ
71
3
VD
D1
4
DQ
ML
15
WE
#1
6
CA
S#
17
RA
S#
18
CS
#1
9
BA
02
0
BA
12
1
A10
22
A0
23
A1
24
A2
25
A3
26
VD
D2
7V
SS
28
A4
29
A5
30
A6
31
A7
32
A8
33
A9
34
A11
35
NC
36
CK
E3
7C
LK
38
DQ
MH
39
NC
40
VS
S4
1D
Q8
42
VD
DQ
43
DQ
94
4D
Q10
45
VS
SQ
46
DQ
114
7D
Q12
48
VD
DQ
49
DQ
135
0D
Q14
51
VS
SQ
52
DQ
155
3V
SS
54
U29
MT
48LC
4M16
A2T
G (
TS
OP
II 4
00 m
il)
U29
MT
48LC
4M16
A2T
G (
TS
OP
II 4
00 m
il)
C13
90.
1uF
C13
90.
1uF
C13
80.
1uF
C13
80.
1uF
C13
70.
1uF
C13
70.
1uF
C14
00.
1uF
C14
00.
1uF
For More Information On This Product,
Go to: www.freescale.com
F
ree
sca
le S
em
ico
nd
uc
tor,
I
Freescale Semiconductor, Inc.n
c..
.
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
/IRQ
[7:1
]/IR
Q1
QS
PI_
PC
S1
QS
PI_
PC
S0
U0R
XD
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TS
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TS
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TS
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QS
PI_
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QS
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SC
K
QS
PI_
PC
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I2C
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L
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A
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NH
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AN
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QS
PI_
PC
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U0T
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U2T
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TO
UT
+3.
3V
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3V+3.
3V
+3.
3V
+3.
3V
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3V
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3V
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3V
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3V
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3V+
3.3V
+3.
3V
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
Ser
ial I
/OB
M52
3xE
VB
C
1516
Frid
ay, A
pril
30, 2
004
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
Ser
ial I
/OB
M52
3xE
VB
C
1516
Frid
ay, A
pril
30, 2
004
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SC
H-2
0380
Ser
ial I
/OB
M52
3xE
VB
C
1516
Frid
ay, A
pril
30, 2
004
TE
RM
INA
L P
OR
T9-
WA
Y D
-TY
PE
(Fem
ale)
RS
232
Tra
nsce
iver
.
Def
ault
setti
ng fo
r JP
46 to
JP
49 is
fitte
d.
RS
232
Tra
nsce
iver
.
AU
XIL
IAR
Y P
OR
T 1
9-W
AY
D-T
YP
E(F
emal
e)
RS
232
Tra
nsce
iver
.
AU
XIL
IAR
Y P
OR
T 2
9-W
AY
D-T
YP
E(F
emal
e)
NO
TE
: the
I2C
bus
on
the
MC
F52
3xpr
oces
sor
is 3
.3V
tole
rant
onl
y. If
con
nect
ion
to a
5V
sys
tem
is r
equi
red
high
freq
uenc
yvo
ltage
leve
l shi
fters
will
be
requ
ired
betw
een
the
perip
hera
l and
pro
cess
or.
Def
ault
setti
ng fo
r JP
53 &
JP
54 is
NO
T fi
tted.
Def
ault
setti
ng fo
r JP
50 to
JP
52 is
fitte
d be
twee
n pi
ns 1
& 2
.
NO
TE
: Lab
el a
s "U
AR
T0"
and
"Ter
min
al"
NO
TE
: Lab
el a
s "U
AR
T1"
and
"Aux
iliar
y"
NO
TE
: Lab
el a
s "U
AR
T2"
and
"CA
N1"
I2C
0.1
" pi
tch
thru
' boa
rd c
onne
ctor
QS
PI 0
.1"
pitc
h th
ru' b
oard
con
nect
or
Mot
orol
a S
PS
TS
PG
- T
EC
D C
oldF
ire G
roup
C14
8
0.1u
F
C14
8
0.1u
F
C14
4
0.1u
F
C14
4
0.1u
F
5 9 4 8 3 7 2 6 1
P6
P6
C15
20.
1uF
C15
20.
1uF
C14
10.
1uF
C14
10.
1uF
12
JP53
JP53
C14
50.
1uF
C14
50.
1uF
1 2 3 4 5 6 7 8 9 10
J12
J12
C15
7
1nF
C15
7
1nF
11
22
33
44
55
66
77
88
RP
24
4x 4
.7K
RP
24
4x 4
.7K
11
22
33
44
55
66
77
88
RP
234x
4.7
KR
P23
4x 4
.7K
C15
00.
1uF
C15
00.
1uF
12
3
JP52
JP52
C14
60.
1uF
C14
60.
1uF
12
3
JP50
JP50
5 9 4 8 3 7 2 6 1
P5
P5
11
22
33
44
55
66
77
88
RP
254x
4.7
KR
P25
4x 4
.7K
12
JP46
JP46
C14
20.
1uF
C14
20.
1uF
12
3
JP51
JP51
12
JP47
JP47
12
JP48
JP48
12
JP49
JP49
12
JP54
JP54
C15
3
1nF
C15
3
1nF
RE
AD
Y1
C1+
2
V+
3
C1-
4
C2+
5
C2-
6
V-
7
T2O
UT
8
R2I
N9
R2O
UT
10IN
VA
LID
11T
2IN
12T
1IN
13F
OR
CE
ON
14
GN
D18
R1O
UT
15R
1IN
16T
1OU
T17
VC
C19
FO
RC
EO
FF
20
U30
MA
X32
25C
AP
or
ICL3
225C
A
U30
MA
X32
25C
AP
or
ICL3
225C
A
RE
AD
Y1
C1+
2
V+
3
C1-
4
C2+
5
C2-
6
V-
7
T2O
UT
8
R2I
N9
R2O
UT
10IN
VA
LID
11T
2IN
12T
1IN
13F
OR
CE
ON
14
GN
D18
R1O
UT
15R
1IN
16T
1OU
T17
VC
C19
FO
RC
EO
FF
20
U31
MA
X32
25C
AP
or
ICL3
225C
A
U31
MA
X32
25C
AP
or
ICL3
225C
A
C15
10.
1uF
C15
10.
1uF
C15
5
1nF
C15
5
1nF
C14
70.
1uF
C14
70.
1uF
C14
30.
1uF
C14
30.
1uF
5 9 4 8 3 7 2 6 1
P4
P4
C15
8
0.1u
F
C15
8
0.1u
F
C15
6
0.1u
F
C15
6
0.1u
F
11
22
33
44
55
66
77
88
RP
26
4x 4
.7K
RP
26
4x 4
.7K
C14
90.
1uF
C14
90.
1uF
C15
4
0.1u
F
C15
4
0.1u
F
RE
AD
Y1
C1+
2
V+
3
C1-
4
C2+
5
C2-
6
V-
7
T2O
UT
8
R2I
N9
R2O
UT
10IN
VA
LID
11T
2IN
12T
1IN
13F
OR
CE
ON
14
GN
D18
R1O
UT
15R
1IN
16T
1OU
T17
VC
C19
FO
RC
EO
FF
20
U32
MA
X32
25C
AP
or
ICL3
225C
A
U32
MA
X32
25C
AP
or
ICL3
225C
A
1 2 3 4J13
J13
For More Information On This Product,
Go to: www.freescale.com
F
ree
sca
le S
em
ico
nd
uc
tor,
I
Freescale Semiconductor, Inc.n
c..
.
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
B_A
[23:
0]
B_D
21
B_D
25B
_D24
B_D
[31:
0]
/CS
2
B_D
17
B_D
28B
_D27
B_D
26
B_D
18
B_D
31
B_D
23
B_D
19
B_D
30
B_D
16
/CS
[7:0
]
B_D
29
B_D
22
B_A
1
B_D
20
/IRQ
3
/IRQ
[7:1
]
/IRQ
4
B_A
0
B_D
[31:
0]
B_A
[23:
0]
/CS
[7:0
]
/OE
R/W
/IRQ
[7:1
]
DT
IN1
DT
IN2
DT
OU
T1
DT
OU
T2
/RS
TO
UT +3.
3V
+3.
3V+
5V
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3V+
3.3V
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3V+
3.3V
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3V
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3V
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of
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M52
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1616
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pril
30, 2
004
Titl
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ev
Dat
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of
SC
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0380
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B C
ontr
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M52
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VB
B
1616
Frid
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pril
30, 2
004
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Siz
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ocum
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umbe
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ev
Dat
e:S
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of
SC
H-2
0380
US
B C
ontr
olle
rB
M52
3xE
VB
B
1616
Frid
ay, A
pril
30, 2
004
Dec
oupl
ing
capa
cito
rs
Hos
t
Dev
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500m
A p
er c
hann
el
HO
ST
EN
B1
(JP
56)
- se
t bet
wee
n pi
ns 2
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if us
ing
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HO
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ns 1
& 2
if u
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(def
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.
OT
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Do
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OT
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nabl
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NO
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by
defa
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The
ISP
1362
can
be
conf
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ed to
op
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PIO
or
DM
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ode.
Jum
per
Set
tings
are
as
follo
ws:
D
MA
PIO
JP57
O
N
OF
FJP
58
ON
O
FF
JP59
O
N
OF
FJP
60
ON
O
FF
JP62
O
FF
ON
JP63
O
FF
ON
Def
ault
setti
ng is
DM
A e
nabl
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US
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erie
s "B
" C
ON
N
US
B S
erie
s "A
" C
ON
N
Def
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for
JP61
is F
ITT
ED
Mot
orol
a S
PS
TS
PG
- T
EC
D C
oldF
ire G
roup
12
JP62
JP62
R89
1KR
891K
D33
D33
12
JP59
JP59
C17
51n
FC
175
1nF
C17
60.
1uF
C17
60.
1uF
C17
11n
FC
171
1nF
C17
20.
1uF
C17
20.
1uF
123
JP56
JP56
EN
A1
FLG
A2
FLG
B3
EN
B4
OU
TB
5G
ND
6IN
7O
UT
A8
U34
MIC
2026
U34
MIC
2026
R85
100K
R85
100K
Y2
12M
Hz
Y2
12M
Hz
12
JP63
JP63
R86
100K
R86
100K
R91
10K
R91
10K
R93
1MR
931M
R92
100K
R92
100K
R81
10K
R81
10K
12
JP57
JP57
1 2 3 4 5J14
US
B M
ini-A
B C
ON
N
J14
US
B M
ini-A
B C
ON
N
C16
347
pFC
163
47pF
DG
ND
1
VC
C(5
.0)
56
AG
ND
51
VB
US
55
OT
G_D
M1
49
OT
G_D
P1
50
CP
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P2
54
CP
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P1
53
OT
GM
OD
E4
5
RE
SE
T3
2
DR
EQ
12
4
DR
EQ
22
5
DA
CK
12
8
DA
CK
22
9
INT
23
1
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23
6
H_D
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46
H_D
P2
47
H_S
US
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/WU
P3
3
D_S
US
PD
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P3
4
H_P
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13
5
GL
39
DG
ND
9
VC
C(3
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4
CS
21
RD
20
WR
22
INT
13
0
ID4
8A
06
1
A1
62
VC
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52
VC
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58
TE
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02
3
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15
9
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ND
19
VC
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14
TE
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26
0
CLK
OU
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8
D0
63
D1
64
DG
ND
27
VC
C(3
.3)
26
D2
2
D3
3
D4
5
D5
6
D6
7
D7
8
D8
10
D9
11
D10
12
D11
13
D12
15
D13
16
D14
17
D15
18
VC
C(3
.3)
40
X2
44
X1
43
DG
ND
37
H_O
C1
42
H_O
C2
41
DG
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57
U33
ISP
1362
U33
ISP
1362
R82
10K
R82
10K
C16
447
pFC
164
47pF
C15
910
uF 1
6VC
159
10uF
16V
1 2 3 4J16
J16
C17
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173
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C17
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170
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R83
22R
R83
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R90
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12
JP58
JP58
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C16
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8822
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R
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JP61
JP61
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TP
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VB
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1
TP
13
VB
US
1
C16
147
pFC
161
47pF
12
JP55
JP55
R87
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R87
22R
C16
222
nFC
162
22nF
R84
22R
R84
22R
C17
822
pFC
178
22pF
C16
81n
FC
168
1nF
C16
710
uF 1
6VC
167
10uF
16V
12
JP60
JP60
C16
60.
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C16
60.
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C17
722
pFC
177
22pF
1 2 3 4J15
J15
For More Information On This Product,
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ree
sca
le S
em
ico
nd
uc
tor,
I
Freescale Semiconductor, Inc.n
c..
.
B-18 M523xEVB User’s Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
For More Information On This Product, Go to: www.freescale.com
F
ree
sca
le S
em
ico
nd
uc
tor,
I
Freescale Semiconductor, Inc.n
c..
.
Appendix CEvaluation Board BOM
MOTOROLA Appendix C. Evaluation Board BOM C-1PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
For More Information On This Product, Go to: www.freescale.com
F
ree
sca
le S
em
ico
nd
uc
tor,
I
Freescale Semiconductor, Inc.n
c..
.
Tab
leC
-1. M
523x
EV
B B
ill o
f M
ater
ials
Item
Qty
Ref
eren
ceD
escr
ipti
on
Mfg
rP
art
Nu
mb
erN
ote
s
11
N/A
BA
RE
PW
B ;
RE
Rev
X fo
r M
523X
EV
BR
apid
PC
B17
0-20
380
246
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C2,
C3,
C4,
C12
, C13
, C14
, C15
, C18
, C
19, C
24, C
25, C
26, C
27, C
37, C
34, C
39,
C70
, C71
, C72
, C73
, C74
, C75
, C76
, C77
, C
98, C
99, C
110,
C11
1, C
112,
C11
3, C
118,
C
124,
C13
3, C
134,
C13
5, C
136,
C15
3,
C15
5, C
157,
C16
8, C
171,
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3, C
175,
C
182,
C18
3
1nF
50V
080
5, 5
% C
OG
Sur
face
Mou
nt C
aps
KO
AA
VX
080
51C
102K
AT
2A
377
C5,
C6,
C7,
C8,
C9,
C10
, C11
, C16
, C17
, C
28, C
29, C
30, C
31, C
33, C
35, C
36, C
38,
C40
, C42
, C43
, C44
, C46
, C47
, C48
, C49
, C
52, C
53, C
55, C
57, C
78, C
79, C
80, C
81,
C82
, C83
, C84
, C85
, C10
0, C
101,
C11
4.
C11
5, C
116,
C11
7. C
119,
C12
0, C
122,
C
123,
C12
7, C
130,
C13
7, C
138,
C13
9,
C14
0, C
141,
C14
2, C
143,
C14
4, C
145,
C
146,
C14
7, C
148,
C14
9, C
150,
C15
1,
C15
2, C
154,
C15
6, C
158,
C16
6, C
169,
C
172,
C17
4, C
176,
C18
4, C
185,
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6,
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7
0.1u
F 2
5V 0
805,
10%
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Sur
face
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nt C
aps
KO
AA
VX
080
55C
104K
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2A
46
C20
, C21
, C22
, C23
, C18
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181
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62
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ase
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ount
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S
For More Information On This Product,
Go to: www.freescale.com
F
ree
sca
le S
em
ico
nd
uc
tor,
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Freescale Semiconductor, Inc.n
c..
.
1210
C90
, C91
, C92
, C93
, C96
, C97
, C10
6,
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7, C
108,
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947
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50V
NP
O o
r C
OG
080
5, 5
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143
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1, C
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or
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165,
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kel
TA01
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R
172
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1, C
132
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805
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or
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lips
184
C16
0, C
161,
C16
3, C
164
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805
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lips
191
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222
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MD
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080
5 5%
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202
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177
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2112
D1,
D2,
D3,
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er D
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MB
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gbrig
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1, F
B2,
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3, F
B4,
FB
5, F
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Fer
rite
Bea
dsS
TE
WA
RD
HI1
206T
500R
-00
Tab
leC
-1. M
523x
EV
B B
ill o
f M
ater
ials
(co
nti
nu
ed)
Item
Qty
Ref
eren
ceD
escr
ipti
on
Mfg
rP
art
Nu
mb
erN
ote
s
For More Information On This Product,
Go to: www.freescale.com
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ree
sca
le S
em
ico
nd
uc
tor,
I
Freescale Semiconductor, Inc.n
c..
.
281
F1
5A F
ast B
low
FU
SE
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2933
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JP
2, J
P3,
JP
4, J
P27
, JP
28, J
P29
, JP
30, J
P33
, JP
34, J
P37
, JP
38, J
P39
, JP
40, J
P41
, JP
42, J
P43
, JP
44, J
P45
, JP
46, J
P47
, JP
48, J
P49
, JP
53, J
P54
, JP
55, J
P57
, JP
58, J
P59
, JP
60, J
P61
, JP
62, J
P63
2-w
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umpe
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or
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3030
JP5,
JP
6, J
P7,
JP
8, J
P9,
JP
10, J
P11
, JP
12, J
P13
, JP
14, J
P15
, JP
16, J
P17
, JP
18, J
P19
, JP
20, J
P21
, JP
22, J
P23
, JP
24, J
P25
, JP
26, J
P31
, JP
32, J
P35
, JP
36, J
P50
, JP
51, J
P52
, JP
56
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Tab
leC
-1. M
523x
EV
B B
ill o
f M
ater
ials
(co
nti
nu
ed)
Item
Qty
Ref
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on
Mfg
rP
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Nu
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erN
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s
For More Information On This Product,
Go to: www.freescale.com
F
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sca
le S
em
ico
nd
uc
tor,
I
Freescale Semiconductor, Inc.n
c..
.
401
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A o
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Tab
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B B
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Ref
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le S
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I
Freescale Semiconductor, Inc.n
c..
.
552
R2,
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62 o
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KO
A o
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568
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R6,
R72
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4.7K
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A o
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220R
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220R
638
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A o
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A o
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R42
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7827
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A o
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Tab
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523x
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B B
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(co
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nu
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Item
Qty
Ref
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Mfg
rP
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Nu
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For More Information On This Product,
Go to: www.freescale.com
F
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sca
le S
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ico
nd
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tor,
I
Freescale Semiconductor, Inc.n
c..
.
695
R51
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1.8K
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560R
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733
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Qty
Ref
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Mfg
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For More Information On This Product,
Go to: www.freescale.com
F
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sca
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I
Freescale Semiconductor, Inc.n
c..
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871
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Tab
leC
-1. M
523x
EV
B B
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f M
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(co
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nu
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Item
Qty
Ref
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escr
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on
Mfg
rP
art
Nu
mb
erN
ote
s
For More Information On This Product,
Go to: www.freescale.com
F
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sca
le S
em
ico
nd
uc
tor,
I
Freescale Semiconductor, Inc.n
c..
.
106
2V
IA1,
VIA
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P
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No
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A =
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Tab
leC
-1. M
523x
EV
B B
ill o
f M
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ials
(co
nti
nu
ed)
Item
Qty
Ref
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ceD
escr
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on
Mfg
rP
art
Nu
mb
erN
ote
s
For More Information On This Product,
Go to: www.freescale.com
F
ree
sca
le S
em
ico
nd
uc
tor,
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Freescale Semiconductor, Inc.n
c..
.
C-10 M523xEVB User’s Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
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