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Machine Instructions

Operations

ITCS 3181 Logic and Computer Systems 2014 B. Wilkinson Slides4-1.ppt Modification date: Oct 22, 2014

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Instructions

We will use a simple instruction formats of a so-called reduced instruction set computer (RISC), which has the characteristics:

• Simple, fixed length instruction format• A few addressing modes• Limited number of operations• Designed to achieve high speed of execution

It was recognized in the 1980’s that such processors would actually execute programs faster that the prevalent CISCs (complex instruction set computers).

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Instruction format

Our instruction format is quite similar to the G4/G5 PowerPC and SUN Sparc processors and also similar but not identical to that used in the assembly language simulator in the labs.

Intel 64/IA32 processor family -- uses a very complex and archaic instruction format, based upon the early 8086 processor (which was themselves loosely based upon even earlier Intel processors).

However Intel processors now convert this complex instruction format (CISC) internally to simpler RISC formats for performance reasons.

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1.Thirty-two 32-bit integer registers called R0 to R31

2. One register, R0, holds zero permanently

3 All arithmetic done only between registers: - Three-register format op-code, destination register, source register 1, source register 2

or

- Immediate addressingop-code destination, source register, constant

4. Memory operations limited to:

load register, and store register

using register indirect addressing plus offset only.

Some Key Features of Processor Used

R0R1R2

R31R30

R3

R29

R4

R28

0000 … 0000

R31 holds return address for procedures.R29 is a stack pointer see later.

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Data TransferInstructions that copy the contents of one location to another location.

Examples

MOV R1,R2 ;R1 = R2LD R3,100[R2] ;Contents of memory whose address is

;given by 100 + R2 copied to R3.ST [R5],R4 ;Contents of R4 copied to memory loc.

;whose address held in R5. (Offset = 0)

Note LD and ST cause 32-bit transfers.Use LB and SB to cause 8-bit transfers.

Instruction Comments

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Arithmetic InstructionsPerforms an arithmetic operation such as addition, subtraction, multiplication or division.

Examples

ADD R1,R2,R3 ;R1 = R2 + R3SUB R5,R4,3 ;R5 = R4 – 3

For literals (immediate addressing) Differences in assembly language notation.

SUB R5,R4,3 ;R5 = R4 - 3might be written as:

SUB R5,R4,#3 ;R5 = R4 - 3or

SBI R5,R4,3 ;R5 = R4 - 3depending upon assembly language.

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Logical Instructions

Performs bit-wise logical operation such as AND, OR, exclusive-OR, or NOT. AND, OR, exclusive-OR operate upon pairs of bits of two operands.

Bit-wise AND, OR, Ex-OR, and NOT are available in C and Java (although you probably did not come across them!):

C/Java Language Examples

y = y & 1 ;bit-wise AND y with the number 1z = z | 2 ;bit-wise OR z with the number 2

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Machine Instruction Examples

AND R1,R2,R3 ;R1 = R2 “AND” R3

if R2 = 10100010100101011000010100001111R3 = 01011011111010100010100010111010

then R1 = 00000010100000000000000000001010

OR R1,R2,R3 ;R1 = R2 “OR” R3

if R2 = 10100010100101011000010100001111R3 = 01011011111010100010100010111010

then R1 = 11111011111111111010110110111111

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Shift Instructions

Moves the bits of a location one or more places left or right.

Again available in C/Java (although you probably did not come across them!):

C/Java language Examples

y = y << 1 ;shift y 1 place left 1

z = z >> 2 ;shift z 2 places right

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Machine Instruction Examples

Examples

SHL R1,R1,1 ;Shift R1 left one place

SHR R1,R1,1 ;Shift R1 right one place

1 0 1 0 1 1 1 1 0 1 0 1 . . . 1 1 0 1

0 1 0 1 1 1 1 0 1 0 1 . . . 1 1 0 1 X

X = 0 or 1 see next slide

1 0 1 0 1 1 1 1 0 1 0 1 . . . 1 1 0 1

X 1 0 1 0 1 1 1 1 0 1 0 1 . . . 1 1 0

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Arithmetical and Logical Shifts

Two types of shift usually provided:

“Logical” shift (SHL, SHR)

Fill free end with 0, i.e. X = 0.

“Arithmetic” shift (SAL, SAR)

Arithmetic shifts multiple/divide by 2.

Arithmetic shift right maintains value of sign bit, i.e. X = value of original sign bit.

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Example

Starting with a number 9 000 ... 0001001

Shift arithmetic left one place. Get 18 000 ... 0010010

Shift arithmetic right two places. Get 4 000 ... 0000100i.e. lost the 0.5.

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Question

What is the difference, if any, between arithmetic shift left and logical shift left, i.e. what is the difference, if any, between:

SHL R1, R1, 1and

SAL R1, R1, 1

Answer

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Arithmetic shift left same as logical shift left (except arithmetic overflow may be detected).

Note: Java has logical shift right - called unsigned right shift, >>>.

Example

x = x >>> 2;

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QuestionWhat is the effect of the sequence?

SAL R1, R1, 1SAR R1, R1, 1

Answer

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Rotate Instructions

Moves bits of location one or more places left of right in a circular fashion.

ExamplesROL R1,R1,1 ;Rotate R1 left one place

ROR R1,R1,1 ;Rotate R1 right one place

1 0 1 0 1 1 1 1 0 1 0 1 . . . 1 1 0 1

0 1 0 1 1 1 1 0 1 0 1 . . . 1 1 0 1 1

1 0 1 0 1 1 1 1 0 1 0 1 . . . 1 1 0 1

1 1 0 1 0 1 1 1 1 0 1 0 1 . . . 1 1 0

Version of rotate exists where the rotate passes thro a Carry flag within the condition code register, see later about the CCR

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Control Flow

Compilers must translate statements such as:

if ((x != y) && (z < 0)) {a = b + 5;b = b + 1;

}

into machine instructions.

Unreasonable to try to provide a unique machine instruction for this IF statement because of the vast number of possible IF statements. Need to extract essential primitive operations for machine instructions.

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Decompose into simple IF statements of the form:

if (x relation y) goto L1;

where:

relation is any of usual relations allowed in high level languages (<, >, >=, <=, ==, !=)

L1 is a label prefixed to an instruction to identify it.

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i.e. translate

if ((x != y) && (z < 0)) {a = b + 5;b = b + 1;

}...

intoif (x == y) goto L1;if (z >= 0) goto L1;a = b + 5;b = b + 1;

L1: ...Label

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There is several ways of implementing the IF statement.

if (x relation y) goto L1;

Here we will consider two ways:

1. Using one branch instruction.

2 Using two instructions, one to determine whether relationship is true, and another to branch to L1 if true.

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1. Using one branch instruction

Single “branch” machine instruction compares two registers and goes to the labeled location if the condition is true, i.e.

Bcond Rs1, Rs2, L1

changes the execution sequence to the instruction labeled L1 if Rs1 cond Rs2 is true, where cond can be any of six possible conditions, and Rs1 and Rs2 can be any of the 32 registers.

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Conditional Branch Instruction op-codes

Bcond

Bcond Condition High level language notationBL Branch if less than <BG Branch if greater than >BGE Branch if greater or equal to >=BLE Branch if less or equal to <=BE Branch if equal ==BNE Branch if not equal !=

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Example

To implementif (x == y) goto L1;

.

.

.L1:

by a single machine instruction, we get:BE R1,R2,L1

.

.

.L1:

where the compiler allocates R1 for x and R2 for y.

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Machine Instruction Encoding

The instruction

Bcond Rs1,Rs2,L1

requires an op-code (Bcond), the two source registers Rs1 and Rs2, and L1 to be specified.

Op-c od e

R s 1 R s 2 L 1Bc on d

Note: Bcond is either BL, BG, BGE, BLE, or BNE

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Specifying “target” location L1

Several ways L1 could be specified in instruction:

Absolute (direct) addressing The address of L1 held in instruction.

(PC) Relative addressing The distance from branch instruction to labeled instruction stored in instruction.

Program counter, see later

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Absolute (direct) addressing

BE R1,R2,120...

L1: ;location 120 say

O p-c ode

R s1 R s2 1 20B c ond

Note: Absolute addressing will not used in our design.

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(Program counter) Relative Addressing

Specify target location as number of instructions from branch instruction.

(The location of the instruction being fetched from memory is given by an instruction pointer called the program counter historically)

Mostly, conditional branch instructions used to implement small changes in sequences or program loops of relatively short length, so distance from branch to target (label) quite small compared to full address of the labeled instruction.

Also good programming practice to limit sequence changes to short distance from current location to avoid difficult to read code.

Also makes code relocatable. (i.e. code can be loaded anywhere in memory without altering branch instructions.)

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PC-Relative Addressing

The number of locations to the target is held in the instruction as an offset.

Offset is added to the program counter to obtain the “effective address” of the target location.

B ra n ch o p -cod e O ffse t

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(PC) Relative Addressing

BE R1,R2,+30 ;location 90 say...

L1: ;location 120 say

O p-c ode

R s1 R s2 3 0B c ond

Offset/displacementPC = 90(Note: PC incremented by the size of instruction, 4 here, after instruction fetched in most implementations)

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QuestionHow would one code:

if (x > y) x = 10;

with machine instructions where x and y are stored in R2 and R3 respectively?

Answer

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2. Condition Code Register Approach

In this approach, we determine whether the Boolean condition in

if (x relation y) goto L1;

is true by subtracting y from x and recognizing whether the result is positive or negative, zero, or not zero:

relation x - y< negative> positive and not zero>= positive or zero<= negative or zero== zero!= not zero

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Condition Code Register (CCR)

Contains a set of flags (single bits) used to be able to recognize the different possible relationships (<, >, >=, <=, ==, !=) after the previous arithmetic operation.

Flags in condition code register indicate a particular aspect of the result of the last arithmetic instruction, i.e. positive or negative, zero or not zero, …

Usually a form of subtract operation is first performed, although technically other arithmetic and logical operations can affect the condition code register.

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Sign Flag (S or N flag)(positive or negative)

Indicates whether previous arithmetic result is negative or positive.

S = 1 for negative resultS = 0 for positive result.

S is actually the most significant (sign) bit of the result of the previous arithmetic operation

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Zero Flag

Zero flag, Z:

Z = 1 for result = 0Z = 0 for result != 0

(Note zero is a positive number.)

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Condition Code Register

Condition Code register normally closely linked to the ALU (Arithmetic and Logic Unit):

A L UCo nd ition co d e

In te rna l b use s

re g is terZS

S – S ign f la gZ – Z ero f la g

S am p le alloca tio n of b its

P roce sso r

(Th ere a re o th er bits u se d no t yet d escrib ed )

Ans werSo urce opera nds

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Using Condition Code RegisterDecompose IF statement such as:

if (x relation y) goto L1

into two sequential operations:

1. Subtract y from x which sets condition code register according to result

2. Read condition code register and “branch” to L1 if specific condition indicated

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Step 1 Subtract and Set Condition Code Register

All arithmetic instructions set condition code register according to the result of the arithmetic operation, but a compare instruction specifically provided, which is similar to a subtract instruction except the result is not stored anywhere, only the CCR flags are set according to the result.

Example

CMP R1, R2 ;R1 - R2, sets CCR flags

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Step 2 Reading Condition Code Register and Branching

A conditional branch instruction used to examine the values stored in the condition code register to determine whether the specific condition exists and to branch if it does.

All six conditions usually available:

BL Branch if less thanBG Branch if greater thanBGE Branch if greater or equal toBLE Branch if less or equal toBE (or BZ) Branch if equalBNE (or BNZ) Branch if not equal

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Example

Suppose x held in R1 and y held in R2. The if statement:

if (x == y) goto L1;

could be implemented by sequence of two instructions, CMP and BE:

CMP R1,R2 ;Compare contents of R1, R2 (x, y)BE L1 ;Go to L1 if equal

L1:

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ExampleSuppose x held in R1 and y held in R2. The if statement:

if (x == y) goto L1;

could be implemented by sequence of two instructions, CMP and BE:

CMP R1,R2 ;Compare contents of R1, R2 (x, y)BE L1 ;Go to L1 if equal

L1:

Z

Wr it e

C on dition co de reg is ter

Z = 1 if R 1 - R 2 = ze ro o th erwise Z = 0S

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Example

Suppose x held in R1 and y held in R2. The if statement:

if (x == y) goto L1;

could be implemented by sequence of two instructions, CMP and BE:

CMP R1,R2 ;Compare contents of R1, R2 (x, y)BE L1 ;Go to L1 if equal

L1:

C on dition co de reg is ter

Z = 1 if R 1 - R 2 = ze ro o th erwise Z = 0R ead

Z

Wr it e

S

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QuestionA processor uses a condition code register approach for branch instructions. Write an assembly language sequence for the C/Java code:

if ((a < b) && (a > 0)) b = a;

assuming that the variables a and b are assigned to registers R1 and R2 respectively.

Provide comments

Use any reasonable hypothetical instructions. (Note && is the symbol for the logical AND operation.)

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Answer

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More complex constructionsif - then - else

Suppose we had to implement:

if (a < b) c = a; else a = c;...

assuming that the variables a, b, and c are assigned to registers R1, R2, and R3 respectively.

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Leads to:

CMP R1,R2 ;Compare R1, R2 (x, y)BL L1 ;Go to L1 if a less than bMOV R1, R3 ;a = c

L1: MOV R3,R1 ; c = a;L2: ...

We need to alter the instruction sequence unconditionally. With the instructions we know about so far, it could be done with:

CMP R1, R1BE L2 ;if (x == x) goto L2;

but there is a special instruction called a jump instruction to do it.

Skip over c = a

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JUMP Instructions

Causes an unconditional change of execution sequence to a new location.

Necessary to implement more complicated IF constructs, FOR, and WHILE loops.

Using J as the opcode mnemonic, the jump instruction is:

J L1 ;goto to L1

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With jump instruction:

CMP R1,R2 ;Compare R1, R2 (x, y)BL L1 ;Go to L1 if a less than bMOV R1, R3 ;a = cJ L2

L1: MOV R3,R1 ;c = a;L2: ...

Go to L2

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For loopsSuppose we had to implement the C/Java code sequence:

for (i = 1; i < 10; i++)a = a * i;

...

Let us assume i is held in register R1, and x is held in register R2.

Possible solution

MOV R1, 1 ;i = 1L2: CMP R1,10 ;Compare R1 with 10

BGE L1 ;Go to L1 if end of loopMUL R2,R2,R1 ;a = a * iADD R1,R1,1 ;increment iJ L2

L1: ...

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Jump Instruction with Register-Indirect Addressing

An “address register” specified in instruction holds the address of the location holding the next instruction to be executed.

Examples

J [R1] ;jump to location whose address in R1

J 100[R1] ;jump to location whose address given ;by R1 + 100

Target address specified as absolute address, rather than relative address.Used to implement high level language SWITCH statements. Also return from procedures see next section.

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Avoiding Condition Code Register

It turns out that the CCR approach has disadvantages when one tries to implement a high performance processor, and does not really suit RISC designs.

CCR approach requires two sequential instructions with no instructions allowed in between that affect the CCR. (All arithmetic/logic instruction affect CCR.)

Alternative -- use a general purpose register in place of CCR to hold “conditions.”

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One solution -- Simplified version of branch instruction

Bcond Rs1, L1

where Rs1 is compared against zero rather than Rs2.

Do subtract operation previous to this instruction, placing result in Rs1.

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QuestionHow would one code:

if (x > y) goto L1;

where x and y are stored in R2 and R3 respectively using previous simplified version of branch instruction?

Answer

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One version of branch instruction used in MIPS processor

Use a general purpose register set to 1 of 0 if one register is less than another.

SLT Rs1,Rs2,Rs3 ;Rs1 = 1 if Rs2 < Rs3

together with a simple branch instruction that only tests condition equal or not equal, i.e.:

BEQ Rs1, Rs2, L1 ;goto L1 if Rs1 = Rs2and

BNE Rs1, Rs2, L1 ;goto L1 if Rs1 != Rs2

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Using MIPS Branch Instruction

To do

if (x < y) goto L1;

where x and y are stored in R2 and R3 respectively, we might write:

SLT R1,R2,R3 ;R1 = 1 if R2 < R3BNE R1,R0,L1 ;goto L1 if R1 != 0

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It is much more common to use a condition code register.

Pentium uses condition code register for historical reasons.

However, the condition code register approach makes it much more difficult to design a high-performance processor.

In our design subsequently, we will use:

Bcond Rs1, L1

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Questions