Machine-Level Programming I:IntroductionSept. 8, 1998
Topics• Assembly Programmer’s
Execution Model
• Arithmetic Instructions
• Memory Instructions
• Transfers of Control
• Comparison to actual Alpha 21164 processor
class05.ppt
15-213“The course that gives CMU its Zip!”
CS 213 F’98– 2 –class05.ppt
Alpha ProcessorsReduced Instruction Set Computer (RISC)
• Simple instructions with regular formats
• Key Idea: make the common cases fast!
– infrequent operations can be synthesized using multiple instructions
Assumes compiler will do optimizations• e.g., scalar optimization, register allocation, scheduling, etc.
• ISA designed for compilers, not assembly language programmers
A 2nd Generation RISC Instruction Set Architecture• Designed for superscalar processors ( > 1 inst per cycle)
• Designed as a 64-bit ISA from the start
Very High Performance Machines• Alpha has been the clear performance leader for many years now
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Assembly Programmer’s View
Programmer-Visible State• PC Program Counter
– Address of next instruction
• Register File
– Heavily used program data
• Memory
– Byte addressable array
– Code, user data, (some) OS data
PC
RegisterFile
CPU Memory
Object CodeProgram Data
OS Data
Addresses
Data
Instructions
CS 213 F’98– 4 –class05.ppt
text
text
binary
binary
Compiler (gcc -S)
Assembler (gcc or as)
Linker (gcc or ld)
C program (p1.c p2.c)
Asm program (p1.s p2.s)
Object program (p1.o p2.o)
Executable program (p)
libraries (.a)
Turning C into Object Cod
e
• Code in files p1.c p2.c
• Compile with command: gcc -O p1.c p2.c -o p
– Use optimizations (-O)
– Put resulting binary in file p
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Compiling Into AssemblyC Code
long int arith(long int x, long int y, long int z){ long int t1 = x+y; long int t2 = z+t1; long int t3 = x+4L; long int t4 = y * 48L; long int t5 = t3 + t4; long int rval = t2 * t5; return rval;}
Generated Assembly
arith:arith..ng:
.frame $30,0,$26,0
.prologue 0addq $16,$17,$1addq $18,$1,$0addq $16,4,$16s4subq $17,$17,$17sll $17,4,$17addq $16,$17,$16mulq $0,$16,$0ret $31,($26),1.end arithObtain with command
gcc -O -S code.c
Produces file code.s
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Assembly CharacteristicsMinimal Data Types
• “Integer” data of 1, 2, 4, or 8 bytes
– Data values
– Addresses (untyped pointers)
• Floating point data of 4 or 8 bytes
• No aggregate types such as arrays or structures
– Just contiguously allocated bytes in memory
Primitive Operations• Perform arithmetic function on register data
• Transfer data between memory and register
– Load data from memory into register
– Store register data into memory
• Transfer control
– Unconditional jumps to/from procedures
– Conditional branches
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Code for arith
0x1200012d0:0x421104010x424104000x420094100x423105710x4a2097310x421104100x4c1004000x6bfa8001
Object Cod
e
Assembler• Translates .s into .o
• Binary encoding of each instruction
• Nearly-complete image of executable code
• Missing linkages between code in different files
Linker• Resolves references between files
• Combines with run-time libraries
– At the very least includes libc.a
– E.g., code for malloc, printf• Total of 8 instructions
• Each 4 bytes
• Starts at address 0x1200012d0
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Machine Instruction ExampleC Code
• Add two signed 64-bit integers
Assembly• Add 2 8-byte integers
– “Quad” words in Alpha parlance
– Same instruction whether signed or unsigned
• Operands & result in registers:
$16: x
$17: y
$1: t1
Object Code• 32-bit pattern
• Stored at address 0x1200012d0
long int t1 = x+y;
addq $16,$17,$1
0x1200012d0: 0x42110401
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Opcode Ra Rb RcFunc000 0
6 5 3 1 7 55
010000 10000 10001 000 0 0100000 00001 0x10 16 17 0x20 1
addq $16,$17,$1
Encoding of
Machine Instruction
Format for Register-Register Arithmetic Instructions
• Opcode + Func fields determine operation <op>
• Effect is Reg[Rc] = Reg[Ra] <op> Reg[Rb]
Decoding Hex Format
Regrouping into Instruction Fields
• Opcode 0x10 + Func 0x20 encodes addq
4 2 1 1 0 4 0 10100 0010 0001 0001 0000 0100 0000 0001
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Object0x1200012d0:
0x421104010x424104000x420094100x423105710x4a2097310x421104100x4c1004000x6bfa8001
Disassembled0x1200012d0: 42110401 addq r16, r17, r10x1200012d4: 42410400 addq r18, r1, r00x1200012d8: 42009410 addq r16, 0x4, r160x1200012dc: 42310571 s4subq r17, r17, r170x1200012e0: 4a209731 sll r17, 0x4, r170x1200012e4: 42110410 addq r16, r17, r160x1200012e8: 4c100400 mulq r0, r16, r00x1200012ec: 6bfa8001 ret r31, (r26), 1
Disassembling Object Cod
eDisassemblerdis -h p
• Useful tool for examining object code
• Analyzes bit pattern of series of instructions
• Produces approximate rendition of assembly code
• Can be run on either a.out (complete executable) or .o file
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Implementing Arithmetic Operations
1. FetchIR = Mem[PC]
a = Reg[Ra]
b = Reg[Rb]
PC
IR
RegisterFile
ALU
Memory
Opcode + Func
Ra
Rb
Rc
a
b
c
InstructionAddress
Instruction Result
+4
2. Executec = a <op> b
3. UpdateReg[Rc] = c
PC = PC + 4
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Arithmetic Operation Example
1. FetchIR = Mem[PC]
a = Reg[Ra]
b = Reg[Rb]
InstructionAddress
Instruction
+4
2. Executec = a <op> b
3. UpdateReg[Rc] = c
PC = PC + 4
Memory
0x1200012d0: 0x42110401
PC
0x1200012d0
ALU
Opcode + Func
Ra
Rb
Rc
a
b
c
Result
Register File
$16: 0xABC
$17: 0x123
$1: 0xFFFIR
0x42110401
$1
$16
$17
0xABC
0x123
0xBDF
0xBDF0x1200012d4
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Executing Aritharith(x, y, z){ t1 = x+y; t2 = z+t1; t3 = x+4L; t4 = y * 48L; t5 = t3 + t4; rval = t2 * t5; return rval;}
addq $16,$17,$1
addq $18,$1,$0
addq $16,4,$16
s4subq $17,$17,$17
sll $17,4,$17
addq $16,$17,$16
mulq $0,$16,$0
ret $31,($26),1
$16 $17 $18$0 $1
x y z- -
Op a <op> b addq a + b s4subq 4*a - b sll a << b mulq a * b
x y z- t1
x y zt2 t1
t3 y zt2 t1
t3 3*y zt2 t1
t3 t4 zt2 t1
t5 t4 zt2 t1
t5 t4 zrval t1
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Logical Operation Example
• Logical operations similar to arithmetic operations
• Both have two formats
– RR: Operands a and b from registers
– RI: Operand a from register, b is 8-bit unsigned “literal”
long int logical(long int x, long int y){ long int t1 = x^y; long int t2 = t1 >> 17; long int mask = (1L<<13) - 7L; long int rval = t2 & mask; return rval;}
Opcode Ra Rb RcFunc000 0
6 5 3 1 7 55
Opcode Ra Lit RcFunc1
6 8 1 7 55
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Executing Logical
xor $16,$17,$17
sra $17,17,$17
lda $0,8185
and $17,$0,$0
ret $31,($26),1
$16 $17$0
x y-
x t1-
x t2-
x t2mask
x t2rval
Op a <op> b xor a ^ b sra a >> b and a & b
logical(x, y){ t1 = x^y; t2 = t1 >> 17; mask = (1L<<13) - 7L; rval = t2 & mask; return rval;}
Special trick to get big constant
1L << 13 = 81928192 - 7 = 8185
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Load & Store InstructionsLoad Operation
• Read (load) from memory
• Write to register
ldq Ra, Offset(Rb)• Arguments
Ra Destination Reg.
Rb Base address Reg.
Offset Offset from base
» Between –32,768 and 32,767
• Effective Address
EA = Reg[Rb] + Offset• Operation
Reg[Ra] = Mem[EA]
Opcode Ra Rb Offset
6 55 16
Store Operation• Read from register
• Write (store) to memory
stq Ra, Offset(Rb)
• Arguments
Ra Source Reg.
Rb Base address Reg.
Offset Offset from base
» Between –32,768 and 32,767
• Effective Address
EA = Reg[Rb] + Offset
• Operation
Mem[EA] = Reg[Rb]
CS 213 F’98– 17 –class05.ppt
Implementing Load Operation
1. FetchIR = Mem[PC]
b = Reg[Rb]
PC
IR
RegisterFile
ALU
Memory
Ra
Rb
Offset
b EA = b+Offset
InstructionAddress
Instruction
+4
2. ExecuteEA = b + Offset
Result = Mem[EA]
3. UpdateReg[Ra] = Result
PC = PC + 4
Mem[EA]
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Implementing Store Operation
1. FetchIR = Mem[PC]
a = Reg[Ra]
b = Reg[Rb]
PC
IR
RegisterFile
ALU
Memory
Ra
Rb
Offset
b EA = b+Offset
InstructionAddress
Instruction
+4
2. ExecuteEA = b + Offset
3. UpdateMem[EA] = a
PC = PC + 4
a
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Load & Store Example
Realization of C Pointers• Pointer is address of object
• Manipulated as 64-bit signed integer
• Machine has no notion of pointer type
– Does not distinguish (char *), (int *), (int **), etc.
void swap(long int *xp, long int *yp) { long int t0 = *xp; long int t1 = *yp; *xp = t1; *yp = t0;}
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Executing Swapswap(*xp, *yp) { t0 = *xp; t1 = *yp; *xp = t1; *yp = t0;}
ldq $1,0($16)
ldq $2,0($17)
stq $2,0($16)
stq $1,0($17)
ret $31,($26),1
$16 $17 Mem[xp]$1 $2
xp yp X- -
Mem[yp]
Y
xp yp XX -
xp yp XX Y
xp yp YX Y
xp yp YX Y
Y
Y
Y
X
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XOR-Based Swap
Very Inefficient Code• 4 loads, 3 stores, 3 ALU ops
• vs. 2 loads, 2 stores for swap
Apparent Non-Optimality• Why does it need to keep reloading operand?
• Hint: required to preserve behavior for special argument combination
void xor_swap(long int *xp, long int *yp){ *xp = *xp ^ *yp; *yp = *xp ^ *yp; *xp = *xp ^ *yp; }
ldq $2,0($16)ldq $1,0($17)xor $2,$1,$2stq $2,0($16)ldq $1,0($17)xor $2,$1,$2stq $2,0($17)ldq $1,0($16)xor $1,$2,$1stq $1,0($16)ret $31,($26),1
= $1?
Reuseearlierresult?
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Conditional Branch InstructionsFormat
bCOND Ra, target
• COND describes branch condition
• target computed from PC+4 and Displacement
• Assembler allows use of symbolic labels
Operation• Compare Reg[Ra] to 0
• Go to target if condition satisfied
• Otherwise proceed with next instruction
Opcode Ra
6 215
Displacement
Possible Conditionseq a == 0ne a != 0gt a > 0ge a >= 0lt a < 0le a <= 0lbc a&1 == 0lbs a&1 != 0
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Implementing Branch Operation
1. FetchIR = Mem[PC]
a = Reg[Ra]
3. Updateif (branch)
PC = target
else
PC = PC+4
2. Executebranch = Cond(a)
target =
Target(PC+4,
Displacement)
PC
IR
RegisterFile
Test
Memory
COND
Ra a
InstructionAddress
Instruction
+4
TargetDisplacement
0
1
branch
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Conditional Branch Example
Dereferencing Invalid Pointer• If address valid, will return whatever is at that address
• If address is invalid, will signal error
– “Segmentation fault”
– Attempt to access portion of virtual address space that hasn’t been allocated yet
long int deref(long int *xp){ long int rval = 0; if (xp != 0) { rval = *xp; } return rval;}
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Executing Deref(0)deref(*xp){ rval = 0; if (xp != 0) { rval = *xp; } return rval;}
bis $31,$31,$0
beq $16, null
ldq $0,0($16)
null:
ret $31,($26),1
$16$0
xp=0-
00
00
00
Op a <op> b bis a | bSpecial Register $31 == 0
Skipped
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Executing Deref(≠0)deref(*xp){ rval = 0; if (xp != 0) { rval = *xp; } return rval;}
bis $31,$31,$0
beq $16, null
ldq $0,0($16)
null:
ret $31,($26),1
Op a <op> b bis a | bSpecial Register $31 == 0
$16$0
xp≠0-
Mem[xp]
X
xp0
xp0
xpX
X
X
X
xpX XExecuted
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Conditional Branch Example #2
Assembly• x in $16
• rval in $0
• $31 always 0
subq $31,$16,$0 # rval = -xblt $16, neg # if x < 0 goto negbis $16, $16, $0 # else rval = x
neg:ret $31,($26),1 # return
long int absval(long int x){ long int rval = x; if (x < 0) { rval = -x; } return rval;}
CS 213 F’98– 28 –class05.ppt
Conditional Move InstructionsFormats
cmoveCOND Ra, Rb, Rc
cmoveCOND Ra, Lit, Rc
• Same formats as arithmetic instruction• COND describes update condition
• Opcode + Func encode COND
Operation• Compare Reg[Ra] to 0
• if (cond) Reg[Rc] = Reg[Rb]
• Else register Rc unchanged
Possible Conditionseq a == 0ne a != 0gt a > 0ge a >= 0lt a < 0le a <= 0lbc a&1 == 0lbs a&1 != 0
Opcode Ra Rb RcFunc000 0
6 5 3 1 7 55
Opcode Ra Lit RcFunc1
6 8 1 7 55
CS 213 F’98– 29 –class05.ppt
Implementing Conditional Move
1. FetchIR = Mem[PC]
a = Reg[Ra]
b = Reg[Rb]
PC
IR
RegisterFile
Test
Memory
Opcode + Func
Ra
Rb
Rc
a
b
InstructionAddress
Update
+4
2. Executecond = Cond(a)
3. Updateif (cond)
Reg[Rc] = b
PC = PC + 4
cond
CS 213 F’98– 30 –class05.ppt
Conditional Move Example
Assembly• x in $16• rval in $0• $31 always 0
Why Use Conditional Moves?• Transfer of control disrupts flow of instructions through pipeline
• Especially when cannot reliably predict test outcome
subq $31,$16,$0 # rval = -xcmovge $16,$16,$0 # if (x >= 0) rval = x ret $31,($26),1 # return
long int absval(long int x){ long int rval = x; if (x < 0) { rval = -x; } return rval;}
CS 213 F’98– 31 –class05.ppt
Jump InstructionsFormat
jmp Ra, (Rb), Hint Jump
jsr Ra, (Rb), Hint Jump to Subroutine
ret Ra, (Rb), Hint Return from Subroutine
• Ra Register to store return pointer: PC+4
– Usually $31 for jmp and ret
» Don’t store return pointer
– Usually $26 for jsr
• Rb Jump destination
– Usually $26 for ret
• Hint Hint to help predict jump target address
– Don’t worry about this
• Assembler allows use of symbolic labels
OperationReg[Ra] = PC+4
PC = Reg[Rb]
Opcode Ra Rb Hint
6 55 16
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Implementing Jump Operations
1. FetchIR = Mem[PC]
b = Reg[Rb]
3. Update Reg[Ra] = PC+4
PC = b
2. Execute
PC
IR
RegisterFile
Memory
Rbb
InstructionAddress
Instruction
+4
Ra
CS 213 F’98– 33 –class05.ppt
Procedure Call/Return Example
Data Passing Conventions• Procedure arguments in registers $16, $17, …
• Return result in $0
long int abs_deref(long int *xp){ long int x = deref(xp); long int rval = absval(x); return rval;}
CS 213 F’98– 34 –class05.ppt
Executing Abs_derefabs_deref(*xp){ x = deref(xp); rval = absval(x); return rval;}
... # Stack stuff ...
0x100: lda $1, deref
0x104: jsr $26,($1),1
# On return:
0x108: bis $0,$0,$16
0x10c: lda $1,absval
0x110: jsr $26,($1),1
# On return:
... # Stack stuff ...
0x11c: ret $31,($26),1
Instruction Addresses0x080: abs_derefcall0x200: derefentry0x300: absvalentry
$16$0
xp-
$1
-
$26
-
xp-
xp-
xx
0x200
-
0x300
-
0x108
0x108
-x - 0x108
xx - 0x108
x- 0x300 0x114
-rval - 0x084
-rval - 0x114
CS 213 F’98– 35 –class05.ppt
Alpha 21164 Block DiagramFour Caches
• Most recently accessed instructions, data, address translations
Two Integer Pipelines• Perform integer
instructions, load/store addresses, branch conditions
Two Floating Point Pipelines• Floating point operations
Attempts to Predict Branches• Whether or not taken
• Target address
Microprocessor Report ‘94
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2116
4 D
ie
Ph
oto
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Summary: Abstract Machines
1) loops2) conditionals3) goto4) Proc. call5) Proc. return
Machine Models Data Control
1) char2) int, float3) double, long4) struct, array5) pointer
mem proc
C
mem regs alu
processor
Assembly1) byte2) 4-byte long word3) 8-byte quad word4) contiguous word allocation5) address of initial byte
3) branch/jump4) jsr5) ret
CS 213 F’98– 38 –class05.ppt
Summary: Instruction Formats
Arithmetic Operations:• all register operands
–addq $1, $7, $5
• with a literal operand–addq $1, 15, $5
Loads & Stores:• ldq $1, 16($30)
Branches:• a single source register
–bne $1, label
Jumps:• one source, one dest reg
–jsr $26, ($1), hint
Opcode Ra Rb RcFunc000 0
6 5 3 1 7 55
Opcode Ra Lit RcFunc1
6 8 1 7 55
Opcode Ra
6 215
Displacement
Opcode Ra Rb Hint
6 55 16
Opcode Ra Rb Offset
6 55 16
