MachXO™ Starter Evaluation Board - Lattice Semi

April 2007Revision: ebug14_01.4

MachXO™ Starter Evaluation Board

User’s Guide

2

MachXO Starter Evaluation BoardLattice Semiconductor User’s Guide

Introduction

The Lattice MachXO Starter Evaluation Board provides a convenient platform to evaluate, test and debug userdesigns. The board features a Lattice MachXO256 cross-over programmable logic device in a 100-pin TQFP pack-age, power input jacks, a 33MHz clock oscillator and I/O connections. The Lattice MachXO I/Os are connected to arich variety of interfaces, including switches (momentary and ON/OFF), LEDs, 0.10” headers and PCB test points.

Features

• Lattice MachXO device

• Prototyping area

• Access to 81 user I/Os

• Independent voltage control for core and I/O

• 33MHz on-board oscillator

• Status LEDs

• Input switches

• Pads for optional board expansion.

• AC adapter

• Lattice ispDOWNLOAD

®

cable, to download programming files to the MachXO device.

Software Support

• Lattice ispLEVER

®

design tools (release 5.0 SP1 or later) for HDL design targeting the MachXO device. The MachXO device is supported in the ispLEVER-Starter software, available from www.latticesemi.com/starter.

• ispVM

®

System, for device programming. Available for download from www.latticesemi.com/software.

Electrical, Mechanical and Environmental Specifications

The nominal board dimensions are 2.875 inches by 3.375 inches. The environmental specifications are as follows:

• Operating temperature: 0ºC to 55ºC

• Storage temperature: -40ºC to 75ºC

• Humidity: < 95% without condensation

• VDC input (+/- 10%) up to 4A

Figure 1 shows the board outline.

3


Figure 1. MachXO Starter Outline

Resources relating to the Lattice MachXO Starter Evaluation Board, including user documentation updates andsample programs, can be found at www.latticesemi.com/boards. Click on the appropriate link for the LatticeMachXO Starter Evaluation Board.

Lattice MachXO Device

The MachXO Starter Evaluation Board features a Lattice MachXO device with a 3.3V DC core. The board is popu-lated with a MachXO256 device in a plastic 100-pin TQFP package. The MachXO Starter Evaluation Board allowsfor density migration to other Lattice MachXO densities in the 100 TQFP package, with either 3.3V or 1.2V cores. Acomplete description of this device can be found in the Lattice MachXO Family Data Sheet on the Lattice web siteat www.latticesemi.com.

Device Core and I/O Voltage

Core Voltage

The MachXO is available with either 3.3V or 1.2V core voltage devices. Boards populated with a 3.3V DC coredevice will allow operation of the core between 1.8V and 3.3V DC. The core voltage is fixed at 3.3V during manu-facturing. The core voltage may be changed from the fixed 3.3V rail to the adjustable voltage rail by changing the 0ohm resistor at R157 to R158.

Boards populated with a 1.2V core device operate at 1.2V only, with the core voltage supply fixed at 1.2V duringmanufacturing. Refer to the board silkscreen outline in the appendix for component location.

PrototypeArea

MachXO I/O Access

MachXO I/OAccess

MachXO I/OAccess

ExpansionHeader

ExpansionHeader

3.3V LDO

1.2V LDO Adjustable LDO

33MHzOscillator

Switches JTAGInterface

DC Input

LED Bank

DIPSwitch

4


I/O Voltage

The Lattice MachXO device has two sysIO™ banks; each is capable of supporting multiple I/O standards. EachsysIO bank has its own I/O supply voltage (V

CCIO

), which allows each I/O bank to be completely independent.Refer to the Lattice MachXO Family Data Sheet for additional information about supported I/O standards. This datasheet can be downloaded from www.latticesemi.com.

The MachXO Starter Evaluation Board allows individual control of each I/O bank capable of supporting V

CCIO

between 1.2V and 3.3V. The board includes 0 ohm resistors which allow the user to select 3.3V or an adjustablevoltage between 1.25V and 3.3V. During manufacturing, the V

CCIO

banks are set to 3.3V. The adjustable voltagerail (ADJ) is fixed at 2.5V during manufacturing. Table 1 shows the required resistor population to set the appropri-ate core and I/O voltages.

Table 1. Voltage Jumpers/Settings for V

CCIO

and VCC_CORE

Device Clocks

The MachXO Starter Evaluation Board provides a variety of ways to supply clock signals to the MachXO device.These include a 33MHz on-board crystal oscillator, expansion connectors and 0.1” header pins. The on-boardoscillator is connected to MachXO pin 36, which is a dedicated clock input. The oscillator can be enabled/disabledvia pull up (R144) /down (R145), or through pin 44 of the MachXO. Dedicated clock inputs are also available on thefollowing pins: 38, 85 and 86. These pins are brought out to test points on the PCB, and to the expansion headers.

Device I/O Banks

MachXO I/O banks 0 and 1 are general purpose I/O banks connected to a combination of test pads, switches,LEDs and two board expansion headers. The switches consist of two user defined push-button switches and an 8-position DIP switch. Both types of switches are pulled up to the associated V

CCIO

voltage with 10K

Ω

resistors(when in the up position) and connected to GND when activated (in the down position). LEDs are active (lit) whenthe device I/O is low. Table 2 details the I/O banks 0 and 1 connections.

I/Os listed as GPIO (General Purpose I/O) are connected to 0.1” centered plated through hole, with an associatedGND hole and pads for a pull-up or pull-down resistor. The pull-up pads are located on the component side of thePCB, and the pull-down pads on the solder side. These pads are sized for 0805 components. Each device I/O isconnected to a test point on the PCB. The PCB silkscreen is marked with the corresponding MachXO 100-TQFPI/O pin.

3.3V ADJ 1.2V

VCC_CORE R157 (default

1

) R158 R156(default*)

V

CCIO0

R148 (default) R150 N/A

V

CCIO1

R151 (default) R152 N/A

1. Default resistor is based on device core I/O voltage, 3.3V for “C” devices, and 1.2V for “E” devices.

Table 2. Device I/O Connections

Pin # Pin Name Expansion Connect Function/PCB Connect

1 PL2A J1-5 GPIO

2 PL2B J1-6 GPIO

3 PL3A J1-7 GPIO

4 PL3B J1-8 GPIO

5 PL3C J1-9 GPIO

6 PL3D J1-10 GPIO

7 PL4A J1-11 GPIO

8 PL4B J1-12 GPIO

9 PL5A J1-13 GPIO

5


11 PL5B J1-14 GPIO

13 PL5C J1-15 GPIO

14 PL5D/GSR_N J1-16 GPIO

15 PL6A J1-17 GPIO

16 PL6B/TSALL J1-18 GPIO

17 PL7A J1-19 GPIO

18 PL7B J1-20 GPIO

19 PL7C J1-21 GPIO

20 PL7D J1-22 GPIO

21 PL8A J1-23 GPIO

22 PL8B J1-24 GPIO

23 PL9A J1-25 GPIO

27 PL9B J1-36 GPIO

29 PB2A J1-37 GPIO

30 PB2B J1-38 GPIO

32 PB2C J1-39 GPIO

34 PB2D J1-40 GPIO

36 PCLKT1_1/PB3A J1-41 Y1

37 PB3B J1-42 GPIO

38 PCLKT1_0/PB3C J1-43 GPIO

39 PB3D J1-44 GPIO

43 PB5A J2-21 GPIO

44 PB4B J2-22 OSC_EN

45 PB4C J2-37 SW2

46 PB4D J2-23 SW3

47 PB5A J2-24 GPIO

48 SLEEPN J2-25 GPIO/SW

1

49 PB5C J2-26 GPIO

50 PB5D J2-20 GPIO

51 PR9B J2-19 GPIO

52 PR9A J2-18 GPIO

53 PR8B J2-17 GPIO

54 PR8A J2-16 GPIO

55 PR7D J2-38 SW1-8

56 PR7C J2-39 SW1-7

57 PR7B J2-40 SW1-6

58 PR7A J2-41 SW1-5

59 PR6B J2-42 SW1-4

61 PR6A J2-43 SW1-3

63 PR5D J2-44 SW1-2

64 PR5C J2-45 SW1-1

65 PR5B J2-46 LED D9

66 PR5A J2-47 LED D8


Table 2. Device I/O Connections (Continued)


6


Expansion Header

The MachXO Starter board includes two Samtec board-to-board connector footprints (connectors not included) forexpansion purposes. All MachXO I/O pins, JTAG signals and board voltages are connected to these pads. Refer toTable 3 for MachXO connections to the expansion headers. Programming pins can be referenced in the Program-ming Headers sections of this guide. Power connections are listed in Table 3.

Table 3. Expansion Connector Power Connections

The connectors are Samtec part number QTH-030-01-F-D-A. Mating connectors are Samtec part number QSH-030-01. A mechanical drawing with placement dimensions is available from Lattice.


69 PR3D J2-50 LED D5

70 PR3C J2-51 LED D4




76 PR2A J2-15 GPIO

77 PT5C J2-14 GPIO

78 PT5B J2-13 GPIO

79 PT5A J2-12 GPIO

80 PT4F J2-11 GPIO

81 PT4E J2-10 GPIO

82 PT4D J2-9 GPIO

83 PT4C J2-8 GPIO

85 PCLKT0_1/PT4B J2-7 GPIO

86 PCLKT0_0/PT4A J2-6 GPIO

87 PT3D J2-5 GPIO

89 PT3C J1-45 GPIO

91 PT3B J1-46 GPIO

94 PT3A J1-47 GPIO

95 PT2F J1-48 GPIO

96 PT2E J1-49 GPIO

97 PT2D J1-50 GPIO

98 PT2C J1-51 GPIO

99 PT2B J1-52 GPIO

100 PT2A J1-53 GPIO

1. By shorting R201 with a 0 ohm resistor.

Power Supply Expansion Connector Pin

3.3V J2-1,J2-2,J2-3,J2-4, J2-55,J2-56,J2-57, J2-58,J2-59,J2-60

ADJ J1-1,J1-2,J1-3,J1-4

1.2V J1-26,J1-27,J1-28, J1-29,J1-30

GNDJ1-31,J1-54,J1-55, J1-56,J1-57,J1-58, J1-59,J1-60, J2-27, J2-28,J2-29,J2-30, J2-31,J2-32,J2-33, J2-34,J2-35,J2-36, J1 and J2 Center

Table 2. Device I/O Connections (Continued)


7


Prototype Area

The MachXO Starter Evaluation Board contains a 0.8” x 1.0” plated through hole prototype area. The holes arespaced on 0.1” centers and are not connected to any MachXO device pins.

Programming Headers

A 1x10 programming header is provided on the MachXO Starter Evaluation Board, providing access to theMachXO JTAG port. The header is compatible with all Lattice ispDOWNLOAD cables. The pinout for the header isprovided in Table 4.

Important Note:

The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWN-LOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAGpins. Failure to follow these procedures can in result in damage to the MachXO device and render the board inop-erable.

An ispDOWNLOAD cable is included with purchase of the ispLEVER design tools. Cables may also be purchasedseparately from Lattice. Visit the Lattice web store to learn more at: www.latticesemi.com/store.

Table 4. JTAG Programming Header Connections

Power Setup

Power is supplied to the PCB via the supplied 5V AC/DC transformer. The DC input jack is a 2.5mm, positive tipsize connector. Input voltage should not exceed 9V DC. 800mA low dropout regulators provide V

CC

core and V

CCIO

voltages. The adjustable voltage regulator output can be modified by changing the value of resistor R153. Theequation for calculating V

ADJ

is as follows:

V

ADJ

= 1.25 * (1 + R2/120)

Table 5 shows some common voltages, and the appropriate resistor value for setting each voltage. Resistancegiven is for the closest standard value. Resistor pads are 0805 component size.

JTAG Programming Function JP1 Pin Number (1x10) Mach XO Device Pin Expansion Connector Pin

+3.3V 1 N/A N/A

TDO 2 31 J1-34

TDI 3 33 J1-35

N/C 4 N/A N/A

N/C 5 N/A N/A

TMS

1

6 26 J1-33

GND 7 N/A N/A

TCK

1

8 28 J1-32

N/C 9 N/A N/A

N/C 10 N/A N/A

1. Please note that some versions of the MachXO Starter Evaluation Board may have an incorrect silkscreen marking for these pins on the printed circuit board. Please follow the connections guidelines in Table 4, and not the silkscreen markings on the board.

8


Table 5. Adjustable Voltage Resistor Values

Ordering Information

Technical Support Assistance

Hotline: 1-800-LATTICE (North America)+1-503-268-8001 (Outside North America)

e-mail: [email protected]: www.latticesemi.com

Revision History

© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are aslisted at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks oftheir respective holders. The specifications and information herein are subject to change without notice.

ADJ Voltage R153 Resistor Value

3.3V 200

Ω

2.8V 150

Ω

2.5V 120

Ω

1.8V 51

Ω

1.5V 24

Ω

Description Ordering Part NumberChina RoHS Environment-Friendly

Use Period (EFUP)

MachXO 256C Evaluation Board - Starter LCMXO256C-S-EV

Date Version Change Summary

— —

Previous Lattice releases.

March 2007 01.3

Added Ordering Information section.

April 2007 01.4

Added important information for proper connection of ispDOWNLOAD (Programming) Cables.

10

9


Appendix A. PCB Schematics

Figure 2. MachXO Starter Evaluation Board Expansion Port

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

LE

D0

LE

D2

LE

D6

LE

D4

LE

D3

LE

D7

LE

D8

SW

6S

W7

SW

5S

W4

SW

3S

W2

SW

1S

W0

IO3

2IO

35

IO3

6

IO4

3IO

44

IO4

5IO

46

IO4

7IO

48

IO4

9IO

50

IO5

1IO

52

IO4

2IO

41

IO4

0IO

39

IO3

8IO

37

IO3

0IO

31

IO3

3IO

34

IO6

1IO

60

IO5

9IO

58

IO5

7

IO5

5IO

54

IO5

3IO

29

IO2

8IO

27

TC

K

IO2

6IO

25

IO2

4IO

23

IO2

2IO

21

IO5

6

TD

IT

DO

IO0

IO1

IO2

IO3

IO4

IO5

IO6

IO8

IO9

IO1

0IO

11

IO1

3IO

14

IO1

5IO

16

IO1

7

IO2

0IO

19

TM

S

IO1

8

IO1

2

IO7

LE

D5

LE

D1

LE

D[8

..0

]

SW

[7..

0]

IO[6

1..

0]

LE

D[8

..0

]

SW

[7..

0]

IO[6

1..

0]

TD

IT

DO

TC

KT

MS

+3.

3V+

3.3V

VC

C_

AD

J

+1.

2V

Titl

e

Siz

eD

ocu

me

nt

Nu

mb

er

Re

v

Da

te:

She

eto

f

XO

-ST

R-S

CH

B

Mac

hX

O S

tart

er P

CB

- E

xpan

sio

n P

ort

A

13

We

dn

esd

ay,

Ju

ne

29

, 2

00

5

AB

6

AB

16

CB

3

DB

19

BB

14

DB

9

BB

3

CB

9

AB

1

CB

18

DB

15

BB

9

AB

12

DB

4

AB

7

BB

17

CB

4

AB

17

CB

14

DB

10

BB

4

CB

10

AB

2

DB

18

AB

15

BB

10

BB

13

DB

5

AB

8

CB

5

BB

20

CB

17

DB

14

DB

11

BB

5

CB

11

AB

3

AB

20

BB

11

BB

16

CB

13

DB

6

AB

9

CB

6

DB

17

AB

14

CB

20

BB

12

BB

6

DB

1

AB

4

BB

19

CB

12

CB

1

DB

13

DB

7

BB

1

AB

10

CB

7

AB

18

BB

15

DB

20

BB

7

CB

16

DB

2

AB

5

DB

12

CB

2

CB

19

AB

13

DB

8

BB

2

AB

19

CB

8

BB

18

AB

11

CB

15

J1 QT

H-0

30-0

1-F

-D-T

R

11

22

33

44

55

66

77

88

99

1010

1111

1212

1313

1414

1515

1616

1717

1818

1919

2020

2121

2222

2323

2424

2525

2626

2727

2828

2929

3030

3131

3232

3333

3434

3535

3636

3737

3838

3939

4040

4141

4242

4343

4444

4545

4646

4747

4848

4949

5050

5151

5252

5353

5454

5555

5656

5757

5858

5959

6060

GND 61

GND 62

GND 63

GND 64

BB

8

DB

16

DB

3

J2 QT

H-0

30-0

1-F

-D-T

R

11

22

33

44

55

66

77

88

99

1010

1111

1212

1313

1414

1515

1616

1717

1818

1919

2020

2121

2222

2323

2424

2525

2626

2727

2828

2929

3030

3131

3232

3333

3434

3535

3636

3737

3838

3939

4040

4141

4242

4343

4444

4545

4646

4747

4848

4949

5050

5151

5252

5353

5454

5555

5656

5757

5858

5959

6060

GND 61

GND 62

GND 63

GND 64

10


Figure 3. MachXO Starter Evaluation Board

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

LE

D1

LE

D5

IO2

6

SW

2

SW

6S

W7

SW

3S

W4

SW

1

TD

OT

DI

TMS

TC

K

IO1

IO7

IO4

IO1

2

IO1

4

IO5

IO0

IO1

0

IO0

IO6

IO8

IO1

0

IO1

4IO

15

IO1

7

IO1

IO2

IO3

IO4

IO5

IO7

IO9

IO1

1IO

12

IO1

3

IO1

6

IO1

8IO

19

IO2

0

IO3

2IO

33

IO8

IO9

IO1

1

IO2

IO3

IO1

5

IO1

3

LE

D0

LE

D1

LE

D2

LE

D3

LE

D4

LE

D5

LE

D6

LE

D7

SW

7S

W6

SW

5

SW

4S

W3

SW

2S

W1

SW

0IO

41

IO4

0IO

39

IO3

8

TMS

IO2

1T

CK

IO2

2IO

23

TD

OIO

24

TD

IIO

25

IO2

6IO

27

IO2

8IO

29

LE

D2

IO3

7IO

36

IO3

5IO

34

IO3

3IO

32

IO3

1IO

30

IO4

2IO

43

IO4

4IO

45

IO4

6IO

47

IO4

8IO

49

IO5

0IO

51

IO5

2

IO6

1IO

60

IO5

9IO

58

IO5

7IO

56

IO5

5IO

54

IO5

3

IO4

6IO

45

IO4

4IO

43

IO4

2IO

41

IO4

0IO

39

IO3

8

IO3

6IO

35

IO3

4

IO3

2IO

31

IO3

0IO

29

IO2

8IO

27

IO2

6IO

25

IO2

4IO

23

IO2

2

IO2

0IO

19

IO1

8IO

17

IO1

6

IO3

3

IO2

1

IO3

7

LE

D0

LE

D8

SW

5

SW

0L

ED

3L

ED

4

IO6

LE

D8

LE

D6

LE

D7

IO6

0IO

61

IO4

9IO

48

IO5

2

IO5

0

IO5

5IO

56

IO5

7

IO5

1

IO5

9IO

58

IO5

3

IO4

7

IO5

4

LE

D[8

..0

]

SW

[7..

0]

IO[6

1..

0]

TD

OT

DI

TMS

TC

K

IO3

1

IO3

5

LE

D[8

..0

]

SW

[7..

0]

IO[6

1..

0]

TD

IT

DO

TMS

TC

K

+3.

3V

+3.

3V

VC

CIO

0

+3.

3V

+3.

3V

VC

CIO

0

VC

CIO

1

VC

CIO

1V

CC

IO1

VC

CIO

0

VC

CIO

1

VC

CIO

1

VC

CIO

0

VC

C_

CO

RE

VC

C_

CO

RE

Titl

e

Siz

eD

ocu

men

t N

um

be

rR

ev

Da

te:

Sh

eet

of

B

Ma

ch

XO

Sta

rte

r P

CB

B

23

We

dn

esd

ay,

Jun

e 2

9,

20

05

R41 DNI

GN

D_

44

R53 DNIR52 DNI

IO9

IO2

2G

ND

_2

1IO

23

R131 220

R31 DNI

IO4

1

IO1

1

R123 DNI

D6 LED

R115 DNI

R36 DNI R140 10K

R39 DNI

R116 DNI

GN

D_

51

R47 DNI

R23 DNI

C1

0.1

uF

GN

D_

38

R108 DNI

R4 DNI

R44 DNI

IO4

5

IO5

3

D2 LED

R11 DNI

GN

D_

7

GN

D_

37

GN

D_

56

R19 DNI

GN

D_

59

R101 DNI

IO6

R133 220

SW

31

4

23

IO3

8

IO2

9

R68 DNI

IO4

9

R2 DNIR17 DNI

D8 LED

R71 DNI

R124 DNIIO5

7

R95 DNI

R117 DNI

IO6

2

R107 DNI

R97 DNI

IO3

0G

ND

_2

8

R63 DNI

GN

D_

45

IO1

0

IO1

5

GN

D_

22

IO2

5

R8 DNI

R138 10K

IO1

2

GN

D_

27

R56 DNI

SW

1

SW

DIP

-8C

TS

208

-8

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

R73 DNI

R110 DNI

D3 LED

GN

D_

52

SW

2

EV

Q-Q

WP

01W

14

23

GN

D_

24

R80 DNI

IO4

6

IO5

4

R50 DNI

R75 DNI

R14

5D

NI

R114 DNI

R6 DNI

GN

D_

8

R84 DNI

R77 DNI

GN

D_

23

R88 DNI

GN

D_

60

R46 DNI

IO7

R24 DNI

IO1

8G

ND

_1

7

R126 220

IO3

1

R14 DNI

R3 DNI

R92 DNI

R85 DNI

R78 DNI

R66 DNI

GN

D_

13

IO3

R86 DNI

IO5

5

R28 DNI

R18 DNI

R136 10K

GN

D_

30

R102 DNI

R141 10K

GN

D_

46

R60 DNI

IO1

6G

ND

_1

5

R1 DNI

IO1

3

GN

D_

3

R76 DNI

R128 220

GN

D_

29

R106 DNI

R96 DNI

R134 10K

IO3

2

GN

D_

53

GN

D_

26

R62 DNI

R59 DNI

IO3

9

IO4

7

IO5

8

GN

D_

1

R120 DNI

R111 DNI

GN

D_

25

GN

D_

41

IO8

R130 220

IO1

9G

ND

_1

8

IO3

3

R70 DNI

GN

D_

14

R118 DNI

R32 DNI

R49 DNI

R122 DNI

R113 DNI

R5 DNI

R7 DNI

R83 DNI

R29 DNI

IO5

6

R40 DNI

GN

D_

32

GN

D_

61

R55 DNI

R45 DNI

R25 DNI

TQ

FP

100

U1

MA

CH

XO

256

PR

3D69

TMS 26

PL9B 27

TCK 28

PB2A 29

PB2B 30

TDO 31

PB2C 32

TDI 33

PB2D 34

VCC 35

PB3A/PCLKT1_1 36

PB3B 37

PB3C/PCLKT1_0 38

PB3D 39

GND 40

VCCIO1 41

GNDIO1 42

PB4A 43

PB4B 44

PB4C 45

PB4D 46

PB5A 47

SLEEPN 48

PB5C 49

PB5D 50

PR

9B51

PR

9A52

PR

8B53

PR

8A54

PR

7D55

PR

7C56

PR

7B57

PR

7A58

PR

6B59

PL3

D6

PL4

A7

PL4

B8

PL5

A9

PR

4A68

PR

4B67

PR

5A66

PR

5B65

PR

5C64

PR

5D63

GN

DIO

062

PR

6A61

VC

CIO

060

VC

CIO

124

PL3

B4

PL7

C19

PL9

A23

PL2

A1

PL8

A21

GN

DIO

125

PL3

C5

PL3

A3

PL2

B2

PL8

B22

PL7

D20

PL5

D/G

SR

_N14

PL5

B11

PL6

A15

PL5

C13

VC

CIO

110

PL6

B/T

SA

LL16

PL7

A17

GN

DIO

112

PL7

B18

PT5A79

PT5B78

PT5C77

PR2A76 GN

DIO

075

VC

CIO

074

PR

2B73

PR

3A72

PR

3B71

PR

3C70

PT2B99PT2A100

PCLKT0_1/PT4B85

GND84

PT4C83

PT4D82

PT4E81

PT4F80

PT2C98

PT2D97

PT2E96

PT2F95

PT3A94

GNDIO093

VCCIO092

PT3B91

VCC90

PT3C89

VCCAUX88

PT3D87

PCLKT0_0/PT4A86

D1 LED

GN

D_

39

R13 DNI

R91 DNI

R37 DNI

R30 DNI

IO4

2

GN

D_

16

IO5

0

GN

D_

4

IO1

4

R132 220

R34 DNI

GN

D_

31

R38 DNI

R27 DNI

R15 DNI

D7 LED

GN

D_

54

R103 DNI

R42 DNI

R51 DNI

IO4

0

IO4

8

R65 DNI

IO5

9

GN

D_

2

R21 DNI

R139 10K

R14

210

K

R105 DNI

R93 DNI

IO3

4

GN

D_

42

IO1

R22 DNI

IO2

0G

ND

_1

9

R61 DNI

IO3

5

R58 DNI

Y1

33.3

3MH

z

EN

1

GN

D2

OU

T3

VC

C4

R99 DNI

IO2

6

R72 DNI

GN

D_

49

GN

D_

34

GN

D_

62

R100 DNI

R14

310

K

GN

D_

40

R10 DNI

IO4

3

R67 DNI

IO5

1

D5 LED

R81 DNI

R48 DNI

GN

D_

5

GN

D_

11

R74 DNI

R112 DNI

GN

D_

33

GN

D_

9

R82 DNI

GN

D_

57

IO4

R137 10K

R89 DNI

GN

D_

47

R54 DNI

R135 10K

R125 220

IO1

7

D4 LED

R90 DNI

R79 DNI

IO2

4

R35 DNI

IO6

0

R87 DNI

R26 DNI

R16 DNI

R69 DNI

GN

D_

43

IO2

R119 DNI

R43 DNI

IO2

1G

ND

_2

0

IO3

7

R127 220

R64 DNI

IO2

7

R20 DNI

GN

D_

50

R104 DNI

R94 DNI

IO3

6G

ND

_3

6

GN

D_

55

R20

1

DN

I

IO4

4

IO5

2

D9 LED

GN

D_

6

GN

D_

12

GN

D_

35

R98 DNI

R129 220

R14

410

K

IO2

8

GN

D_

58

IO5

GN

D_

48

R9 DNI

GN

D_

10

R33 DNI

R57 DNI

JP1

HE

AD

ER

1X101 2 3 4 5 6 7 8 9 10

R121 DNI

R109 DNI

IO6

1

R12 DNI XO

-ST

R-S

CH

11


Figure 4. MachXO Starter Evaluation Board – Power Section5 5

4 4

3 3

2 2

1 1

D

D

C

C

B

B

A

A

VI N

VI N

V

I N

+3

.3 V

+3

.3 V

+1

.2 V

V C

C_

AD

J

VC

C_

CO

RE

V

CC

I O0

V

CC

I O1

V C

C_

AD

J +

3.3

V

V C

CI O

0

V C

CI O

1

VC

C_

CO

RE

+

1.2

V

+3

.3 V

Ti tl

e

Si z

e D

o cu

me

nt

Nu

mb

er

Re

v

Da

te :

Sh

ee

t o

f

XO

-ST

R-S

CH

B

Mac

hX

O S

tart

er P

CB

– P

ow

er S

ecti

on

A

33

W

e d

n esd

ay ,

Ju

ne

29

, 2

00

5

C1

3

0. 1

uF

+

C4

10

uF

C1

7

0. 1

uF

R1

57

*D

NI

R1

50

DN

I

U4

RC

11

17

X /S

OT

223

GN D 1

VO

UT

2

VI N

3

TA

B

4 +

C7

10

uF

J4

PW

R J

AC

K

3 2 1

R146 22 0

C8

0. 1

uF

D1 2 RE D

C1

2

0. 1

uF

C1

6

0. 1

uF

+

C2

10

uF

R 1

49

1

2 0

+

C5

1 0

uF

D1 0 RE D

R1

51

0

C1

1

0. 1

uF

R 1

53

12

0

R154 220

C1

5

0. 1

uF

+

C6

1 0

uF

U3

RC

11

17

X/ S

OT

223

GN D 1

VO

UT

2

VI N

3

TA

B

4

R1

48

0

U2

RC

11

17

X/ S

OT

223

GN D 1

VO

UT

2

VI N

3

TA

B

4 +

C3

10

uF

R1

52

DN

I

C1

0

0. 1

uF

R2

00

DN

I

C1

4

0. 1

uF

TP

0

R

*NO

TE

: S

ilksc

ree

n m

ark

ing

s a

re r

eve

rsed for

R156 a

nd R

157

on b

oard

s m

ark

ed a

s R

ev.

B.

15

6*

0

R1

47

12

0

C9

0. 1

uF

12


Appendix B. PCB Layout Diagrams

Figure 5. MachXO Starter Evaluation Board Layout Diagrams

Figure 1. Top Silkscreen

Figure 3. Solder Side Layout

Figure 2. Component Side Layout

Figure 4. Bottom Silkscreen

Date post:	12-Dec-2021
Category:	Documents
Upload:	others
View:	2 times
Download:	0 times

MachXO™ Starter Evaluation Board - Lattice Semi

Documents