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MAJOR PROJECT Mid Semester Evaluation
MAJOR PROJECTEnd Semester Evaluation
Designing of ALU and Reducing the Multiplication Complexity using Ancient Mathematics
Group Members
Siddharth (9911102336)
Mehul Garg (9911102255)
Aditya Gahlaut (9911102157)
Project Mentor
Mr. Sidhartha S. Rout
Introduction
Basic Arithmetic and Logical Unit of the central processing unit of a computer is responsible for
Arithmetic Operations
Logical Operations
Shift Operations
The aim of this project is to modify the conventional multiplication algorithm in ALU using Vedic mathematics in order to improve the efficiency of the process.
Conventional Multiplication
In general, ALU uses binary multiplication technique as explained below
The numbers are multiplied
shifted to the left
All the outputs are added
Drawbacks
No. of intermediate values increases with the no. of
of bits used.
Time intensive because calculation of each value
requires one clock cycle.
Existing Alternate Methods
Array Multiplier
Advantages:
Regular Layout
Less Design Time
Disadvantages:
Worst case delay is proportional to
the width of the multiplier. Hence,
not suitable for large bits.
Existing Alternate Methods
Tree Multiplier
Advantages:
Small Delay
Disadvantages:
Complex Layout
Irregular wires
Not suitable for negative inputs
Existing Alternate Methods
Nikhilam Sutra Based Multiplier
Advantages:
1.Reduces the complexity of multiplication
Disadvantages:
Not suitable for negative inputs
Existing Alternate Methods
Booths Multiplier
Advantages:
1.Reduces the number of partial products
Disadvantages:
Complexity of the circuit in generating the
partial product bits.
Our Methodology
We are using URDHAV TRIYAKBHAYAM Sutra based Multiplier.
Advantages:
For a given number of bits,
Area consumption is least
Power consumption is least
Delay is least
Speed is maximum
All these factors results in the desired outcome
of the multiplication block.
4*4 Bit Vedic Multiplier using Urdhav Triyakbhyam
Arithmetic And Logical Unit
The conventional ALU is splited into three modules:
Arithmetic Module
Logical Module
Shift Module
For 32-bit ALU, a 33bit 4:1 MUX is used.
Any particular arithmetic, logical or shift operation is selected according to the selection inputs S0 and S1.
The final output of the ALU is selected by the set of multiplexers with selection lines S2 and S3.
10
32-bit Conventional Arithmetic Logic Unit
32-bit Proposed Arithmetic Logic Unit containing separate Multiplication Block
Simulation Results
4-bit Addition
4-bit Subtraction
Simulation Results
Left Shift Operation
Simulation Results
Right Shift Operation
Simulation Results
4-bit * 4-bit Multiplication
Simulation Results
Application Specific Low Power Design of ALU
Typical designs of an ALU:
1. Tree Structure 2. Chain Structure
All functional components are connected in parallel to the multiplexer.
Generally, fast
Demands more area and hence power consumption is high.
All functional components are concatenated through a series of small multiplexers.
Comparatively slow
Demands less area and hence power consumption is comparatively low.
References
Anvesh Kumar, Low Power ALU Design by Ancient Mathematics, IEEE Vol.5, pp. 862-865,2010.
Yu Zhou and Hui Guo, Application Specific Low Power ALU Design, IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, pp. 215-220,2008.
Syed Shahzad Hussain Shah, Muhammad Naseem Majoka, and Gulistan Raja, DESIGN AND IMPLEMENTATION OF 32-BIT VEDIC MULTIPLIER ON FPGA, First International Conference on Modern Communication & Computing Technologies (MCCT'14)
G.Vaithiyanathan, K.Venkatesan, S.Sivaramakrishnan, S.Siva and S. Jayakumar, SIMULATION AND IMPLEMENTATION OF VEDIC MULTIPLIER USING VHDL, International Journal of Scientific & Engineering Research Volume 4, Issue 1, January-2013.
Anju, PERFORMANCE COMPARISON OF VEDIC MULTIPLIER AND BOOTH MULTIPLIER, International Journal of Engineering and Advanced Technology (IJEAT) ISSN: 2249 8958, Volume-2, Issue-5, June 2013
Literature Review(dspace.unimap.edu.my/dspace/bitstream/...)
SarwagyaChaudhary, IMPLEMENTATION OF AN ARITHMETIC LOGIC UNIT USING AREA EFFICIENT CARRY LOOK-AHEAD ADDER AND BOOTHS MULTIPLIER, International Journal of Scientific & Engineering Research Volume 7, Issue 7, July 2013.