Major Threats to Satelites

8/6/2019 Major Threats to Satelites

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EF: Interference in CommunicationsI)A Major Threat to Satellites Radio Systems inow Earth Orbit

Reinaldo PerezJet Propulsion Laboratory

8003 South Corona Way, Littleton, CO 80122phone:303-977-5845, fax:303-9714306, mail:[email protected]

Introductiongeosynchronous orbit (GEO) have experienced serious or catastrophic failures includinginterruption of desired communicationsdueFspec ia lly to non linear interference. It hasbeen shown that severe electrostatic discharges from spacecraft dielectric surfaces cansustain high discharge currents capablef disabling key avionics components posing athreat to satellite communications.Short Summary

Surface chargingof spacecraft surfaces in LEO and GEO orbit environmentsscaused primarily by electrons with high energies during magnetospheric substorms. Thepotentials reached during charging events depends on the total current balance amongseveral types of effects. Differential charging occurs when partsf a spacecraft arecharged at different negative potentials relative to each other.n this typeof chargingstrong electric fields develop. When the electric fields exceed critical values electrostaticdischarges (ESD) can cause not only EM1 but can pose potential threatso spacecrafthardware.

The physics involved in the charging mechanisms in spacecraft at geosynchronousand low earth orbits is addressed. We address the discharge mechanism involved in anESD event. Modeling the discharge mechanism from solar array surfaces and thermal--blankets surfaces as shown in Figure.The induced current from these ESD events cancause severe satellite malfunction in communication systems.

Over the last two years several satellites in Low Earth Orbit (LEO) and

nPACE PLASMA>alar Array Cross Section

Ground 3to StructureFigure 1 . Lumped Element Parameters for ESD Event Betweena Solar Array and Cable.

References:[l] Launchspace Magazine, Major Space Losses 1994-1998, October 1998.
mailto:email:[email protected]:email:[email protected]:email:[email protected]


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q,->.(a) Rip-Flop Upset

C-OtJ~put

AmplifierResponseOalay Time

(c )Amplifier UpselI .- .. .- . -"- f . "" ""_ _ _

Figure 9.27. Examples of upset from discharges transients pulses.

'Ile upset thresholds for representative logic families are given in Table 9.9 . The upset level (e.gnoise margin) for commonly used logic families vary from a few hundred milli-electron-volts to afew volts. Typical upset energy level threshold range from 1 to 50 nanojoules.


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LogicFamily

D1-LI'ILIT1-LSCLCMOSCMOSCMOS

55I55.2510I S

Typical GateQuiescentPowerDissipation(IllW)

51530250.000025 .0.00010 "0.00023

lypicalPropagationDeleyW )

t '1-3010852451612

TypicalSignalLine IX I TypicalSignal

L O WM in0.70.45.0NA1 .s3.04.4

---

I'yp-1.21.27.50.22.24.26.5-

r

I Impdance(ohms)

H i g hMin IlighowTyp0.7 3.8 50 1400.2.4 I .7 K

45050.0.560000.0.0 12K00.4 1.57.17A16K40.0.0

Logic Typical

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Table 9.9.Typical Upset Tllresllold andCharacteristics of Some Logic families9.12 Component DamageComponent damage is a permanent change in one or more electrical characteristics of a circuitcomponent, Circuit components are vulnerable to thermal damage and electrical breakdown whenstressed by dielectric discharge transients. The damage energy threshold for various circuitcomponents for a 100 nS rectangular ransientpulse s shown in Figure 9.28. Thedamagethreshold level ranges from 10 nJ for microwave diodes to several hundred nanojoules for variouslogic families.


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Ttonsmlor

IT 1 SIC

JFET

1145CMOSISOS

T

Figure 9.28.Permanent damage energy threshold of components for 100 nS pulse.For semiconductors, the most ommondischargeransient damage mechanism is localizedthernlalunawayriggered by electro thermal o v e r - s t r e s s 3 This condition produces aresolidified melt channel across the junction once the transient is removed where the melt channelappears electrically as a low resistance shunt across the junction. Junction damage is most likelyto occur when the discharge ransient reverse biases the junction and drives it into secondbreakdown. Forward stressed junctions also failbut ypicallyhave damage thresholds that arethree to ten timeshigher than reverse stressed junctions. For integrated circuits, metallizationburnout and gate oxide breakdown (for MOS devices) are also prominent failure tnechanisms.


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III -"II

Figure 9.29.Pulse power failure depedence on pulse width for discrete semiconductorsDevice1 N750A1 N7561N9141N3 600IN41481N40032N9 182N22222N28572N2907A2N30192N3440'kt = k, k2 = 1/2

ZenerDiodeDiodeDiodeDiodeTransistorTransistorTransistorTransistorTransistorTransistor

20.40.0960.180.01 12.20.00860.110.00850.10.441 . 1

352.5577

30603060140300

VBD(V,4.78.2757575200 -

Table 9.10. Damage Constants and Junction Breakdown Voltages for Some Typical DiscreteSemiconductors.


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Tramitfor Damago Modal

$TCqE

IC Terminal Oomage ModelPower3

Figure 9.30.Transient pulse failure models for transistors, diodes, and integrated circrlilsDevice Category

Table 9.11. Typical Junction Bulk Resistance for Discrete Semiconductors0.2.0igh power transistor (e-b)1 .o0.0ow fiequency transistor (e-b) 0.0550.0ectifier diodes0.255.0ignal diodes0.1.oener diodes Forward Bias (ohms)everse Bias (ohms)

For integrated circuits, kl and k2 are determinedexperimentallywhenpossible. For thecasewhere test data is no t available, typical. valuesof these coeflicients fo r different types of integratedcircuitshavebeendetermined by tests a nd are given in Table 3.12. Tight ntegratedcircuitmanufacturing tolerances and standard circuit designs haveallowed ntegratedcircllits to he


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grouped by their tecl~nology nto genetic failure classesand their terminals categorized into one ofthe following types: input terminal, output terminal, and power terminal. The IC terminal failuremodel consists of a resistor representing the terminalsbulk resistance m d voltage sourcerepresenting the terminals reverse breakdown oltage.

Category

0.554nputTL0.00359utput0.00216nput11LY

l*enniImlnlnilK I

Output 0.0594Power 0.0875DIZ Input 0.01x7,Output 0.0040Power 0.0393ECL Input 0.152Output 0.0348Power 0.456MO S Input 0.0546Output 0.0014Power 0.105Linear Input 0.0743Output 0.0 139

-Kz0.6890.7220.3840.5080.5550.5800.7060.5760.4410.5580.4930.4830.8 190.5430.5090.714

V OD(V )-- 71.36557I1200.70.73 00.G377

I b(ohms)

162.44 018.920.825.215.830.615.77.88.99.211.610.413.25. 5

Lower 95%Kt

0.000520.000980.120.00960.0260.00460.0120.0090.0450.00310.220.00630.000420.0380.00540.0045

Uppcr 95K2

0.008960.0132. 60.390.71)0.0410.01360.170.5 10.3970.9350.470.00460.291.010 . 0 4 3

I LTable 9.12.Damage Constants and Failure Parameters for Various Logic families.From the failure tnodels for discrete semiconductorsand integrated circuits, we find the failurevoltage, Vp, and failure current IF , at the device terminalsare expressed as

VI;.= V, + I ,R ,

where VO s the terminals breakdown voltage, Re is the terminals bulk resistance and P, is theterminals failure power given previously. The conditions for failure to occur when a circuit isstressed by a discharge transients is as follows:

1 ) the discharge ransient current produced at the terminals of the transistor, diode, or integratedcircuit must be equal to or exceed I& where IF is obtained from equation 9.9 above. D is aderating factor o account for statistical variations in device failure thresholds. D is 3 for P, values


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r CarrierBaseband+ Spread-spectrumncodingProcessing

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Sideband Splatter1') Deviations from therequiredresponselaw inthetransmittermodulatorcausingspectrumbroadening. A)(/",SSB, DSB systems.mneration(z)Intarnal Harmonic Deviations from thel inoar i ty of atransmitter inalamplif ier *Intennodulatian and more s ignals narossmodulation") nixing of two ornon linear eleme nt.Resultingmult ipl icat ivemixture of boths i g n a l s

s p l a t t e r e x c e p t a ta ower le ve lOsci l lator Noise Similar t o sideband

- Fi l ter ing

-Balanced circuits-Fi l t er ing-Wave trap-Fi l t er ing

- Qi l t e r i n ggood oacillatorr-Qaaign of very

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Inheol lowingpplies:(1 ) Output o i nonlinear element plus narrowband f i l t e r centered a tcarrier Y, . Input function is X ,.

( 2 ) output of nonlineardevice isY - a, + a,x 4 %xa *. . . . + ak x t

where x - x , ( t ) + Cos wc t( 3 ) U t Signal 1

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For

T a b 1 0 l a . FRI PROBLEMS I N TRANSMITTERS.


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Y X 0.oIIL.r IBm c x m uBroadband Noise

Co-ChannelInterference

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I F ChannelInterference

spurious Respon8e(''"

Intermodulation LCrossmodulation

Desensitization

B R I X ? D I 6 C l X P T I O MO I ?MILEMN0i.e from naturalshot , o lar ,atmospheric) rman-made(discharqas,e lec tron ic dev ices ,antennabohavior)Signal fromcommunicationmources arefrequencynear thecenter requency ofreceiverPenetration ofunvantad rignalacentered a t one ofthe I P Channel8 ofthe receiverHonlinearities nearly stage givesrise t o harmonicso f incomingmignals Inonl inaar i t i e s nthe mixer andfrequencymultiplication i nloca l osc i l la tor

8 O U r C e 8 (thermal ,

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In the fo l lov inqppl ie s :

MZTEOD O I6UPPRE6SIOM-Limiting Lblanketingbeforebroadband noise i 5f i l t e r a d n tho IFamplif ier

-Good care nf requencyamsignment

-Solact ive of theinput RP circuitand/or stra y path smust be con tro lle d-Fi l t er ing 'prior t omixer

-Fi l t er ing

-Fi l t er ing pr ior toreceiver

( I ) Mixing -ration:

and the rssul t of y - y , + y2 f sT a b l e lb . FRI PROBLEMS I N RECEI VERSk


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L i E N G T H OF W I R E SL1 = WIRE INDUCTANCE OF S O U R C E C I R C U I T2, IMPEDANCE OF S O U R C E C I R C U I TcGl= A P A C I T A N C E T OGROUND IN S O U R C E C I R C U I Tv, * VOLTAGE OF S O U R C E C I R C U I Tz1 = LOAD IMPEDANCE OF S O U R C E C I R C U I Tcc = C O U P L I N GC A P A C I T A N C Ez2 SOUCE IMPEDANCE OF V I C T I MI R C U I TZL * LOAD IMPEDANCE OF V I C T I MC I R C U I Tc C A P A C I T A N C E T OROUND IN V I C T I MGz C I R C U I TL12 RITUAL INDUCTANCE

ZL[CCZ ,2, - L,,] v,V ( Z J - [ -- I

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~ ~ " . " """" . '--m rFigure 9.26.Equivalent circuits for plates, cylinder, and disc.

9.1 Circuit U r n

Circuit upset is a nonpermanent alteration of a circuit or component operational state tha t is self-correcting or reversible by automatic or snar~ualmeans. Some examples of upset are provided inFigure 9.27. The conditions for upset to occur when a circuit is stressed by a discharge transientare as follows:


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I De vi ce s Library II Schematicapture I

I . Floor Planning III c IParasitic ExtractionI Timing Simulation I

Signal Integrity Analysis

P C 6 Router -.

Pos t RoutingSignal IntegrityA

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Worst Case Analysis*

Final Data Checkin g

OUTPUT TO MANUFACTURING-RELIABLE PCB DESIGN PROCESS THAT ASSUR ES RIGHT THE FIRST TIME PERFORM

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Major Threats to Satelites

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