Manfred Meyer & IDT & ODTManfred Meyer & IDT & ODT

mmeyer@eso.orgmmeyer@eso.org

15 Okt 200915 Okt 2009

11

Detectors for Astronomy 2009, Detectors for Astronomy 2009, ESO Garching, 12-16 OktESO Garching, 12-16 Okt

Detector Data Acquisition Hardware Designs Detector Data Acquisition Hardware Designs and Features of NGC and Features of NGC

((NNew ew GGeneral Detector eneral Detector CController) ontroller)

NGC NGC

First Light First Light ImageImage20052005

Acquisition System OverviewAcquisition System Overview

Acquisition System – Useful ToolsAcquisition System – Useful Tools

When setting up a detector …

Monitoring Signals Monitoring Signals

Front Panel Basic Board NGC

Two Clock Monitors

VideoMonitor

Two ConvertUtility SignalSignalMonitors

LED’s

Monitor Selection via GUI

Acquisition System – Useful ToolsAcquisition System – Useful Tools

Verifying data flow …

Video Data Simulator Video Data Simulator (Four Channel System)(Four Channel System)

Simulated video data show channel numbers

Simulated Video Data show CounterValues(Counter is incrementedon each Conversion Strobe)

Simulation Mode Selection via GUI

OneChannel

OneChannel

Acquisition System – Video ChannelsAcquisition System – Video Channels

Video ChainVideo Chain

High Speed ADC’sHigh Speed ADC’s

Acquisition System – Bias, ClockAcquisition System – Bias, Clock

Low Frequency System Noise with H2RGLow Frequency System Noise with H2RG

The Hawaii-2RG array has 4 rows and columns of The Hawaii-2RG array has 4 rows and columns of reference pixels around the arrayreference pixels around the array

Even though good noise performance isEven though good noise performance isachieved (9.55e RMS) when the reference pixel achieved (9.55e RMS) when the reference pixel subtraction is activated, this is not the case if subtraction is activated, this is not the case if the reference subtraction is switched off. the reference subtraction is switched off.

Without reference subtraction the noise Without reference subtraction the noise measured is increased by a factor of two. In this measured is increased by a factor of two. In this operating mode the detector system suffers from operating mode the detector system suffers from strong low frequency noise and the readout strong low frequency noise and the readout noise is 19e RMSnoise is 19e RMS

MeasurementMeasurementss on D on Detetector Bias ector Bias VoltageVoltage

(Four Video Channels shown)(Four Video Channels shown)

Test with a bias voltage as input to the video chain

Image shows low frequency noise on the bias voltage ( same input is applied to all four video channels )

OneChannel

Ceramic Cap TRC = 0.05s

Simple Things ?Simple Things ?Detector Bias GenerationDetector Bias Generation

Detector Bias Cleanup and Resulting Detector Bias Cleanup and Resulting Image Image

(All Double Correlated)(All Double Correlated)Tantalum Cap TRC = 1s

Detector ClocksDetector Clocks

Acquisition System - PreamplifierAcquisition System - Preamplifier

Detector Preamplifier Detector Preamplifier (Single Ended Input)(Single Ended Input)

Detector Preamplifier Detector Preamplifier (Differential Input) (Differential Input)

Acquisition System - SequencerAcquisition System - Sequencer

Sequencer

Most simple designMost simple designBut :But :•Detector readout difficult Detector readout difficult to set-upto set-up•Not user friendlyNot user friendly

Sequencer(realized in FPGA)

EOP = End of patternRSP = Read speed

REP = Number of Repetitions

Contains read-out patterns start addressesand sequence code to be executed

Contains read-out patterns

Sequencer Code Function and Code Interpretation Time

(Sequence RAM)

SequencerExample : PICNIC Array Readout

Sequence Pattern (Extract)

All programming in simple syntax and ASCII code

NGC

Design and

Applications

Conventional Approach :Conventional Approach :Acquisition System (IRACE)Acquisition System (IRACE)

CommunicationCommunication and Data Transferand Data Transfer

SequencerSequencer Clock and BiasClock and BiasAcquisitiAcquisitionon

Module(Module(s)s)

PCI PCI InterfaceInterface

NGC SystemNGC SystemNew Design Principle : New Design Principle :

No Parallel Bus No Parallel Bus Communication and Data Transfers Communication and Data Transfers

on High Speed Serial Links with 2 GBit/son High Speed Serial Links with 2 GBit/s

NGC System in Minimum Configuration:NGC System in Minimum Configuration:Basic Board, Backplane and Transition Basic Board, Backplane and Transition

BoardBoard

See Demo Set-up in Council Room

NGC SystemNGC SystemComponent : PCI Back-EndComponent : PCI Back-End

Back-End

PCI BUS Interface

XILINX IP

TX COM #10

RX COM #10

Header #02

STATUS REG # 14

COMMAND REG #1C

VIDEO FIFO Header #01

PCI REGISTERS SLAVE IF

MASTER IF

Rx

Tx

DOWNSTREAM LINK

Back-EndBack-End

Function is based on the XILINX Function is based on the XILINX Virtex Pro FPGA XC2VP7 FF 672 Virtex Pro FPGA XC2VP7 FF 672

Back-End PCI is a 64 Bit PCI boardBack-End PCI is a 64 Bit PCI board FPGA contains PCI interface toFPGA contains PCI interface to Communication functionsCommunication functions DMA data channelDMA data channel Status and CommandStatus and Command Direct interface from FPGA to PCI Direct interface from FPGA to PCI

without glue logicwithout glue logic

PCI master and PCI slave are PCI master and PCI slave are independentindependent

Scatter – Gather DMA implemented Scatter – Gather DMA implemented

Communication and data transfers Communication and data transfers all on serial link with RocketIO all on serial link with RocketIO transceiverstransceivers

Handshake communication to Handshake communication to Front-EndFront-End

Data rate on one channel between Data rate on one channel between front and back-end ~ 200MByte/sfront and back-end ~ 200MByte/s

PCI Back-EndPCI Back-End

NGC SystemNGC SystemComponent : Basic BoardComponent : Basic Board

RX COM

Rx NEXT LINK IF

STATUS REG

Tx

Tx

Rx

SEQUENCER

AQ MANAGER

AQ FIFO 1

AQ FIFO

CLOCK and BIAS

TX COM

DOWNSTREAM RX LINK

On Board ADCs

DOWNSTREAM TX LINK

CONFIG REGISTER

SYSTEM RESET

MONITOR

TELEMETRY

LINK CONFIG

UPSTREAM RX LINK

UPSTREAM TX LINK

Function is based on the XILINX Virtex Pro Function is based on the XILINX Virtex Pro FPGA XC2VP7 FF 672 FPGA XC2VP7 FF 672

FPGA contains link interface for FPGA contains link interface for

communication and data transfer with communication and data transfer with RocketIO transceivers, sequencer, system RocketIO transceivers, sequencer, system administration, interface to acquisition, administration, interface to acquisition, clock and bias, telemetry and monitoringclock and bias, telemetry and monitoring

Four ADC channels ( 16 or 18Bit)Four ADC channels ( 16 or 18Bit)

18 clocks, 20 biases18 clocks, 20 biases

TelemetryTelemetry

MonitoringMonitoring

Data rate on one channel between front-Data rate on one channel between front-end modules and front to back-end ~ end modules and front to back-end ~ 200MByte200MByte

Handshake for communication to back-endHandshake for communication to back-end

Galvanic isolated trigger input and control Galvanic isolated trigger input and control outputs outputs

Front-End Basic BoardFront-End Basic Board

Front-End Basic BoardFront-End Basic Board

Contains everything to read a CMOS sensoror a CCD with up to four video channels

16 or 18 Bit ADC’s Standard 1 MS/s Optional 3 MS/s

NGC SystemNGC SystemComponent : 32 Channel Video BoardComponent : 32 Channel Video Board

COM IF

Rx NEXT LINK IF

STATUS REG

Tx

Tx

Rx

SEQUENCER For Stand-alone

Tests only

AQ MANAGER

AQ FIFO 1

AQ FIFO

TX COM

DOWNSTREAM RX LINK

On Board ADCs

DOWNSTREAM TX LINK

CONFIG REGISTER

SYSTEM RESET

MONITOR

LINK CONFIG

UPSTREAM RX LINK

UPSTREAM TX LINK

OFFSET DAC REGISTER

AQ 32 BoardAQ 32 Board

AQ 32 BoardAQ 32 Board

32 Video channels16 or 18 Bit ADC’s Standard 1 MS/s Optional 3 MS/s

Double-Correlated Sampling Readout Noise = 6.9 e RMS

ApplicationsApplicationswithwith

NGC Used as the Building NGC Used as the Building PlatformPlatform

AO Interface for Tip/Tilt CorrectionAO Interface for Tip/Tilt Correction

Back-End PCI in LINUX Workstation

FPGA

RxTx

RxTx

NGC Front-End

FPGA

RxTx

RxTx PICNIC

Fiber Link “Aurora” Protocol

Fiber Link “SFPDP” Protocol

AO - SPARTA Real Time System

ApplicationApplication : : Copy Science Data to SFPDP Link Copy Science Data to SFPDP Link

of Real Time Processing System SPARTAof Real Time Processing System SPARTADetector Control done with NGC BEDetector Control done with NGC BE

All done with standard NGC Back-End BoardAll done with standard NGC Back-End Board- only the Firmware was modified- only the Firmware was modified

AO Interface for Tip/Tilt CorrectionAO Interface for Tip/Tilt Correction

Front-End Side

Back-End Side

PCI Back-End in LINUX workstation

FPGA

Fiber Duplex

Connection

RxTx

RxTx

PMC Interface Interferometry FPGA

RxTx

RxTx

VME LCU Board

MVME 6100

RxTx

FPGA

Detector Front-End (DFE)

RxTx RxTx

PMC Based Low Latency DMA Channel

Application : Real Time Processing Application : Real Time Processing for Interferometry for Interferometry

DFE is controlled by DFE is controlled by the PCI Back Endthe PCI Back End Data Transfer from Data Transfer from DFE to VME PMC for DFE to VME PMC for InterferometryInterferometry

Data also routed Data also routed through to PCI BE through to PCI BE for set-up for set-up

PMC Based Low Latency DMA Channel

Back-End PCI in LINUX Workstation

FPGA

Fiber Duplex

Connection RxTx

RxTx

NGC2ASIC Interface

FPGA

RxTx

RxTx

ASIC

CLOCK

COMUNICATION

SCIENCE DATA

POWER

H2RG

LVDS Connections

Detector Signals

NGC to ASICNGC to ASIC

ApplicationApplication : Communication Channel to/from ASIC : Communication Channel to/from ASIC Receiver of Science Data from ASIC Receiver of Science Data from ASIC all mapped on NGC Fiberlink all mapped on NGC Fiberlink

NGC to ASIC – Test Set-upNGC to ASIC – Test Set-up

NGC to ASICNGC to ASIC

Image ofImage ofBare Mux Bare Mux H2RGH2RG

NGC High SpeedNGC High Speed Eight 40MS/s Eight 40MS/s

Pipeline Pipeline ADC’sADC’s

Ten Clocks with Ten Clocks with Tr/Tf < 5nsTr/Tf < 5ns

Eight BiasesEight Biases

TelemetryTelemetry

Clock and Video Clock and Video MonitorsMonitors

System is System is modularmodular

FinFin