Manual Mint Starterkit Version PA 3.7 September 7, · PDF filePicture 23: Mint Starterkit...

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Prepared Document Number

Manfred OrtmannApproved Checked Date Revision Storage

20090907 PA 3.7 Mycable01

Receiver: Info:M. CarstensBehrens mycable GmbH

Manual

Mint Starterkit

( Working name : 467 / GDC Board )

Version PA 3.7 September 7, 2009

http://www.fujitsu.com/emea/services/microelectronics

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Developer’s Manual for the Mint Starterkit

Summary

This manual provides detailed technical information for system architects, hardware and software developers, who work with the Mint Starterkit version PA3 for evaluation and development purpose.

Enclosures

None.

Product Information

The board is populated with the 32bit CPU MB91F467DAPFV, Flash memory, SDRAM, SRAM, interfaces as UART, Ethernet, CAN, USB, SD memory card, GPIOs, video inputs and outputs and an interface for different GDC modules.

Up to now two GDC modules are available for this board, a module with the MINT and a module with the LIME. For details see the manuals for these modules.

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Revision History

Version Date Sign Description

PA 3.1 20080325 mo Create this document

PA 3.2 20080409 mo 2.2.3 CPU – Mode pin description added

PA 3.3 20080505 mo 2.2.3 CPU – Internal comment removed

PA 3.4 20080506 mo 2.2.3 CPU – Mode pin description corrected

PA 3.5 20080514 mo Product name

PA 3.6 20090811 mo 2.2.3 CPU DMA

PA 3.7 20090907 mo Board name 467 / GDC Board change to Mint Starterkit

Contact Information

mycable GmbHMichael CarstensBehrens( hardware and commercial )

Email [email protected]

Tel. +49 4321 55956 55

mailto:[email protected]

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Table of Contents1 OVERVIEW....................................................................................................................6

1.1 Manual Scope........................................................................................................61.2 Putting into Operation.............................................................................................6

2 MINT STARTERKIT....................................................................................................7

2.1 System Architecture...............................................................................................72.2 Function Units........................................................................................................9

2.2.1 Power Supply...............................................................................................102.2.2 Reset...........................................................................................................102.2.3 CPU.............................................................................................................112.2.4 Graphic Display Controller ( GDC ) Module..................................................152.2.5 Serial Ports...................................................................................................212.2.6 Ethernet........................................................................................................222.2.7 Universal Serial Bus ( USB )........................................................................232.2.8 CAN Interfaces.............................................................................................252.2.9 Video Inputs................................................................................................272.2.10 Video Outputs.............................................................................................282.2.11 Buttons.......................................................................................................332.2.12 LEDs.........................................................................................................332.2.13 GPIOs ......................................................................................................342.2.14 Secure Digital ( SD ) Memory Card Interface.............................................37

2.3 Hardware Variants................................................................................................392.4 Placement of Components...................................................................................402.5 Mechanical Dimensions........................................................................................42

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1 Overview

1.1 Manual Scope

This manual provides detailed technical information about the Mint Starterkit for system architects, hardware and software developers covering:

• System architecture description and users manual

• Hardware architecture

• Mechanical information

It is the engineer’s reference for evaluation, system development and prototyping based on the module. This document covers all available hardware versions regarding their configuration options and revision state.

1.2 Putting into Operation

The Mint Starterkit can be used without GDC module.

But do not plug the GDC module if the power supply is switched on !

Under this condition circuits can be damaged ! Details for power supply connection see chapter power supply.

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2 Mint Starterkit

2.1 System Architecture

The system architecture of the Mint Starterkit is shown in picture 21.

Pic. 21: Mint Starterkit block diagram

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Picture 22: Mint Starterkit top side

Picture 23: Mint Starterkit bottom side

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2.2 Function UnitsOverview in the available interfaces:

– 10/100 Ethernet

– 2x serial ports

– 2x CAN

– DVII

– Power supply

– Video Input

– USB

– GPIOs

– Video Output

– SD Memory Card Slot

– GDC module interface

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2.2.1 Power Supply

Connect the Mint Starterkit with a power supply between 6 and 25 V DC and approximate 10 Watt at connector X100.

Be aware to use the correct polarity as shown in picture 24.

Pic. 24: Polarity of the Mint Starterkit power supply connector

A protection against wrong polarity ( D109 ) and overcurrent ( F100 ) is implemented but a too high current can damage the power supply or can produce great heat !Do not plug the GDC module when the power supply is on !

The required voltages + 3.3 V and + 5.0 V will be regulated from the dual switching power regulator LT1940EFEPBF from Linear Technologies ( U100 ) on the board.

2.2.2 Reset

The triple processor supervisor TPS330733DGN from Texas Instruments ( U102 ) generates a poweron reset and monitors the + 3.3 and + 5.0 V power supply. Also if the reset button SW100 will be pressed the supervisor circuit generates a reset.

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2.2.3 CPU

The CPU MB91F467DA from Fujitsu ( U500 ) is used. External 2x 1 Gbit Flash Memory ( U580, U581 ), 128Mx16 SDRAM ( U591 ) and 512kx16 SRAM ( U592 ) are connected.

The mode pins of the CPU MD_2 and MD_1 are set fixed to logical '0'.

The logical level of mode pin MD_0 can be set with switch SW500.

If the switch is open the MD_0 pin is logical '1'. If the switch is closed the MD_0 pin is logical '0'.

MD[2:0] = '000' : Internal ROM Vector mode, Reset vector access: internal Flash.

This is the standard setting where the internal Flash memory of the device is available.

( see Hardware Manual MB91460 Serie Chapter 9 Reset 4.3 MD: Mode Pins )

MD[2:0] = '001' : External ROM Vector mode, Reset vector access: external.

After old information for DMA access the CPU pins 132 ( P17_4 / PPG4 ), 133 ( P17_5 / PPG5 ) and 134 ( P17_6 / PPG6 ) should be used for DREQ, DTACK and DRACK.

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After actual information for DMA access the CPU pins 189 ( P13_0 / DREQ ), 190 ( P13_1 / DACKX0 ) and 191 ( P13_2 / DEOTX0 ) should be used for DREQ, DTACK and DRACK.

The resistors R502, R513 and R515 have to be populated application dependent.

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The CPU MB91F467DA has following features

Core frequency 96 MHz

Resource frequency 48 MHz

Watchdog

Bit Search

Reset Input

Clock Modulator

DMA 5 ch

MPU/EDSU 16 BP (8 MPU ch)

Flash external 1024 kB + 64 kB

Flash Protection

Dbus RAM 32 kB

GP RAM 32 kB

Direct mapped cache 8 kB

BootROM 4 kB

RTC 1 ch

Free Running Timer 8 ch

ICU 8 ch

OCU 8 ch

Reload Timer 8 ch

PPG 12 ch

PFM 1 ch

Sound Generator 1 ch

UpDown Counter 3 ch

C_CAN 3 ch (32 msg buffer)

LINUSART 5 ch (4 ch FIFO)

I2C 3 ch

FR external bus 32bit address / 32bit data 26bit address / 32bit data

External Interrupts 14 ch

SMC 6 ch

ADC (10bit) 24 ch

Alarm Comparator 1 ch

Low voltage detection

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Clock Supervisor

Following picture shows the block diagram of the CPU.

More details see datasheet.

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2.2.4 Graphic Display Controller ( GDC ) Module

For a GDC module the 2.54 mm connectors X300 and X301 ( SSM120SDVP from Samtec ) and the 1.27 mm connector X302 ( FLE12001GDVAP from Samtec ) are available.

Detailed information on the GDC module see the manual to this board.

Do not plug the GDC module when the power supply is on !

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Following table shows the assignment of pins, signals and function from the connector X300:

Pin Signal Function

1 GND Ground

2 GND Ground

3 CPU_D16 CPU data signal
















19 VCC33 + 3.3 V

20 VCC33 + 3.3 V

21 VCC33 + 3.3 V

22 VCC33 + 3.3 V

23 GDC_XCS CPU chip select

24 GDC_RD CPU read

25 GDC_XWE0 CPU write enable 0


27 GDC_XRDY CPU ready

28 GDC_XBS CPU XBS

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Pin Signal Function

29 GDC_DTACK CPU DT acknowledge

30 GDC_RACK CPU R acknowledge

31 GDC_DREQ CPU data request

32 GDC_XINT CPU interrupt

33 I2C_SCL I2C SCL

34 I2C_SDA I2C SDA

35 GND Ground

36 GND Ground

37 RESET#0 Reset

38 GDC_BCLKI CPU BCLKI

39 GND Ground

40 GND Ground

Table 21: Pin assignment X300


Pin Signal Function

1 GND Ground

2 GND Ground

3 NC Not connected

4 GDC_A2 CPU address signal











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Pin Signal Function






20 VCC33 + 3.3 V

21 VCC33 + 3.3 V







28 NC Not connected

29 NC Not connected

30 NC Not connected

31 NC Not connected

32 NC Not connected

33 GND_CV Analog ground to X480and X481

34 GND_CV Analog ground to X480and X481

35 AVIN0 Analog video input 0 from X480

36 NC Not connected

37 AVIN1 Analog video input 1from X481

38 NC Not connected

39 GND Ground

40 GND Ground



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Pin Signal Function

1 GND Ground

2 GND Ground







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Pin Signal Function











19 CPU_A24 CPU address signal

20 VCC33 + 3.3 V

21 VCC33 + 3.3 V




25 EXT_GPIO1 GPIO 1

26 EXT_GPIO0 GPIO 0

27 S_VSYNC Vertical sync

28 EXT_GPIO2 GPIO 2

29 S_DE Data enable

30 S_HSYNC Horicontal sync

31 S_CSYNC Composite sync

32 S_DCLK Data clock

33 AOUTB Analog video output blue

34 GND Ground

35 GDC_AVS Analog ground

36 GDC_AVS Analog ground

37 AOUTR Analog video output red

38 AOUTG Analog video output green

39 GND Ground

40 GND Ground

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2.2.5 Serial Ports

UART 0 is available at the 9pin SubD female connector X800 with RS232 inputs and outputs.UART 1 is available at the 9pin SubD female connector X801 with RS232 inputs and outputs.

As transceiver with enhanced electrostatic discharge ( ESD ) protection the MAX3243EIPW ( U800, U801 ) are used.

Following table shows the assignment of pins, signals and function from the UART connector X800. Connector X801 is identical. For X801 the index 0 has to be changed to 1.

Pin Signal Function

1 RS232_0_CD Data carrier detect

2 RS232_0_TXD Transmit data

3 RS232_0_RXD Receive data

4 RS232_0_DSR Data set ready

5 GND Ground

6 RS232_0_DTR Data terminal ready

7 RS232_0_CTS Clear to send

8 RS232_0_RTS Request to send

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Pin Signal Function

9 RS232_0_RI Ring indicator

Table 24: Pin assignment X800 and X801

2.2.6 Ethernet

At the RJ45 connector X600 the Ethernet interface is available.The Ethernet interface is implemented with the 10/100 Ethernet controller LAN9218 ( U600 ) from SMSC. The LAN9218 is connected to the 32Bit processor interface of the CPU.

The LAN9218 is fully IEEE 802.3 10BASET and 802.3u 100BASETX compliant and supports HP AutoMDIX. The LAN9218 includes an integrated Ethernet MAC and PHY, large transmit and receive data FIFOs with a highspeed host bus interface to accommodate high bandwidth and high latency applications.The LAN9218 also supports features which reduce or eliminate packet loss. Its internal 16kByte SRAM can hold over 200 received packets. If the receive FIFO gets too full, the LAN9218 can automatically generate flow control packets to the remote node or assert backpressure on the remote node by generating network collision.

The default ethernet setting by pin strapping at the SPD_SEL pin of U600 is speed 100 Mbps, halfduplex and auto negotation enabled because this pin will be strapped to VCC by the 10k Ohm resistor R609.It is possible to strap this pin to ground by a 0 Ohm resistor R612 then the settings would be speed 10 Mbps, halfduplex and auto negotiation disabled.

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The FIFO_SEL pin of U600 can be strapped by 0 Ohm resistor R613 to ground.If this resistor is not populated the FIFO_SEL pin is strapped by the 10k Ohm resistor R610 to VCC then all accesses to U600 are to the RX or TX data FIFO and the upper addresses A[7:3] are ignored.

As default the AMDIX_EN pin of U600 is strapped by the 10k Ohm resistor R611 to VCC so AutoMDIX is enabled. That means if the user plugs in either a direct connect LAN cable or a crossover patch cable U600 is capable of configuring the TPO and TPI twisted pair pins for correct transceiver operation. It is possible to strap this pin to ground by a 0 Ohm resistor R614 then AutoMDIX is disabled.

2.2.7 Universal Serial Bus ( USB )

UART 2 from the CPU is connected with an Incorporating Clock Generator Output and FTDI ChipID™ Security Dongle FT232R ( U601 ) from Future Technology Devices International Ltd.. This is an USB to serial UART interface.

The USB interface is available at connector X601.

Following table shows the assignment of pins, signals and function from the USB connector X601.

Pin Signal Function

1 VCC 3.3 V power supply for USB device

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Pin Signal Function

2 D USB data signal minus

3 D+ USB data signal plus

4 ID Not used

5 GND Ground


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2.2.8 CAN Interfaces

At the 9pin SubD female connector X700 are two CAN interfaces CAN0 and CAN1 available.

The CAN transceiver SN65HVD234D from Texas Instruments ( U700 and U701 ) provides transmit and receive capability between the differential CAN bus and the JADE with its implemented CAN controllers.

The RS pin 8 of the SN65HVD234 provides for three modes of operation: highspeed,slope control or lowpower standby mode. The highspeed mode of operation is selected by connecting pin 8 directly to ground, allowing the driver output transistors to switch on and off as fast as possible with no limitation on the rise and fall slope. The rise and fall slope can be adjusted by connecting a resistor to ground at pin 8, since the slope is proportional to the pin’s output current. Slope control is implemented with a resistor value of 10 k to achieve a slew rate of 15 V/us and a value of 100 k to achieve 2.0 V/s slew rate. The SN65HVD234 enter a lowcurrent standby mode during which the driver is switched off and the receiver remains active if a high logic level is applied to pin 8. The local protocol controller reverses this lowcurrent standby mode when it needs to transmit to the bus.

The SN65HVD234 enters an ultralowcurrent sleep mode in which both the driver and receiver circuits are deactivated if a low logic level is applied to EN pin 5. The device remains in this sleep mode until the circuit is reactivated by applying a high logic level to pin 5.

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120 Ohm termination is configurable per line via switches on board:SW700: 120 Ohm Termination for CAN 0SW701: 120 Ohm Termination for CAN 1

Following table shows the assignment of pins, signals and function from the CAN connector X700:

Pin Signal Function

1 VCC33 3,3V switchable via R702

2 EXT_CAN0L CAN 0 Low

3 GND Ground

4 EXT_CAN1L CAN 1 Low

5 GND Ground

6 GND Ground

7 EXT_CAN0H CAN 0 High

8 EXT_CAN1H CAN 1 High

9 VCC50 5V swichable via R701


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2.2.9 Video Inputs

The Cinch video connectors X480 ( AVIN0 ) and X481 ( AVIN1 ) are connected directly to GDC module interface connector X301 pin 35 and 37 ( Ground pin 33 and 34 ).

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2.2.10 Video Outputs

The digital RGB video output 0 from the GDC module has to be connected to X404 by a cable. The digital RGB video output 1 from the GDC module if availablehas to be connected to X405 by a cable. The type from X404 and X405 is DF1340DP1.25C from Hirose.

The signals from X404 are connected to X402, transmitter SiI164CT64 ( U400 ) and triple 8Bit high speed video digitaltoanalog converter ( DAC ) ADV7125JSTZ240 ( U403 ).

The signals from X405 are connected to X403, transmitter SiI164CT64 ( U402 ) and triple 8Bit high speed video digitaltoanalog converter ( DAC ) ADV7125JSTZ240 ( U401 ).

The type from X402 and X403 is FTSH12001LDVEJP from Samtec.

The transmitter SiI164CT64 ( U400 and U402 ) from Silicon Image uses PanelLink® Digital technology to support displays ranging from VGA to UXGA resolutions ( 25 – 165 Mpps ) in a single link interface. The link interface of U400 is connected to DVII connector X400. The link interface of U402 is connected to DVI connector X401.The SiI164 transmitter has a highly

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flexible interface with either a 12bit mode ( ½ pixel per clock edge ) or 24bit mode 1pixel / clock input for true color ( 16.7 million ) support. In 24bit mode, the SiI164 supports single or dual edge clocking. In 12bit mode, the SiI164 supports dual edge single clocking or single edge dual clocking.The SiI164 can be programmed though the I2C interface. The multifunction address inputs A1, A2 and A3 of U400 are strapped to ground by resistors R409, R410 and R412 so the slave address for readings is 0x71 and the slave address for writings is 0x70. The multifunction address inputs of U402 A2 and A3 are strapped to ground by resistor R423 and R424 and A1 is strapped to VCC by resistor RN402 so the slave address for readings is 0x73 and the slave address for writings is 0x72. The SiI164 support receiver and hot plug detection.

The triple 8Bit high speed video digitaltoanalog converter ( DAC ) ADV7125JSTZ240 ( U401 and U403 ) from Analog Devices convert the digital RGB666 video output signals from the GDC to an analog video signals. Outputs from U403 are connected to DVII connector X400. Outputs from U401 are connected to DVII connector X401 over multiplexer U404 FSAV330MTC ( MPLEX_CTRL ).

Following table shows the assignment of pins, signals and function from the connectors X402 and X403. For X403 the index 0 has to be changed to 1.

Pin Signal Function

1 GND Ground

2 GND Ground

3 VO0_B0 Digital RGB output 0 Data blue








11 VO0_G0 Digital RGB output 0 Data green








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Pin Signal Function

19 VCC33 + 3.3 V

20 VCC33 + 3.3 V

21 VCC33 + 3.3 V

22 VCC33 + 3.3 V

23 VO0_R0 Digital RGB output 0 Data red








31 VO0_HSYNC Video output interface horizontal sync output

32 VO0_VSYNC Video output interface vertical sync output

33 VO0_DE DE / CSYNC

34 VO0_CSYNC DE / CSYNC

35 NC Not connected

36 VO0_CLK_RGBD Video output interface dot clock output

37 I2C_SCL I2C interface 0 SCL

38 I2C_SDA I2C interface 0 SDA

39 GND Ground

40 GND Ground


Following table shows the assignment of pins, signals and function from the UART connector X404 and X405. For X405 the index 0 has to be changed to 1.

Pin Signal Function

1 VCC50 + 5.0 V

2 VCC50 + 5.0 V

3 GND Ground

4 GND Ground

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Pin Signal Function

5 VCC33 + 3.3 V

6 VCC33 + 3.3 V

7 NC Not connected

8 GND Ground

























33 GND Ground

34 GND Ground

35 VO0_CLK Video output interface dot clock output

36 VO0_VSYNC Video output interface vertical sync output

37 VO0_DE Video output interface data enable

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Pin Signal Function

38 VO0_HSYNC Video output interface horizontal sync output

39 GND Ground

40 GND Ground


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2.2.11 Buttons

If the button SW100 which is not labeled will be pressed a reset will be generated.

If the button SW501 which is labeled with ABORT will be pressed the interrupt 0 ( P24_0 ) will be generated.

If the button SW502 which is labeled with TEST1 will be pressed the interrupt 1 ( P24_1 ) will be generated. If the button SW503 which is labeled with TEST2 will be pressed the interrupt 7 ( P24_7 ) will be generated. If the button SW504 which is labeled with TEST3 will be pressed the interrupt 6 ( P24_6 ) will be generated.

2.2.12 LEDs

The RESET LED ( D102 ) is on if the reset is active.

The 3.3V LED ( D106 ) is on if the 3.3 V power supply is on independent of the limits. The 5.0V LED ( D107 ) is on if the 5.0 V power supply is on independent of the limits.

D500 and D503 are free usable LEDs. A logical '0' switches the LED on. A logical '1' switches the LED off.

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Following table shows the assignment of LEDs and GPIOs.

LED GPIO

D500 P25_0

D501 P25_1

D502 P25_2

D503 P25_3

Table 29: LED GPIO assignment

2.2.13 GPIOs

Some GPIOs from the CPU are available at connected X900 FTSH11001LDVKAP from Samtec.

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Pin Signal Function

1 VCC33 + 3.3 V

2 GPIO0 P14_0

3 GPIO1 P14_1

4 GPIO2 P16_4

5 GPIO3 P16_5

6 GPIO4 P16_6

7 GPIO5 P16_7

8 GPIO6 P27_0

9 GPIO7 P27_1

10 GPIO8 P27_2

11 GPIO9 P27_3

12 GPIO10 P27_4

13 GPIO11 P27_5

14 GPIO12 P27_6

15 GPIO13 P27_7

16 GPIO14 P26_0

17 GPIO15 P26_1

18 GPIO16 P26_2

19 GPIO17 P26_3

20 GND Ground


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2.2.14 Secure Digital ( SD ) Memory Card Interface

At SD memory card connector X901 the signals of the SD memory card from the CPU are connected.

The supply voltage SD_CARD_VCC for the SD memory card will be switched from GPIO P14_5. A logical 0 at GPIO P14_5 switches the supply voltage ON.

Following table shows the assignment of pins, signals and function.

Pin Signal Function

1 SD_DAT3 SD data line 3

2 SD_CMD Command line

3 GND Ground

4 SD_CARD_VCC Supply voltage

5 SD_CLK Clock

6 GND Ground




10 SD_XMCD Card detect

11 VCC33 3.3 V Supply voltage

12 SD_WP Write protect


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2.3 Hardware Variants

Up to now only PCB version PA3 without variants is available.

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2.4 Placement of Components

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2.5 Mechanical Dimensions

The Mint Starterkit has a size of 160.0 x 100.0 mm.

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