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© Digital Integrated Circuits2nd Manufacturing
Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective
ManufacturingManufacturingProcessProcess
Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolic
July 30, 2002
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© Digital Integrated Circuits2nd Manufacturing
CMOS ProcessCMOS Process
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A Modern CMOS ProcessA Modern CMOS Process
p-well n-well
p+
p-epi
SiO2
AlCu
poly
n+
SiO2
p+
gate-oxide
Tungsten
TiSi2
DualDual--Well TrenchWell Trench--Isolated CMOS ProcessIsolated CMOS Process
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Circuit Under DesignCircuit Under Design
VDD VDD
VinVout
M1
M2
M3
M4
Vout2
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Its Layout ViewIts Layout View
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The Manufacturing ProcessThe Manufacturing Process
For a great tour through the IC manufacturing process and its different steps, checkhttp://www.fullman.com/semiconductors/semiconductors.html
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oxidation
opticalmask
processstep
photoresist coatingphotoresistremoval (ashing)
spin, rinse, dryacid etch
photoresist
stepper exposure
development
Typical operations in a single photolithographic cycle (from [Fullman]).
PhotoPhoto--Lithographic ProcessLithographic Process
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Patterning of SiO2Patterning of SiO2
Si-substrate
Si-substrate Si-substrate
(a) Silicon base material
(b) After oxidation and depositionof negative photoresist
(c) Stepper exposure
PhotoresistSiO2
UV-light
Patternedoptical mask
Exposed resist
SiO2
Si-substrate
Si-substrate
Si-substrate
SiO2
SiO2
(d) After development and etching of resist,chemical or plasma etch of SiO2
(e) After etching
(f) Final result after removal of resist
Hardened resist
Hardened resist
Chemical or plasmaetch
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CMOS Process at a GlanceCMOS Process at a GlanceDefine active areasEtch and fill trenches
Implant well regions
Deposit and patternpolysilicon layer
Implant source and drainregions and substrate contacts
Create contact and via windowsDeposit and pattern metal layers
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CMOS Process WalkCMOS Process Walk--ThroughThrough
p+
p-epi (a) Base material: p+ substrate with p-epi layer
p+
(c) After plasma etch of insulatingtrenches using the inverse of the active area mask
p+
p-epiSiO2
3SiN
4
(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)
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CMOS Process WalkCMOS Process Walk--ThroughThroughSiO2
(d) After trench filling, CMPplanarization, and removal of sacrificial nitride
(e) After n-well and VTp adjust implants
n
(f) After p-well andVTn adjust implants
p
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CMOS Process WalkCMOS Process Walk--ThroughThrough
(g) After polysilicon depositionand etch
poly(silicon)
(h) After n+ source/drain andp+source/drain implants. These
p+n+
steps also dope the polysilicon.
(i) After deposition of SiO2insulator and contact hole etch.
SiO2
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CMOS Process WalkCMOS Process Walk--ThroughThrough
(j) After deposition and patterning of first Al layer.
Al
(k) After deposition of SiO 2insulator, etching of via’s,deposition and patterning ofsecond layer of Al.
AlSiO2
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Advanced MetallizationAdvanced Metallization
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Advanced MetallizationAdvanced Metallization
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Design RulesDesign Rules
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3D Perspective3D Perspective
Polysilicon Aluminum
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Design RulesDesign Rules
q Interface between designer and process engineer
q Guidelines for constructing process masksq Unit dimension: Minimum line width§ scalable design rules: lambda parameter§ absolute dimensions (micron rules)
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CMOS Process LayersCMOS Process Layers
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+) Green
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Layers in 0.25 Layers in 0.25 µµm CMOS processm CMOS process
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IntraIntra--Layer Design RulesLayer Design Rules
Metal24
3
10
90
Well
Active3
3
Polysilicon2
2
Different PotentialSame Potential
Metal13
3
2
Contactor Via
Select2
or6
2Hole
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Transistor LayoutTransistor Layout
1
2
5
3
Tran
sist
or
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ViasVias and Contactsand Contacts
1
2
1
Via
Metal toPoly ContactMetal to
Active Contact
1
2
5
4
3 2
2
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Select LayerSelect Layer
1
3 3
2
2
2
WellSubstrate
Select3
5
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CMOS Inverter LayoutCMOS Inverter Layout
A A’
np-substrate Field
Oxidep+n+
In
Out
GND VDD
(a) Layout
(b) Cross-Section along A-A’
A A’
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Layout EditorLayout Editor
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Design Rule CheckerDesign Rule Checker
poly_not_fet to all_diff minimum spacing = 0.14 um.
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Sticks DiagramSticks Diagram
1
3
In Out
VDD
GND
Stick diagram of inverter
• Dimensionless layout entities• Only topology is important• Final layout generated by
“compaction” program
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PackagingPackaging
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Packaging RequirementsPackaging Requirements
qElectrical: Low parasiticsqMechanical: Reliable and robustqThermal: Efficient heat removalqEconomical: Cheap
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Bonding TechniquesBonding Techniques
Lead Frame
Substrate
Die
Pad
Wire Bonding
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TapeTape--Automated Bonding (TAB)Automated Bonding (TAB)
(a) Polymer Tape with imprinted
(b) Die attachment using solder bumps.
wiring pattern.
Substrate
Die
Solder BumpFilm + Pattern
Sprockethole
Polymer film
Leadframe
Testpads
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FlipFlip--Chip BondingChip Bonding
Solder bumps
Substrate
Die
Interconnect
layers
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PackagePackage--toto--Board InterconnectBoard Interconnect
(a) Through-Hole Mounting (b) Surface Mount
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Package TypesPackage Types
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Package ParametersPackage Parameters
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MultiMulti--Chip ModulesChip Modules