Mapping the Pathways to “Beyond–CMOS” Technology for
Computation
IanYoungSeniorFellow,TechnologyandManufacturingGroup,
Director,ExploratoryIntegratedCircuits,ComponentsResearch
IntelCorporaBonHillsboro,Oregon
ExploratoryIntegratedCircuitsGroup/ComponentsResearch 1
Energyvs.Delay,AdderCMOS ref
Electronic
Spintronic
Ferroelectric
Orbitronic
Straintronic
ExploratoryIC/ComponentsResearch2
Slower,butnon-volaBle
TFETSub-thresholdSlope• TunnelingprobabilityincreasessharplyattheonsetofSourceValanceBandandChannelConducBonBandoverlap
E
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
0.0 0.1 0.2 0.3 0.4
ID (A/um)
VG (V)
VDS=0.4V
TFET
S
Ch Ch
D D
S
Higher VG Lowers EC(Channel)
60 mV/dec
DensityOfStates
ExploratoryIntegratedCircuitsGroup/ComponentsResearch 3
Figure1:(a)TFETvsMOSFETstructureandprincipleofoperaBon:drive-current(transport)definedbytunneling,steep-SSduetofilteringofhigh-energycarriers.(b)IDSvsVGSforGaSb/InAshet-jn.N-andP-TFET,GeSnhet-jn.N-andP-TFETcomparedwithSiandInAsMOSFET
NaturePhysics4,851-854(2008)
Spin logic device based on spin torque
6ExploratoryIntegratedCircuitsGroup/ComponentsResearch
Vsp
FM1 FM2
Output
NatureNano5,266(2010).
Proposed all Spin Logic Device (ASL)
Delay, ps 10 0 10 1 10 2 10 3 10 4
E n e r
g y , f
J
10 -4
10 -3
10 -2
10 -1
10 0
10 1
CMOS HP
CMOS LV
ITFET
FEFET
BisFET
Inpl ASL
STT/DW SMG
STOlogic
SWD
NML
NAND2
CMOS LP
PMA ASL
PMA imp Anis
PMA imp Anis+Gmix
D.E.Nikonov,I.A.Young,IEEEJournalonExploratorySolid-StateComputaBonalDevicesandCircuits2015
Solid-StateDevicesandMaterials,Sept.27th-30th2015,Sapporo,Japan 7
Summary:
q Benchmarking of Beyond-CMOS Devices is useful to explore new device concepts.
q Spin Logic is an interesting device due to low operating voltage and non-volatility.
§ Needs materials and circuit research q Tunneling FET an attractive option for replacing
CMOS due to it’s steep sub-threshold slope and charge token like CMOS
ExploratoryIntegratedCircuitsGroup/ComponentsResearch 8
Reboo0nhg2015
RecentProgressinSteepSlopeTransistors
SumanDa9a
PennsylvaniaStateUniversity,UniversityPark,PA,USAUniversityofNotreDame,NotreDame,IN,USA
Slide10
SteepSlope(SS)FETs
ü SSFETstoenablecon0nuedoracceleratedsupplyvoltagescaling
SS:SS<kT/q
VGS
IOFF
IOFF
IDS
MOSFET:SS≥kT/q
SteepslopeFETs
Slide11
SS ≈ ln10 1VTW
dVTWdVGS
+ ξ + bξ 2
dξdVGS
⎡
⎣⎢
⎤
⎦⎥ − cV
dψ S
dVGS− cQ
dnSdVGS
voltage-gainusingnega.vecapacitance
carriergainusingcorrela.on,phase
transi.on
interbandtunnelingusingenergyfiltering
LEASTStarnetcenter(SRCandDARPA)atNotreDamefocusesondemonstraBngsteepslopeFETs
Slide12
10-1 100 101 102 103 104 10510-2
10-1
100
101 0.9V
0.6V
HTFET Inverter Si FinFET Inverter
0.1V0.2V0.3V0.4V
0.5V
0.1V
0.2V0.3V
0.4V0.5V
0.6V
Ener
gy p
er c
ycle
(aJ)
Delay (ps)
Lg=20nm
0.0 0.2 0.4 0.6 0.8
VDS=0.3V,0.5V
N-HTFET
22nm Si FinFET
40mV/dec
-0.8 -0.6 -0.4 -0.2 0.010-4
10-3
10-2
10-1
100
101
102
103
104
22nm Si FinFET
44mV/dec
Dra
in C
urre
nt I D
S (µ
A/µ
m)
VDS=-0.3V,-0.5V
P-HTFET
Lg=20nm,EOT=0.5nm Tb=7nm,IOFF=5×10-4uA/um
GaAs0.35Sb0.65In0.7Ga0.3As In0.65Ga0.35As
GaAs0.4Sb0.6
Eb,eff=0.4eV (Quantized) Eb,eff=0.45eV (Quantized)
Gate Voltage VGS (V)
HTFETinverter:EnergyDelayPromise
Courtesy: H. Liu
ü HTFETinvertershowsenergyefficientopera0onoverCMOSatultralowVDDapplica0on(intheory)
VDD Scaling
Slide13
HTFETDemonstraBonPla`orm
NTFET
Gate,Sourceviapadsdeposi0on
TakeAways
Slide14
• TunnelFETs– Materials:interfacedefectcontrol– Devices:scaling,layout,variaBon– Circuits:leveragesub-thresholdCMOSdesigntechniques– Architecture:heterogenousmixedcoretargeBngdimsilicon
• NegaBveCapacitanceFETs– Materials:scaling,switchingspeed,historyeffect– Devices:variaBon,aging,endurance– CircuitsandArchitecture:tuninghysteresis,exploiBngnonvolaBlty
• PhaseTransiBonFETs– Materials:thermalstability,on-offconductancera0o– Devices:monolithicintegraBon,switchingspeed– CircuitsandArchitecture:lowpowerdigitalCMOSandbeyond(neuromorphic,
coupledoscillators)
Moore'sLawforEnergy:Searchingforamilli-VoltSwitch
EliYablonovitch,
Director,NSFCenterforEnergyEfficientElectronicsScience
Reboo0ngCompu0ngSummit4
WashingtonDCDec.11,2015
A problem arises from states where they should not be:
exp{-ΔE/kT}
Conduction band
2d quantum Density of States ~1012 states/cm2eV
Valence band
2d-interface defect density ~1011 states/cm2eV
The low voltage tunnel switch concept demands a higher degree of perfection than previously required in electronics.
Amuchmorechemicalapproachisneeded§ We are placing attention squarely on novel materials systems capable of
producing the most perfect molecular scale device structures, that will be a pre-requisite for future progress. - chalcogenide monolayer structures - molecular synthesized structures
molecularprecursor
doublequantumdotgraphene
G
D
S
G
WSe2
insulator
MoS2
AliJavey YablonovitchFischerSwager
By chemical treatment we have raised the luminescence efficiency of monolayer MoS2 by orders of magnitude to >95%
A. Javey et al, SCIENCE 350, 1065 (Nov. 2015)
Summary
1. The Moore's Law for miniaturization will be replaced by the Moore's Law for Energy.
2. There is up to a 106× reduction available.
3. This will require new Materials Science, including improvement in the new 2d monolayer semiconductors. 4. New architectures would be nice, but the current architecture can be preserved.
Present2015-2030Roadmap• FinFETgoodfor5+5yearsto2025• 2005.NRI:NewSwitch
– Technologyreuse:cousinsofCMOS– Exploremagneto-electriceffects
• 2010.TFETlookspromising,effortincreased– Newmagneto-electricdevicesproposed– MemoryopBonsontheraise
• 2015.TFETgoodfor2020-2025coexistencewithCMOS– Increaseeffortonmagneto-electriclikelywinner(s)– 3DmemoryinproducBon– ResisBvememoryverypromising
• 2020.Magneto-electricearliestinserBon– Somenewmemorymakesitbig
Needs
ResearchFaciliBescapableoffulldeviceprocesscapability
