Archive
March 4 - 7, 2018
Hilton Phoenix / Mesa Hotel
Mesa, Arizona
© 2018 BiTS Workshop – Image: pilgrims49 / iStock
COPYRIGHT NOTICE
The presentation(s)/poster(s) in this publication comprise the Proceedings of the 2018 BiTS Workshop. The content reflects the opinion of the authors and their respective companies. They are reproduced here as they were presented at the 2018 BiTS Workshop. This version of the presentation or poster may differ from the version that was distributed in hardcopy & softcopy form at the 2018 BiTS Workshop. The inclusion of the presentations/posters in this publication does not constitute an endorsement by BiTS Workshop or the workshop’s sponsors. There is NO copyright protection claimed on the presentation/poster content by BiTS Workshop. However, each presentation/poster is the work of the authors and their respective companies: as such, it is strongly encouraged that any use reflect proper acknowledgement to the appropriate source. Any questions regarding the use of any materials presented should be directed to the author(s) or their companies. The BiTS logo and ‘Burn-in & Test Strategies Workshop’ are trademarks of BiTS Workshop. All rights reserved.
www.bitsworkshop.org
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware
Signal Integrity Design
Noel Del Rio (NXP), Don Thompson (RDA)
BiTS Workshop
March 4 - 7, 2018
Conference Ready
mm/dd/2014
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 2
Scope and target application: • Electrical performance as presented in this study are
specific to the hardware. This paper is about a methodology and partnership (i.e. NXP, RDA, Leeno, Yamaichi, other socket vendors…)
• Applicable to any ATE platform Loadboard. This program started on Advantest 93K™, and propagated to Teradyne UltraFlex™.
• Methods and concepts can be applied to industry test sockets, loadboards, connectors, and fixtures.
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 3
Agenda • Software Tools , LAB Validation Setup, and fixtures
– Signal path segment measurement capability
• Bandwidth, Rise/Fall Time, Wave Length
• Signal Path Analysis and Design Target – Metric base assessment of the signal path (i.e. serdes I/O)
• Signal Path – Dielectric Material and PCB Process
– DUT Field or Package Ball Grid
– VIA for 28G
– Test Strategy : Loop Back, and Loop Back Components.
– Test Socket…Welcome to the real world
• Signal Path review, target vs actual measurements
• Conclusion
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 4
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 5
DUT Package Surrogate(Venom RF 5G, UA RF 5G, T4/TV1/LX2 28G)
• Precision electrical interface to enable access at the Pogo-pin top
• It is modeled, simulated, and validated with VNA(Vector Network Analyzer)
• Performance Specifications for 28G
• S21 3dB point >20Ghz
• S11 -11dB to -15dB at 3dB point
• Differential Impedance 100 Ohms +5, -5
• De-embed point up to surrogate balls
Test socket interface (Package surrogate)
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 6
R& D Altanova Confidential and Proprietary
Model and simulation (S21, S11)
results for LX2 package surrogate
Complete signal path to H&S
Connector
Surrogate Performance
Targets (for all lanes)
- S21 3dB point, > 20Ghz
- S-11 @ 3dB point, -15dB
- Differential Impedance
100 Ohms +/- 5
- Correlation or variance
for all lanes(i.e. 32 lanes)
<<< 1dB @ 3dB Point
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 7
TV1 28G Surrogate Validation Setup, S-parameters, and TDR Plots
TV1 Surrogate TDR
Profile, TX & RX Loop TV1 Surrogate S21
Insertion Loss Profile,
TX & RX Loop
TV1 Surrogate S11
Return Loss Profile,
TX & RX Loop
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 8
Test Loadboard Validation Setup
~ 50Ghz Probe setup up differential and
single ended
Application of board connectors and
interfaces for segmented DUT
signal path
Different methodologies and techniques to assess the different segment of the DUT
signal path. Individual, isolated and or combined. Full DUT signal path or accumulated
effects of the different segment
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 9
Loadboard (PCB pad to pad) Measured S21
10G 3db
point
28G 3db
point Ultra-Flex Board S21 budget
10G Test
Socket
S21 budget
28G Test
Socket
S21 budget
10G Test HW
Pass Region
28G Test Hardware Pass Region
• Enable NXP to validate actual board (populated loadboard) against
performance target, models, and simulation results.
• DN populated loadboards undergo 100% VNA performance validation test
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 10
Bandwidth Consideration • DFT (Design for Testability)
• Test Strategy
• Cost
BANDWIDTH ASSESSMENT
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 11
SIGNAL PATH ANALYSIS, what are we dealing with
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 12
Target Metrics
• S21 3db Point is 15 GHz
• S11 ~ (-10db) at 3db point
• Lane to Lane Correlation <1 dB
• Lane to Layer Correlation <1 dB
• Board to Board Correlation
~ 1 dB
• Loop-Back Impedance @ RX
within 10% or 90 Ohm
Differential
DEFINE YOUR DESIGN TARGETS & PARAMETERS
• Defined performance target based on metrics …S-Parameters, TDR impedance profile
• Objective targets vs traditional practice of litany of design-rules and hope it works.
10G
3db
point
28G
3db
point
Ultra-Flex Board S21 budget
10G Test
Socket
S21
budget
28G Test
Socket
S21 budget
28G Test Hardware Pass Region
10G Test HW
Pass Region
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
• Digital Networking has stopped using PCB design-houses and PCB fabrication vendors that can’t present PCB-Process Data (Simulated vs Measured)
• Board validation @ frequency domain is required.
• PCB Trace is the biggest source of loss in the signal path
DIELECTRIC AND PCB FABRICATION PROCESS
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 14
T4: 4 of 32 Lanes 10G
Loadboard
Wide Performance
Variance
Inferior insertion loss plot
32 Lanes 10G Designed
board
3db pt @ ~ 6ghz
Modeled, Simulated, VNA
Tested
High Correlation between
Lanes
Blind Built Board Board with Verifiable
Target Performance T4 Dielectric Meteorwave 2000
Measured Simulated
DIELECTRIC AND PCB FABRICATION PROCESS
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 15
SERDES BALL MAP AND DUTFIELD
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
16 28G Test Hardware Signal Integrity Design
DUTFIELD 28G Summary
• The SERDES BALLMAP location has profound effect on I/O
Performance
• Meet with package designers for preferential ball map profile
• SERDES deep inside the DUTFIELD is most likely to
present challenges for 28G.
• SERDES I/O Profile can impact loadboard design, socket
and cost
• Additional optimization is required to address issues on high
speed I/O s deep inside the grid
• Layer Management is used to mitigate DUTFIELD related
routing issues
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
17 28G Test Hardware Signal Integrity Design
VIA DESIGN as a function of data rate
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 18
• Differential Impedance control closer to
100 Simulation results indicate 28G
performance is attainable
• Base on mature PCB process
• Can be implemented on >300mil thick
boards
• Cheaper than COAX VIA
Twin-Axial Via 28G Summary
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 19
LOOP BACK DESIGN CONSIDERATION
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 20
DUT_TX_P
ATE_TX_P
DUT_TX_N
DUT_RX_P
ATE_TX_N
ATE_RX_P
DUT_RX_N
ATE_RX_N
R247
R28G
R248
R28G
R249
R28G
R250
R28G
C376
C28G
C377
C28G
C1
C_PAD1
C2
C_PAD2
C
CAPACITANCE
ESR
RESISTANCE
ESL
INDUCTANCE
C378
C_PAD1
C379
C_PAD2
C
CAPACITANCE
OUT
L_PAD2
INDUCTANCE RESISTANCE
IN
L_PAD1
ZoZo
LOOP BACK DESIGN CONSIDERATION
R28G Resistor equivalent circuit
C28G Capacitor equivalent circuit
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 21
DUT_TX_P
ATE_TX_P
DUT_TX_N
DUT_RX_P
ATE_TX_N
ATE_RX_P
DUT_RX_N
ATE_RX_N
R247
R28G
R248
R28G
R249
R28G
R250
R28G
C376
C28G
C377
C28G
BSLB 3D Model
LOOP BACK DESIGN CONSIDERATION
Advantages of RC over relay 1. Reliability
2. Eliminate layout related issues resulting
to discontinuities (component size,
impedance control, via count.)
3. Enable the shortest possible trace length
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 22
SUMMARY : (BSLB) Backside Loop Back Module Solution 1. Eliminated ~2 weeks on 16 Week fabrication schedule
2. Lower Cost compare to Embedded RC component
3. Provided option for several configuration: RC, C, Direct to ATE(No loopback)
BSLB Module BSLB Module &
UltraFlex Loadboard
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 23
Test socket(blind built) induced performance degradation
15.000 Ghz 6.000 Ghz
B4 S21 w/o Socket
B4 S21 w/ Socket
15.000 Ghz
10G
28G
28G
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 24
Test Socket Impedance Drop
Unless measured or tested there is no assurance that a test socket for
high speed SerDes I/O test impedance is ~100 Ohms differential or ~50
Ohms for single ended application.
TEST SOCKET, MAJOR SOURCE OF DISCONUITY
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 25
28G Test Socket Target
Performance
S21 0.5 dB Point is 15 GHz
S11 ~ (-15db) at 0.5 dB point
SerDes Lane to Lane Correlation <0.5 dB
Differential Impedance 100 0hms + / - 5%
Insertion Life (i.e. 10k, 20k…500k) cycles
S21 degraded to -5db at 15Ghz
S11 (-15db) at 15 GHz
Differential Impedance is above 90 Ohms
All parameters are to be measured by VNA
(Vector Network Analyzer)
S21
S11
15 Ghz
0.5 dB.
-15 dB.
DESIGN PARAMETERS FOR TEST SOCKET
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 26
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 27
Test Socket S21 Insertion Loss Test Socket S11 Return Loss
Test Socket serdes I/O Models
&
Simulation Results
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 28
Test Socket serdes I/O
Models
&
Simulation Results
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 29
TEST SOCKET DOE SUMMARY:
1. Five test socket vendors provided prototypes 28G capable sockets for the 32 I/O device
(T4): Leeno, Yamaichi, Socket-4B, Socket-4A, RDA
2. Each Socket benchmarked for S-parameters, TDR Impedance Plots, functional,
parametric test. Time 0, 10K to 20K cycles
1. Test temperature as function of typical product flow (25C, 110C, -40C)
2. 400 Mechanical Samples, 100 known good devices use for electrical characterization
for all test conditions
3. Leeno and Socket-4B vendors were selected to continue to the 16 - 28G I/O network
processor (TV1). Yamaichi pursued a mechanical cycling study with NXP (50K cycles).
Note: This is high level summary. Socket DOE is another presentation by itself…
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 30
Case-1: Inductive test socket resulting to rippling
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 31
• SCKT4-B was used for 28G
Characterization
• No performance issues that
can be attributed to SCKT4-B
degradation detected as a
function of insertion
• Rippling was not a major issue
at 20K cycles.
Case-2: Socket manufacturing challenges.
Correlation problem between models and fabrication
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design 32
Case-2: Socket manufacturing challenges.
Correlation problem between models and fabrication
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Leeno R1 TV1 Test Socket
Leeno T4 to TV1 28G Conversion challenges.. We have a case of validation and
instrumentation correlation question
• TV1 R1 Models resulted to inductive pin/socket
• TV1 R2 (Change pin diameter, Change package material with better dielectric
constant)
Case-3: Correlation problem between models and fabrication
28G Test Hardware Signal Integrity Design
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Leeno R2 TV1, S11 and Improve TDR Impedance
50.00
60.00
70.00
80.00
90.00
100.00
110.00
120.00
TIM
E2.S
EC
-2.3
1E
-10
-2.1
3E
-10
-1.9
4E
-10
-1.7
5E
-10
-1.5
6E
-10
-1.3
8E
-10
-1.1
9E
-10
-1.0
0E
-10
-8.1
4E
-11
-6.2
6E
-11
-4.3
9E
-11
-2.5
1E
-11
-6.3
5E
-12
1.2
4E
-11
3.1
2E
-11
4.9
9E
-11
6.8
7E
-11
8.7
4E
-11
1.0
6E
-10
1.2
5E
-10
1.4
4E
-10
1.6
2E
-10
1.8
1E
-10
2.0
0E
-10
2.1
9E
-10
2.3
7E
-10
2.5
6E
-10
2.7
5E
-10
2.9
4E
-10
3.1
2E
-10
3.3
1E
-10
3.5
0E
-10
3.6
9E
-10
3.8
7E
-10
4.0
6E
-10
4.2
5E
-10
4.4
4E
-10
4.6
2E
-10
4.8
1E
-10
S11/S22 TDR (ohms)_TV1_LB#3_Leeno Skt2 Rev2 0 Cycles
lane0_sd1 lane1_sd1 lane2_sd1 lane3_sd1 lane4_sd1 lane5_sd1
lane6_sd1 lane7_sd1 lane0_sd2 lane1_sd2 lane2_sd2 lane3_sd2
lane4_sd2 lane5_sd2 lane6_sd2 lane7_sd2
Imp
eda
nce
(O
hm
s)
Pogo TX
28G Test Hardware Signal Integrity Design
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
28G Test Hardware Signal Integrity Design
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Case-4: Frequency domain performance as function
of insertion cycle
28G Test Hardware Signal Integrity Design
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
37
Performance inflection point was detected in between 40K and 50K cycles
-10.00
-9.00
-8.00
-7.00
-6.00
-5.00
-4.00
-3.00
-2.00
-1.00
0.00
FR
EQ
3.G
HZ
0.6
66
1.3
32
1.9
98
2.6
64
3.3
33.9
96
4.6
62
5.3
28
5.9
94
6.6
67.3
26
7.9
92
8.6
58
9.3
24
9.9
910.6
56
11.3
22
11.9
88
12.6
54
13.3
213.9
86
14.6
52
15.3
18
15.9
84
16.6
517.3
16
17.9
82
18.6
48
19.3
14
19.9
820.6
46
21.3
12
21.9
78
22.6
44
23.3
123.9
76
24.6
42
25.3
08
25.9
74
26.6
427.3
06
27.9
72
28.6
38
29.3
04
S21I/SD2D1 Insertion Loss (dB)_TV1_LB#2_Yamaichi Rev2 50K
Cycles
lane0_sd1 lane1_sd1 lane2_sd1 lane3_sd1 lane4_sd1 lane5_sd1
lane6_sd1 lane7_sd1 lane0_sd2 lane1_sd2 lane2_sd2 lane3_sd2
lane4_sd2 lane5_sd2 lane6_sd2 lane7_sd2
dec
ibel
s (
dB
)
Test HW Pass Region
50.00
60.00
70.00
80.00
90.00
100.00
110.00
120.00
TIM
E1.S
EC
-2.3
0E
-10
-2.1
1E
-10
-1.9
1E
-10
-1.7
1E
-10
-1.5
1E
-10
-1.3
1E
-10
-1.1
2E
-10
-9.1
7E
-11
-7.1
9E
-11
-5.2
1E
-11
-3.2
3E
-11
-1.2
5E
-11
7.3
0E
-12
2.7
1E
-11
4.6
9E
-11
6.6
7E
-11
8.6
5E
-11
1.0
6E
-10
1.2
6E
-10
1.4
6E
-10
1.6
6E
-10
1.8
6E
-10
2.0
5E
-10
2.2
5E
-10
2.4
5E
-10
2.6
5E
-10
2.8
5E
-10
3.0
4E
-10
3.2
4E
-10
3.4
4E
-10
3.6
4E
-10
3.8
4E
-10
4.0
3E
-10
4.2
3E
-10
4.4
3E
-10
4.6
3E
-10
4.8
3E
-10
S11/S22 TDR (ohms)_TV1_LB#2_TX to RX_Yamaichi
Rev2 50K Cycles
lane0_sd1 lane1_sd1 lane2_sd1 lane3_sd1 lane4_sd1 lane5_sd1
lane6_sd1 lane7_sd1 lane0_sd2 lane1_sd2 lane2_sd2 lane3_sd2
lane4_sd2 lane5_sd2 lane6_sd2 lane7_sd2
Imp
eda
nce
(O
hm
s)
Three (3) lanes with
performance
deviations
DUT-Pass all test
No cleaning from
cycle-0 to cycle-50K
Time domain impedance plot will
indicate specific failure on the signal
path. For this case on TIP of the pogo.
Frequency domain plot shows the effect of specific
physical defect across frequency range. Takes out the
guessing game
28G Test Hardware Signal Integrity Design
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
38
Target VS Measured
• Loss estimate and actual
performance measurements are very
close
• All DN loadboard 10G and above
(28G) are VNA tested prior shipment
to NXP
• Focus Test Engineers to the DUT(No
hardware related issue)
• Test hardware Signal Integrity(SI)
performance ascertained before 1st
silicon
28G Test Hardware Signal Integrity Design
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Conclusion 1. Analytical approach is highly recommended for signal integrity design for test
hardware for short wavelength applications.
2. Understanding and quantitative assessment of the signal path is key to ascertain
exposure to sources of discontinuity and signal loss.
3. Definition of performance budget for the Test Hardware Signal Path, in reference to
DUT SERDES 28G I/O requirements, is highly recommended.
4. Performance Validation of Test Hardware for 28G I/O application and higher is a
necessity. Compliance to design target performance must be confirmed not
assumed.
5. PCB vendor SI capability and PCB process control is a major area for improvement
in the industry .SI design models must be tied to PCB fabrication process
6. Socket vendors need to tool up for SI model and performance validation to ensure
compliance of its product. Socket Vendors need VNA to validate 28G test socket
performance.
28G Test Hardware Signal Integrity Design
Designed Right - PCB Simulation-Characterization BiTS 2018 Session 3B Presentation 3
March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org
References:
– Signal Integrity Simplified (Eric Bogatin),
ISBN 0-13-066946-6
– High Speed Digital Design(Howard
Johnson, Martin Graham), ISBN 0-13-
395724-1
– Practical RF Circuit Design (Les Besser,
Rowan Gilmore), ISBN 1-58053-521-6
– Production Testing of RF and System on
a Chip(SOC) for wireless
Communications(Keith B. Schaub, Joe
Kelly), ISBN 1-58053-692-1
40 28G Test Hardware Signal Integrity Design