March 8, 2006“Bus Stuttering”1 Bus Stuttering : An Encoding Technique To Reduce Inductive Noise...

March 8, 2006 “Bus Stuttering” 1

Bus Stuttering : An Encoding Technique To Reduce Inductive Noise In Off-Chip Data Transmission

DATE 2006Session 5B: Timing and Noise Analysis

Presenter: Ganesh Venkataraman Texas A&M University

Authors: Brock J. LaMeres Agilent TechnologiesSunil P. Khatri Texas A&M University

Contact: [email protected]


Agenda

• Problem Motivation

• Our Solution

• Experimental Results


Why is IC Packaging Important?• All Electronic Circuitry Resides in a Package

- The package serves many purposes:

1) Protection of devices 2) Density Translation 3) Thermal Dissipation 4) Manufacturing Standardization

• Packaging Limits System Performance


Why is packaging limiting performance?• IC Design/Fabrication is Outpacing Package Technology

- We’re seeing exponential increase in IC transistor performance - >1.3 Billion transistors on 1 die [Fall IDF-05]


Why is packaging limiting performance?• Packages Have Been Designed for Mechanical Performance

- Electrical performance was not primary consideration

- IC’s limited electrical performance- Package performance was not the bottleneck


Why is packaging limiting performance?• VLSI Performance Exceeds Package Performance

- Packages optimized for mechanical reliability, but still used due to cost

- IC performance far exceeds package performance

On-Chip

- fIC > 4GHz - large signal counts - exponential scaling

Package

- fpkg < 2GHz - limited signal counts - linear scaling


Why is packaging limiting performance?• Package Interconnect Contains Parasitic Inductance

- Long interconnect paths

- Large return current loops

Wire Bond Inductance (up to 10s of nH)


Why is packaging limiting performance?• Package Parasitics Limit Performance

- Excess inductance causes package noise - Noise limits how fast the package can transmit data

1. Supply Bounce (due to self inductance of VDD/GND bondwires)

2. Signal Coupling (due to mutual inductance between nearby signal bondwires)


Why is packaging limiting performance?• Aggressive Package Design Helps, but is expensive…

- 95% of ASIC design-starts are wire bonded - Goal: Extend the life of current packages

QFP – Wire Bond : ~ 4.5nH $0.22 / pin

BGA – Wire Bond : ~ 3.7nH $0.34 / pin

BGA – Flip-Chip : ~ 1.2nH $0.63 / pin


Our Solution

“Encode Off-Chip Data to Avoid Inductive Cross-talk”

• Avoid the following cases:

1) Excessive switching in the same direction = reduce ground/power bounce

2) Excessive X-talk on a signal when switching = reduce edge degradation

3) Excessive X-talk on signal when static = reduce glitching


Our Solution

• This results in:

1) A subset of vectors is transmitted that avoids inductive X-talk.

2) The off-chip bus can now be ran at a higher data rate.

3) The subset of vectors running faster can achieve a higher throughput over the original set of vectors running slower (including overhead).

Throughput Throughput

of less vectors of more vectors

at higher data-rate at lower data-rate


Bus Stuttering CODEC

• Intermediate States are Inserted Between Noise Causing Transitions- Stutter states limit the number of simultaneously switching signals - The source synchronous clock is gated during stutter state

Package

Un-encoded:

BC Vector Sequence Causes

Noise Limit Violation

Package

Encoded:

BC Vector Sequence is

eliminated using Stutter

BA C

BA C

BA C

Encoder

Core

Core

No Encoding

w/ Encoding

BA C

BA C

BA C

BA C

BA C

BA C A B stutter C

A B stutter C

A B stutter C


• Simultaneous Switching Noise

Supply Bounce• Induced Self Voltage

Glitching• Coupling onto Non-Switching Signals

Edge Degradation• Coupling onto Switching Signals

• Data Dependent Delay

Bus Stuttering CODEC – Noise Sources

ni

selfi

diV L

dt

11

kk

couple k

diV M

dt


Terminology

Define the following:n = width of the bus segment

where each bus segment consists of n-2 signalsand 1 VDD and 1 VSS.

j = the segment consisting of an n-bit bus. j is the segment under consideration. j-1 is the segment to the immediate left. j+1 is the segment to the immediate right. each segment has the same VDD/VSS placement.


Terminology

Define the following:

= the transition (vector sequence) that the ith signal in the jth segment is undergoing, where

= 1 = rising edge = -1 = falling edge

= 0 = signal is static

This 3-valued algebra enables us to model mutual inductive coupling of any sign

jiv

jivjivjiv


Terminology

Define the following coding constraints: Supply Bounce

if is a supply pin, the total bounce on this pin is bounded by Pbnc.Pbnc is a user defined constant.

Glitching

if is a signal pin and is static ( = 0), the total magnitude of the glitch from switching neighbors should be

less than P0 . P0 is a user defined constant.

Edge Degradation if is a signal pin and is switching ( = 1/-1), the total magnitude of the coupling from switching neighbors should be greater than P1 / P-1. This coupling should not hurt (should aid)

the transition. P1 / P-1 is a user defined constant.

jiv

jiv

jiv

jiv

jiv


Terminology

Also define the following:

p = how far away to consider coupling (ex., p = 3, consider K11, K12, and K13 on each side of

the victim)

kq = Magnitude of coupled voltage on pin i when its qth neighbor p switches:

pq ip

dik M

dt


Methodology

•For each pin vij within segment j, we will write a series of constraints

that will bound the inductive cross-talk magnitude.

•The constraints will differ depending on whether vij is a signal or

power pin.

•The coupling constraints will consider signals in adjacent segments (j+1, j-1) depending on p.


Methodology

Glitching : coupling is bounded by P0

Example:

v2j =0, and p=3. This means the three adjacent neighbors on either side of

v2j need to be considered (v4

j-1, v0j, v1

j, v3j, v4

j, v0j+1).

Note we use modulo n arithmetic (and consider adjacent segments as required).

v2j = 0 (static)

-P0 < k3·(v4j-1) + k2·(v0

j ) + k1·(v1j) + k1·(v3

j) + k2·(v4j) + k3·(v0

j+1) < P0

The constraint equation is tested against each possible transition and the transitions that violate the constraint are eliminated.

0 0 0 0


Methodology

Edge Degradation : coupling is bounded by P1 and P-1

Example:

v2j = 1 or -1, and p = 3. This means the three adjacent neighbors on either

side of v2j need to be considered (v4

j-1, v0j, v1

j, v3j, v4

j, v0j+1).

v2j = 1 (rising)

k3·(v4j-1) + k2·(v0

j ) + k1·(v1j) + k1·(v3

j) + k2·(v4j) + k3·(v0

j+1) > P1

v2j = -1 (falling)

k3·(v4j-1) + k2·(v0

j ) + k1·(v1j) + k1·(v3

j) + k2·(v4j) + k3·(v0

j+1) < P-1

Again, the constraint equations are tested against each possible transition and the transitions that violate the constraints are eliminated.

0 0 0 0

0 0 0 0


Methodology

Supply Bounce : coupling is bounded by Pbnc

Example:

v0j =VDD or VSS. The total number of switching signals that use v0

j to return current must be considered. Due to symmetry of the bus arrangement, signal pins will always return current through two supply pins. i.e., (v0

j-1 and v0j) or (v4

j and v4j+1). This results in the self inductance

of the return path being divided by 2. Let z = |L di/dt| for any pin. Then, v0

j = VDD

(z/2)·(# of vij pins that are 1) < Pbnc

v4j = VSS

(z/2)·(# of vij pins that are -1) < Pbnc


Methodology

• For each bit in the jth segment bus, constraints are written.

• If the pin is a signal, 3 constraint equations are written; - v0

j = 0, the bit is static and a glitching constraint is written - v0

j = 1, the bit is rising and an edge degradation constraint is written. - v0

j = -1, the bit is falling and an edge degradation constraint is written.

• If the pin is VDD, 1 constraint equation is written to avoid supply bounce.

• If the pin is VSS, 1 constraint equation is written to avoid ground bounce.

• For the segment, 1 constraint equation is written to constrain power.


Methodology

• This results in the total number of constraint equations written is:

(3·n – 4)

• Each equation must be evaluated for each possible transition to verify if the transition meets the constraints. The total number of transitions that are evaluated depends on n and p:

3(n+2p – 6)

• This follows since there are n-2 signal pins in the segment j, and 2p-4 signal pins in neighboring segments.

• The values of n and p are small in practice, hence this is tractable.


Example # of Constraints = (3n – 4) = 111) v0

j = VDD (L/2)· (# of vij pins that are 1) < Pbnc

2) v1j = 1 k1· (v2

j) + k2· (v3j) > P1

3) v1j = -1 k1· (v2

j) + k2· (v3j) < P-1

4) v1j = 0 - P0 < k1· (v2

j) + k2· (v3j) < P0

5) v2j = 1 k1· (v1

j) + k1· (v3j) > P1

6) v2j = -1 k1· (v1

j) + k1· (v3j) < P-1

7) v2j = 0 - P0 < k1· (v1

j) + k1· (v3j) < P0

8) v3j = 1 k2· (v1

j) + k1· (v2j) > P1

9) v3j = -1 k2· (v1

j) + k1· (v2j) < P-1

10) v3j = 0 - P0 < k2· (v1

j) + k1· (v2j) < P0

11) v4j = VSS (L/2)· (# of vi

j pins that are -1) < Pbnc


Example

Transitions Eliminated due to Constraint Violations

Rule(s) Violated

Transition Aggressive Non Aggressive

011 violates 1,4 -

0-1-1 violates 4,11 -

101 violates 1,7 -

110 violates 1,10 -

111 violates 1,2,5,8 violates 11

11-1 violates 1 -

1-11 violates 1 -

1-1-1 violates 11 -

-10-1 violates 7,11 -

-111 violates 1 -

-11-1 violates 11 -

-1-10 violates 10,11 -

-1-11 violates 11 -

-1-1-1 violates 3,6,9,11 violates 1


• Directed graph is created from surviving legal transitions

• Directed Graph is Used to Map Transitions Between any Two Vectors - A transition path (which may include stutters) exists between any two vectors if:

• There exists at least two outgoing edges for each vector vsG (including self-edge) • There exists at least two incoming edges for each vector vdG (including self-edge)

Bus Stuttering CODEC - Algorithm

G


Bus Stuttering CODEC - Construction

• Multiple Stutter States can be used - Between 0 and 2(Wbus-1) stutters can be inserted between any two vectors - Results show that for segments up to 8 bits, more than 3 stutters is rare

• Overhead - Overhead increases as segments sizes increase - Still useful since segments greater than 8 bits are rarely used.

( 1)2

1(2 )

(#_ _ Re _ _ )

2

Wbus

bus

kW

Trans quiring k stutters kOverhead


Bus Stuttering CODEC – Physical Results

• Circuit Implementation - 32 pipeline stages used - Pipeline reset after 32 idle states (similar to SRIO, HT, and PCI Express)

- Protocol inherently handles pipeline overflow


• SPICE Simulations- 3 bit segment (5 pins including VDD and GND)

• - Fixed di/dt- Maximum noise reduced by limiting simultaneously switching signals

• SPICE simulations match analytical predictions with great fidelity


Ground Bounce Glitching Edge Degradation



• TSMC 0.13um Synthesis Results - RTL design, synthesized and mapped - Segment sizes 2 8 implemented - Logic, delay, and area evaluated



• Xilinx FPGA, 0.35um Implementation Results - RTL design implemented - Xilinx, VirtexIIPro, FPGA



• Xilinx FPGA, 0.35um Implementation Results - RTL design, implemented - Logic operation verified

- Noise Reduced from 16% to 4% (Segments with 4 signal pins)


Conclusion

• Packaging Performance is the Largest System Bottleneck

• Stutter Encoding Avoids Worst-Case Noise Patterns

• Performance Improved Even After Considering Encoding Overhead

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March 8, 2006“Bus Stuttering”1 Bus Stuttering : An Encoding Technique To Reduce Inductive Noise...

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