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Marseille 30 January 2013
David Calvo
IFIC (CSIC – Universidad de Valencia)
CLB: Current status and development on CLBv2 in Valencia
TDC: DESIGN
DES
ERIA
LIZE
R
RECOVERYUNIT
F
IFO
Output 48 bits (Resolution: 1ns)
8 bits
KC705
32 bitsTime StampHeader
8 bitsPulse width
LVDS Input Signal
TDC: 31 CHANNELS
LVDS Input Signal
Output (48 bits)
KC705
3
MU
LTIP
LEXE
R
Ch.1
Ch.2
Ch.31SIG
NAL
DIS
TRIB
UTI
ON
Enable Interface
Ch.1
Ch.31
PC
TDC: TEST
ML605 LVDS Input Signal
Output (48 bits)
KC705
4
Well-known pattern
MU
LTIP
LEXE
R
Ch.1
Ch.2
Ch.31SIG
NAL
DIS
TRIB
UTI
ON
Enable Interface
Ch.1
Ch.31
PC
TDC: PATTERNS TO TEST
Jitter = 0.3 ns 5
CHANNEL 1
CHANNEL 2
TDC: PATTERN TO TEST
6
Patterns replicated 250 times
1000 pulses x channelCHANNEL 1
CHANNEL 2
TDC: RESULT
7
Pulse width
ns
coun
ts
CHANNEL 1
ns
coun
ts
CHANNEL 2
TDC: RESULT
8
Time between pulses
ns
coun
ts
CHANNEL 1
ns
coun
ts
CHANNEL 2
I2C1
LM32 DEVELOPMENTS IN VALENCIA
• LM32 SOC with several wishbone slaves (32 bits bus):o BRAMo UARTo TIMERo I2C0 Nanobeacono I2C1 Temperature and Humidity sensor (DIGIPICCO)o GPIO
2nd CPULM32
BRAM I2C0UART
Data
Wishbone shared bus (32 bits) NanoBeacon
GPIODebug LEDs
TIMER
RS-232 HYPERTERMINAL
XilinxSpartan-6
Temp and Humidity Sensor
LM32 DEVELOPMENTS IN VALENCIA
Rx_m
ac2b
uf
I2C
Fifo
31 TDCsTDC0
Management& Control
DataControlWishbone bus
RxPacketBuffer64KB
IP/UDP Packet BufferStream Selector (IPMUX)
Rx_b
uf2d
ata RxPort 1
RxPort 2
RxPort_m
Management& Config.
Tx_p
kt2m
ac
Tx_d
ata2
buf TxPort 1
TxPort 2
TxPort_m
Flags
Rx S
trea
m
Sele
ct
TxPacketBuffer32KB
Flags
Tx S
trea
m
Sele
ct
31 P
MTs
UTC time & Clock (PPS, 125 MHz)
Pause Frame
ADC
Management& Control
Hyd
roph
one
Fifo TDC30
Fifo
NanoBeacon
GPIODebug LEDsI2C
Debug RS232
Temp Compass TiltPoint to Point interconnection
XilinxKintex-7
Start Time Slice UTC &Offset counter since
Tim
e Sl
ice
Star
t
MEMS
2nd CPULM32
M
M
WB Crossbar(1x7)
WB Crossbar(3x2)
SM
SM
M
S
S
MM
M
S SS
UARTS
M
M
S
S
MM
Stat
e M
achi
ne
SPIS
M
SPIFlash
NEXT STEPS IN VALENCIA (I)
Rx_m
ac2b
uf
I2C
Fifo
31 TDCsTDC0
Management& Control
DataControlWishbone bus
RxPacketBuffer64KB
IP/UDP Packet BufferStream Selector (IPMUX)
Rx_b
uf2d
ata RxPort 1
RxPort 2
RxPort_m
Management& Config.
Tx_p
kt2m
ac
Tx_d
ata2
buf TxPort 1
TxPort 2
TxPort_m
Flags
Rx S
trea
m
Sele
ct
TxPacketBuffer32KB
Flags
Tx S
trea
m
Sele
ct
31 P
MTs
UTC time & Clock (PPS, 125 MHz)
Pause Frame
ADC
Management& Control
Hyd
roph
one
Fifo TDC30
Fifo
NanoBeacon
GPIODebug LEDsI2C
Debug RS232
Temp Compass TiltPoint to Point interconnection
XilinxKintex-7
Start Time Slice UTC &Offset counter since
Tim
e Sl
ice
Star
t
MEMS
2nd CPULM32
M
M
WB Crossbar(1x7)
WB Crossbar(3x2)
SM
SM
M
S
S
MM
M
S SS
UARTS
M
M
S
S
MM
Stat
e M
achi
ne
SPIS
M
SPIFlash
NEXT STEPS IN VALENCIA (II)
Rx_m
ac2b
uf
I2C
Fifo
31 TDCsTDC0
Management& Control
DataControlWishbone bus
RxPacketBuffer64KB
IP/UDP Packet BufferStream Selector (IPMUX)
Rx_b
uf2d
ata RxPort 1
RxPort 2
RxPort_m
Management& Config.
Tx_p
kt2m
ac
Tx_d
ata2
buf TxPort 1
TxPort 2
TxPort_m
Flags
Rx S
trea
m
Sele
ct
TxPacketBuffer32KB
Flags
Tx S
trea
m
Sele
ct
31 P
MTs
UTC time & Clock (PPS, 125 MHz)
Pause Frame
ADC
Management& Control
Hyd
roph
one
Fifo TDC30
Fifo
NanoBeacon
GPIODebug LEDsI2C
Debug RS232
Temp Compass TiltPoint to Point interconnection
XilinxKintex-7
Start Time Slice UTC &Offset counter since
Tim
e Sl
ice
Star
t
MEMS
2nd CPULM32
M
M
WB Crossbar(1x7)
WB Crossbar(3x2)
SM
SM
M
S
S
MM
M
S SS
UARTS
M
M
S
S
MM
Stat
e M
achi
ne
SPIS
M
SPIFlash
NEXT STEPS IN VALENCIA (III)
Rx_m
ac2b
uf
I2C
Fifo
31 TDCsTDC0
Management& Control
DataControlWishbone bus
RxPacketBuffer64KB
IP/UDP Packet BufferStream Selector (IPMUX)
Rx_b
uf2d
ata RxPort 1
RxPort 2
RxPort_m
Management& Config.
Tx_p
kt2m
ac
Tx_d
ata2
buf TxPort 1
TxPort 2
TxPort_m
Flags
Rx S
trea
m
Sele
ct
TxPacketBuffer32KB
Flags
Tx S
trea
m
Sele
ct
31 P
MTs
UTC time & Clock (PPS, 125 MHz)
Pause Frame
ADC
Management& Control
Hyd
roph
one
Fifo TDC30
Fifo
NanoBeacon
GPIODebug LEDsI2C
Debug RS232
Temp Compass TiltPoint to Point interconnection
XilinxKintex-7
Start Time Slice UTC &Offset counter since
Tim
e Sl
ice
Star
t
MEMS
2nd CPULM32
M
M
WB Crossbar(1x7)
WB Crossbar(3x2)
SM
SM
M
S
S
MM
M
S SS
UARTS
M
M
S
S
MM
Stat
e M
achi
ne
SPIS
M
SPIFlash
NEXT STEEPS IN VALENCIA (IV)
Implement reconfigurability:
A.- To use the multiboot capabilities of the KINTEX
B.- To be able to write on the SPI FLASH with the LM32
2nd CPULM32
SPI
Data
Wishbone shared bus (32 bits)
Multiboot image – upgraded image(read /write)
Golden Image (read only)
XilinxKintex KC705
SPI QFLASH MEMORY
THANKS FOR YOUR ATTENTION!
LM32 developments in Valencia
Rx_m
ac2b
uf
I2C
Fifo
31 TDCsTDC0
Management& Control
DataControlWishbone bus
RxPacketBuffer64KB
IP/UDP Packet BufferStream Selector (IPMUX)
Rx_b
uf2d
ata RxPort 1
RxPort 2
RxPort_m
Management& Config.
Tx_p
kt2m
ac
Tx_d
ata2
buf TxPort 1
TxPort 2
TxPort_m
Flags
Rx S
trea
m
Sele
ct
TxPacketBuffer32KB
Flags
Tx S
trea
m
Sele
ct
31 P
MTs
UTC time & Clock (PPS, 125 MHz)
Pause Frame
ADC
Management& Control
Hyd
roph
one
Fifo TDC30
Fifo
NanoBeacon
GPIODebug LEDsI2C
Debug RS232
Temp Compass TiltPoint to Point interconnection
XilinxKintex-7
Start Time Slice UTC &Offset counter since
Tim
e Sl
ice
Star
t
MEMS
2nd CPULM32
M
M
WB Crossbar(1x7)
WB Crossbar(3x2)
SM
SM
M
S
S
MM
M
S SS
UARTS
M
M
S
S
MM
Stat
e M
achi
ne
SPIS
M
SPIFlash