Mask Layout Challenges for Silicon Photonics Session IV: Design Automa=on and Methodologies
M A R C E L VA N D E R V L I E T DESIGN, AUTOMATION & TEST IN EUROPEAN CONFERENCE OPTICAL/PHOTONIC INTERCONNECTS FOR COMPUTING SYSTEMS MARCH 31ST 2017
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• PhoeniXSo@ware
• DiscreFzaFon
• DesignIntent
• DesignRuleChecks
• PDA–EDAIntegraFon
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Outline
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PhoeniX SoSware
new
Weenabletheeasyandcost-effec1verealiza1onofintegrated
photonicschipsandsystems
Partnershipswithfoundries,
so@warevendors,designhouses,universiFes,…
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EDA versus PDA
ManhaVanversus“Erice”paVerns
ManhaVanversuscurvilinearpaVerns
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Non-ManhaWan / curvilinear design
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Curve Discre=za=on
Fromideal(analyFcal)curve ToadiscreFzedpolygon MappedontoGDSgrid
Needfortoolstotranslateidealcurves(DesignIntent)intodiscreFzedpolygons,controllingphaserelaFons
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• Losses• Obtaining smooth curves and side-walls
• Mask orienta=on of waveguides (due to wri=ng direc=on of mask)
• BackReflecFon• Smooth curves and side-walls
• Limits on angle changes (radius)
• PhaseChanges• Width (and height) control of waveguides (1 nm -> 125 GHz) • Changes in op=cal path-length
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Mask layout impacts:
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Impact of op=cal path-length
Example: Arrayed Waveguide Gra=ng
Itisinfacta(de)mulFplexerforlight.Differentcolors(datastreams)arefilteredintodifferentwaveguides.
ThegeometrydeterminestheopFcalperformance,andcanbecalculatedthroughsimulaFonsfromspecificaFonslikebandwidth,numberofoutputchannels,channelspacing,etc. Phase errors resul=ng from:
(1)errorsduetomismatchesintheopFcalpathlengthsinthebranchesinthearray(2)stochasFcalerrorsfromfabricaFonvariaFons
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Generic (EDA) scrip=ng languages
Exampleofthedescrip1onofasine-bendtakenfromaCadenceVirtuoso(SKILL)p-cellasusedinasiliconphotonicsPDKSameappliestoMentorGraphicsAMPLEorgenericlanguageslikeMatlab,Python,…
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• FabricaFon->cross-secFon->performance
Design for Manufacturing
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• FabricaFonàcross-secFonàperformanceDesigner:
Process:
Ideal/theory
Notguided
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From Design Intent to GDSII
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• FabricaFonàcross-secFonàperformanceDesigner:
Process:
Ideal/theory
Notguided
Guided
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OptoDesigner:maskwideningtocompensateunderetch
From Design Intent to GDSII
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Real life example for Design Intent
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Fromdesignintenttofinalmasklayout:• CalculaFngtherequiredshapes,giventhe
designintentandthefabricaFoninformaFon• Turningtheseintopolygons,givena
maximumallowedpatherror• Placingthepolygonsintotherequiredmask
layers,includingsizing,inversion,booleanoperaFons,etc.
• Checkingdesignrules• ExporFngmask(GDS2)files
AWGexample:fromintendedwaveguideor“logical”designintoactualmaskor“GDS”designtofabricatewiththecorrectwaveguidedimensions(crosssec1on)
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Using Design Intent in the UCSB PDK
automated
DesignIntent On-specsGDSforfoundry
Op=mizing polygons snapped to the grid to avoid transla=on and phase errors is very important in photonics.
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Heterogeneous SOI & III-V Integra=on – PDK Available
MinhA.Tranetal.,"Integratedop1caldriverforinterferometricop1calgyroscopes,"Opt.Express25,3826-3840(2017)
Twophasematcheddelaylines(SOI)measurerotaFonangleofgyroscope
Widelytunablelaser(III-V)enableslinemeasurementofphasechange
Op1calgyroscope
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UCSB Heterogeneous SOI & III-V Integra=on – PDK available
8×8×40Gbpsfullyintegratedsiliconphotonicnetworkonchip,Zhangetal.,2334-2536/16/070785-02Journal,2016OpMcalSocietyofAmerica
Morethan400PhotonicBuilding
BlocksinonePIC!J
AlGaInAsEAMAlGaInAsDFBInGaAsPINPD
1×8(De)Mux
BroadbandMZIswitcharray
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DRC Design Rule Checks
drcMinWidth drcMinSpace
drcMinNotch
drcAngleCheck on the Echelle gra8ngs
drcSingularPoint
drcMinWidth drcMinSpace
Fabrica=on errors can lead to high costs and unwanted delays, however, they can be prevented by using verifica=on and Design Rule Checks (DRC).
Both for academic research as well as commercial product development, it is a key step in the whole design flow from ini=al concept to manufacturable mask layout.
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DRC example Notch Check Notchtoosmall
Notchlargeenough
Notch
Notch
Notch
Rounding of a square feature (the end of the waveguide) as a result of the distance to surrounding features (or non etched surfaces) Topview
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Challenges for Calibre
Silicon photonics components are usually formed by curvilinear geometries (non-ManhaGan shapes). Tradi8onal IC DRC tools are incompa8ble with these geometries, resul8ng in false errors reported during the physical verifica8on phase.
MOHANED ELSHAWY, MENTOR GRAPHICS MGC 06-16 TECH14370
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Condi=onal and mul=dimensional DRC
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• Challengesweseecustomersandfoundriesrunninginto:• Increasing complexity of PIC designs
• Significant waveguide rou=ng challenges • Limited circuit simula=on capabili=es with validated models
• Design verifica=on: design rule checking and layout vs schema=c • Co-design of electronics and photonics
Tosupporttheindustryinthetransi1onfromresearchtocommercialproductdevelopment,weneedintegrateddesignflowssuppor1ngadesignformanufacturabilitydesignstrategy,makinguseofstrengthsofbothPDAaswellasEDAtools
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Situa=on today
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EDA – PDA integra=on Example of 3-party collabora=on
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• CollaboraFonannouncedinDecember2015
• SchemaFcDriven
Layoutflow,centeredaroundaPDKapproach
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AllphotonicspartsareprovidedbyPhoeniXSo@waretechnology
Overcomingthegrid-based“ManhaVan”designlimitaFonsintradiFonalICdesigntools
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PhoeniX SoSware’s Virtuoso integra=on with PDA-Link access point into all PhoeniX SoSware’s PIC design rou=nes
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All angle in Virtuoso
• FullyParameterized• Path Length Difference
• Modulator Length • …
• AllAngle
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• DiscreFzaFonimpactsdeviceperformance• Good algorithms required
• Technologydependenciescancreatecomplextasks• Need good PDKs • Hybrid PDK design environment
• DesignrulechecksofEDAarenotsufficient
• NeedintegraFonbetweenEDAandPDAtools
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Summary
