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Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

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Massively LDPC Decoding on Multicore Architectures Present by : fakewen
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Page 1: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

Massively LDPC Decoding onMulticore Architectures

Present by : fakewen

Page 2: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

Authors

• Gabriel Falcao• Leonel Sousa• Vitor Silva

Page 3: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

Outline

• Introduction• BELIEF PROPAGATION• DATA STRUCTURES AND PARALLEL

COMPUTING MODELS• PARALLELIZING THE KERNELS EXECUTION• EXPERIMENTAL RESULTS

Page 4: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

Outline

• Introduction• BELIEF PROPAGATION• DATA STRUCTURES AND PARALLEL

COMPUTING MODELS• PARALLELIZING THE KERNELS EXECUTION• EXPERIMENTAL RESULTS

Page 5: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

Introduction

• LDPC decoding on multicore architectures• LDPC decoders were developed on recent

multicores, such as off-the-shelf general-purpose x86 processors, Graphics Processing Units (GPUs), and the CELL Broadband Engine (CELL/B.E.).

Page 6: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

Outline

• Introduction• BELIEF PROPAGATION• DATA STRUCTURES AND PARALLEL

COMPUTING MODELS• PARALLELIZING THE KERNELS EXECUTION• EXPERIMENTAL RESULTS

Page 7: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

BELIEF PROPAGATION

• Belief propagation, also known as the SPA, is an iterative algorithm for the computation of joint probabilities

Page 8: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

LDPC Decoding

• exploit probabilistic relationships between nodes imposed by parity-check conditions that allow inferring the most likely transmitted codeword.

Page 9: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

LDPC Decoding(cont.)

White Gaussian noise

Page 10: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

LDPC Decoding(cont.)

Page 11: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.
Page 12: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.
Page 13: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

Outline

• Introduction• BELIEF PROPAGATION• DATA STRUCTURES AND PARALLEL

COMPUTING MODELS• PARALLELIZING THE KERNELS EXECUTION• EXPERIMENTAL RESULTS

Page 14: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

DATA STRUCTURES AND PARALLEL COMPUTING MODELS

• compact data structures to represent the H matrix

Page 15: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

Data Structures

• separately code the information about H in two independent data streams, and

Page 16: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

remind

• rmn :是 CNm->BNn

• qnm :是 BNn->CNm

Page 17: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

Parallel Computational Models

• Parallel Features of the General-Purpose Multicores

• Parallel Features of the GPU• Parallel Features of the CELL/B.E.

Page 18: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

Parallel Features of the General-Purpose Multicores

• #pragma omp parallel for

Page 19: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

Parallel Features of the GPU

Page 20: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

Throughput

Page 21: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

Parallel Features of the CELL/B.E.

Page 22: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

Throughput

Page 23: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

Outline

• Introduction• BELIEF PROPAGATION• DATA STRUCTURES AND PARALLEL

COMPUTING MODELS• PARALLELIZING THE KERNELS EXECUTION• EXPERIMENTAL RESULTS

Page 24: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

PARALLELIZING THE KERNELS EXECUTION

• The Multicores Using OpenMP• The GPU Using CUDA• The CELL/B.E.

Page 25: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

The Multicores Using OpenMP

Page 26: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

The GPU Using CUDA

• Programming the Grid Using a Thread per Node Approach

Page 27: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

The GPU Using CUDA(cont.)

• Coalesced Memory Accesses

Page 28: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.
Page 29: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

The CELL/B.E.

• Small Single-SPE Model(A B C)• Large Single-SPE Model

Page 30: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

Why Single-SPE Model

• In the single-SPE model, the number of communications between PPE and SPEs is minimum and the PPE is relieved from the costly task of reorganizing data (sorting procedure in Algorithm 4) between data transfers to the SPE.

Page 31: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

Outline

• Introduction• BELIEF PROPAGATION• DATA STRUCTURES AND PARALLEL

COMPUTING MODELS• PARALLELIZING THE KERNELS EXECUTION• EXPERIMENTAL RESULTS

Page 32: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.
Page 33: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

EXPERIMENTAL RESULTS

• LDPC Decoding on the General-Purpose x86 Multicores Using OpenMP

• LDPC Decoding on the CELL/B.E.– Small Single-SPE Model– Large Single-SPE Model

• LDPC Decoding on the GPU Using CUDA

Page 34: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

LDPC Decoding on the General-Purpose x86 Multicores Using OpenMP

Page 35: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

LDPC Decoding on the CELL/B.E.

Page 36: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

LDPC Decoding on the CELL/B.E.(cont.)

Page 37: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

LDPC Decoding on the CELL/B.E.(cont.)

Page 38: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

LDPC Decoding on the GPU Using CUDA

Page 39: Massively LDPC Decoding on Multicore Architectures Present by : fakewen.

The end

Thank you~


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