May 17, 1999 2

USB 2.0 Transceiver Macrocell

USB 2.0 Transceiver Macrocell

Steve McGowan - Steve McGowan - Intel CorporationIntel Corporation

Clarence Lewis - Texas InstrumentsClarence Lewis - Texas InstrumentsSteve McGowan - Steve McGowan - Intel CorporationIntel Corporation

Clarence Lewis - Texas InstrumentsClarence Lewis - Texas Instruments

May 17, 1999 3

Macrocell RequirementsMacrocell Requirements

Simplify the design process for peripheral vendorsSimplify the design process for peripheral vendors– Consolidate high speed logic in to a discrete moduleConsolidate high speed logic in to a discrete module– Provide a “standard” USB 2.0 hardware interfaceProvide a “standard” USB 2.0 hardware interface

Minimize time to marketMinimize time to market– Decouple ASIC and Peripheral development cyclesDecouple ASIC and Peripheral development cycles

Enable standard library elements from ASIC vendorsEnable standard library elements from ASIC vendors– Peripheral vendors can focus on productPeripheral vendors can focus on product

specific developmentspecific development Reuse of existing USB 1.1 SIE logicReuse of existing USB 1.1 SIE logic

OverviewOverview

Enable High Volume DevicesEnable High Volume Devices

May 17, 1999 4

OverviewOverview

USB Device DevelopmentUSB Device Development

AssumptionsAssumptions– PrototypingPrototyping

FPGAFPGA UTMI Compliant Discrete TransceiverUTMI Compliant Discrete Transceiver

– ProductionProduction Low VolumeLow Volume

Gate ArrayGate Array UTMI Compliant Discrete TransceiverUTMI Compliant Discrete Transceiver

High VolumeHigh Volume ASICASIC UTMI Compliant Transceiver MacrocellUTMI Compliant Transceiver Macrocell

May 17, 1999 5

Device AnatomyDevice Anatomy

USB Transceiver Macrocell (UTM)USB Transceiver Macrocell (UTM) Serial Interface EngineSerial Interface Engine Device Specific LogicDevice Specific Logic

OverviewOverview

ASICASICASICASIC

Serial Interface EngineSerial Interface EngineSerial Interface EngineSerial Interface Engine

DeviceDeviceSpecificSpecific

LogicLogic

DeviceDeviceSpecificSpecific

LogicLogic

Endpoint LogicEndpoint Logic

Endpoint LogicEndpoint Logic

……SIE

Control Logic

SIEControl Logic

USB 2.0USB 2.0Endpoint LogicEndpoint Logic

Device Hardware

Device Hardware

USB 2.0 USB 2.0 TransceiverTransceiver

USB 2.0 USB 2.0 TransceiverTransceiver

UTM Interface

UTM Interface

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Serial Interface EngineSerial Interface Engine

SIE Control LogicSIE Control Logic– USB Transaction State MachineUSB Transaction State Machine– PID, Address, and EP match logicPID, Address, and EP match logic– Checks receive completion statusChecks receive completion status– Chains packets into transactionsChains packets into transactions

Endpoint LogicEndpoint Logic– FIFOs and FIFO controlFIFOs and FIFO control

Serial Interface EngineSerial Interface EngineSerial Interface EngineSerial Interface Engine

Endpoint Logic

Endpoint Logic

……

SIEControl Logic

Endpoint Logic

ControlControl

Data InData In

Data OutData Out

To Device To Device Specific Specific

LogicLogic

To TransceiverTo Transceiver

OverviewOverview

May 17, 1999 7

Transceiver MacrocellTransceiver Macrocell

Converts USB signaling into a simple interfaceConverts USB signaling into a simple interface– USB 2.0 compliant serial interfaceUSB 2.0 compliant serial interface– Multiple Parallel Data Interface OptionsMultiple Parallel Data Interface Options– Multiple Speed OptionsMultiple Speed Options

HS/FS, FS Only, LS OnlyHS/FS, FS Only, LS Only

USB 2.0USB 2.0USB 2.0 USB 2.0 TransceiverTransceiver

USB 2.0 USB 2.0 TransceiverTransceiver

ControlControl

Data InData In

Data OutData Out

To SIETo SIE To BusTo Bus

OverviewOverview

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Macrocell FunctionsMacrocell Functions

HS and FS signaling and terminationHS and FS signaling and termination HS receiver squelchHS receiver squelch USB clock recoveryUSB clock recovery Bit stuffingBit stuffing NRZI encodingNRZI encoding Serializing and deserializingSerializing and deserializing Data-rate toleranceData-rate tolerance Data bufferingData buffering Single interface for HS/FS, FS or LS operationSingle interface for HS/FS, FS or LS operation

OverviewOverview

May 17, 1999 9

Block DiagramBlock Diagram

ControlControlControl

D-

D+

DLLDLLDLLDLL

FSInterface

HSInterface

Shared LogicShared Logic

ParallelParallelInterfaceInterfaceParallelParallel

InterfaceInterfaceDLLDLLDLLDLL

muxmux

BitBitUnstufferUnstuffer

BitBitUnstufferUnstuffer DeseralizerDeseralizerDeseralizerDeseralizer RX HoldingRX Holding

RegRegRX HoldingRX Holding

RegReg

BitBitStufferStuffer

BitBitStufferStuffer SeralizerSeralizerSeralizerSeralizer TX HoldingTX Holding

RegRegTX HoldingTX Holding

RegReg

ToSIE

Data

ToUSB

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8-Bit Uni-Directional8-Bit Uni-DirectionalInterface OptionsInterface Options

DataIn(0-7)DataIn(0-7)

TXValidTXValid

ResetResetSusepsndMSusepsndM

XcvrSelectXcvrSelectTermSelectTermSelect

OpMode(0-1)OpMode(0-1)

DataOut(0-7)DataOut(0-7)

TXReadyTXReady

RXActiveRXActiveRXValidRXValid

CLKCLKRXErrorRXError

DPDPDMDM

LineState(0-1)LineState(0-1)

8-Bit Interface8-Bit Interface

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16-Bit Uni-Directional16-Bit Uni-DirectionalInterface OptionsInterface Options

DataIn(8-15)DataIn(0-7)

TXValidTXValidH

DataBus16_8

ResetSusepsndM

XcvrSelectTermSelect

OpMode(0-1)

DataOut(8-15)DataOut(8-15)DataOut(0-7)DataOut(0-7)

TXReadyTXReady

RXActiveRXActive

RXValidRXValidRXValidHRXValidH

CLKCLKRXErrorRXError

DPDPDMDM

LineState(0-1)LineState(0-1)

16-Bit Interface16-Bit Interface

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16-Bit Bi-Directional16-Bit Bi-DirectionalInterface OptionsInterface Options

DataBus16_8DataBus16_8

DataOut(8-15)DataOut(8-15)DataOut(0-7)DataOut(0-7)

TXValidTXValid

RXValidHRXValidH

Data(8-15)Data(8-15)Data(0-7)Data(0-7)

ValidHValidH

DataIn(8-15)DataIn(8-15)DataIn(0-7)DataIn(0-7)

TXReadyTXReady

TXValidHTXValidH

16-Bit Bi-Directional Interface16-Bit Bi-Directional Interface

May 17, 1999 13

How Does the Macrocell Do It?How Does the Macrocell Do It?

Macrocell FunctionsMacrocell Functions

May 17, 1999 14

Macrocell FunctionsMacrocell Functions

InterfaceInterface

Packet Engine Packet Engine – Automatically handles SYNC Pattern and EOPAutomatically handles SYNC Pattern and EOP

Flow ControlFlow Control– Compensates for Bit Stuffing and Data Rate ToleranceCompensates for Bit Stuffing and Data Rate Tolerance

Primitives for Full Protocol SupportPrimitives for Full Protocol Support Speed SwitchingSpeed Switching Clock GenerationClock Generation Power ControlPower Control

May 17, 1999 15

ReceiveReceive

RXActive - Frames PacketRXActive - Frames Packet RXValid - Provides Flow ControlRXValid - Provides Flow Control

Macrocell FunctionsMacrocell Functions

CLKCLK CLKCLK

RXActiveRXActiveRXActiveRXActive

RXValidRXValidRXValidRXValid

DataOut(7:0)DataOut(7:0)DataOut(7:0)DataOut(7:0) PIDPIDPIDPID DataDataDataData DataDataDataData

DP/DMDP/DMDP/DMDP/DM SYNCSYNCSYNCSYNC PIDPIDPIDPID DataDataDataData DataDataDataData EOPEOPEOPEOP

May 17, 1999 16

TransmitTransmit

TXValid - Frames PacketTXValid - Frames Packet TXReady - Provides Flow ControlTXReady - Provides Flow Control

TXValidTXValid

DP/DMDP/DM PIDPID DataDataSYNCSYNC DataData DataData DataData CRCCRC CRCCRC EOPEOP

TXReadyTXReady

CLKCLK

DataIn(7:0)DataIn(7:0) PIDPID DataData DataData DataData CRCCRC CRCCRCDataData

Macrocell FunctionsMacrocell Functions

May 17, 1999 17

Macrocell FunctionsMacrocell Functions

SignalsSignals

Flow ControlFlow Control– Receive with data underruns due to removing stuffed Receive with data underruns due to removing stuffed

bits from the data streambits from the data stream

CLKCLK

DataOut(7:0)DataOut(7:0)

RXActiveRXActive

DataData DataDataDataData CRCCRC CRCCRC

RXValidRXValid

Invalid DataInvalid Data

DataData DataDataDataData Inv Inv

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Protocol Primitive SupportProtocol Primitive Support

Resume AssertionResume Assertion Resume DetectionResume Detection Suspend DetectionSuspend Detection Reset DetectionReset Detection HS Detection HandshakeHS Detection Handshake

Macrocell FunctionsMacrocell Functions

May 17, 1999 19

Macrocell FunctionsMacrocell Functions

Operational ModesOperational Modes

Normal OperationNormal Operation– Standard encoding and decoding of serial streamStandard encoding and decoding of serial stream

Non-DrivingNon-Driving– Tri-states all transmitters and termination on the busTri-states all transmitters and termination on the bus

Unencoded Data (needed for test modes)Unencoded Data (needed for test modes)– Disable Bit Stuffing and NRZI encodingDisable Bit Stuffing and NRZI encoding– Allows transmission and reception of unencoded dataAllows transmission and reception of unencoded data

May 17, 1999 20

Resume AssertionResume Assertion

Place Macrocell in Place Macrocell in “Disable Bit Stuffing and NRZI “Disable Bit Stuffing and NRZI encoding”encoding” mode mode

Transmit ‘0’ data for K’s (‘1’ data for J’s)Transmit ‘0’ data for K’s (‘1’ data for J’s) Wait for SE0Wait for SE0

SuspendMSuspendM

XcvrSelect & TermSelect

XcvrSelect & TermSelect

'K' State'K' StateFS Idle ('J')FS Idle ('J')DP/DMDP/DM SE0SE0

FS ModeFS Mode HS ModeHS Mode

TXValidTXValid

OpModeOpMode Mode 2Mode 2Mode 0Mode 0 Mode 0Mode 0

Macrocell FunctionsMacrocell Functions

May 17, 1999 21

Resume DetectionResume Detection

Listen to Listen to LineStateLineState Use J to K transition to disable Use J to K transition to disable SuspendMSuspendM Enter HS mode after K to SE0 transitionEnter HS mode after K to SE0 transition

– Assert Assert XcvrSelect XcvrSelect and and TermSelectTermSelect

FS ModeFS Mode HS ModeHS Mode

SuspendMSuspendM

XcvrSelect XcvrSelect

'K' State'K' State'J’ State (FS Idle)'J’ State (FS Idle)LineStateLineState SE0SE0

OpModeOpMode Mode 0Mode 0

XcvrSelectXcvrSelect

Macrocell FunctionsMacrocell Functions

May 17, 1999 22

Suspend DetectionSuspend Detection

Watch Watch LineStateLineState for 3ms of inactivity (SE0) for 3ms of inactivity (SE0) Switch to FS modeSwitch to FS mode

– Assert Assert XcvrSelectXcvrSelect and and TermSelectTermSelect If J asserted, then enter Suspend StateIf J asserted, then enter Suspend State

– Assert Assert SuspendMSuspendM

Term SelectTerm Select

Last ActivityLast Activity

'J' State'J' StateSE0SE0

SuspendMSuspendM

LineStateLineState

Xcvr SelectXcvr Select

Transceiver suspendedTransceiver suspended

Macrocell FunctionsMacrocell Functions

May 17, 1999 23

Reset DetectionReset Detection

SE0 is the Idle state in HS modeSE0 is the Idle state in HS mode After 3ms of inactivity (SE0) switch to FS modeAfter 3ms of inactivity (SE0) switch to FS mode

– Assert Assert XcvrSelectXcvrSelect and and TermSelectTermSelect If SE0 asserted then enter ResetIf SE0 asserted then enter Reset

– Initiate HS Handshake DetectionInitiate HS Handshake Detection

Term SelectTerm Select

Last ActivityLast Activity ’SE0' State’SE0' StateSE0SE0DP/DMDP/DM

Xcvr SelectXcvr Select

HS Handshake DetectionProcess

HS Handshake DetectionProcess

Macrocell FunctionsMacrocell Functions

May 17, 1999 24

HS Detection HandshakeHS Detection Handshake

Turn on HS Transceivers with FS TerminationsTurn on HS Transceivers with FS Terminations Drive a “Chirp K”Drive a “Chirp K” Detect Chirp K/J Sequence from the HubDetect Chirp K/J Sequence from the Hub Assert HS TerminationsAssert HS Terminations

Hub Chirp SequenceHub Chirp SequenceDeviceChirp

DeviceChirp

TXValidTXValid

TermSelectTermSelect

XcvrSelectXcvrSelect

HS ModeHS Mode

Chirp KChirp KDP/DMDP/DM

KK JJ KK JJ KK JJKK JJ SE0SE0 SOFSOF

HS Detection Handshake ProcessHS Detection Handshake Process

Macrocell FunctionsMacrocell Functions

May 17, 1999 25

Clock GenerationClock Generation

Macrocell supplies clocks to the SIEMacrocell supplies clocks to the SIE Frequency depends on implementationFrequency depends on implementation

– HS/FSHS/FS 60 MHz 8-bit uni-directional60 MHz 8-bit uni-directional 30 MHz 16-bit uni- or bi-directional30 MHz 16-bit uni- or bi-directional

– FS OnlyFS Only 48 MHz 8-bit uni-directional48 MHz 8-bit uni-directional

– LS OnlyLS Only 6 MHz 8-bit uni-directional6 MHz 8-bit uni-directional

Macrocell FunctionsMacrocell Functions

May 17, 1999 26

Power ControlPower Control

SuspendM signalSuspendM signal– Shuts down clocksShuts down clocks– Maintains terminationsMaintains terminations

Vendor determined Drive Current ControlVendor determined Drive Current Control– Enabled during transmitsEnabled during transmits– Enabled by receivesEnabled by receives– Always onAlways on

DPDP

DMDM

HS_Current_Source_EnableHS_Current_Source_Enable

HS_Drive_EnableHS_Drive_Enable

HS_Data_Driver_InputHS_Data_Driver_Input

High-speed Current DriverHigh-speed Current Driver

Macrocell FunctionsMacrocell Functions

May 17, 1999 27

Next StepsNext Steps

Get the USB 2.0 Transceiver Macrocell Interface Get the USB 2.0 Transceiver Macrocell Interface (UTMI) Specification(UTMI) Specification– http://developer.intel.com/technology/usb/http://developer.intel.com/technology/usb/– 1.0 Release Available1.0 Release Available– No RoyaltyNo Royalty

Develop to the UTMI SpecificationDevelop to the UTMI Specification Get your ASIC vendors to provide a UTMI Get your ASIC vendors to provide a UTMI

Compliant MacrocellsCompliant Macrocells

steve.mcgowan@intel.comsteve.mcgowan@intel.com