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May 8, 2001 2
High Speed Electrical Testing
High Speed Electrical Testing
Jim ChoateJim Choate
Intel CorporationIntel Corporation
May 8, 2001 3
AgendaAgenda
Electrical Testing GoalsElectrical Testing Goals Test ModesTest Modes Electrical Testing ProceduresElectrical Testing Procedures Problems to AvoidProblems to Avoid SummarySummary
May 8, 2001 4
Goals of the ElectricalCompliance ProgramGoals of the ElectricalCompliance Program
High Quality USB ProductsHigh Quality USB Products Stable, Repeatable, Well Documented TestsStable, Repeatable, Well Documented Tests
– Documented Equipment SetupsDocumented Equipment Setups– Documented Test ProceduresDocumented Test Procedures– Documented Test Assertions and DescriptionsDocumented Test Assertions and Descriptions
Leverage USB FS/LS Electrical TestsLeverage USB FS/LS Electrical Tests– FS and LS Electrical Testing (LS for downstream ports)FS and LS Electrical Testing (LS for downstream ports)– InrushInrush– Drop and DroopDrop and Droop
May 8, 2001 5
New Testing AreasNew Testing Areas
ElectricalsElectricals– High Speed Signal QualityHigh Speed Signal Quality– Time Domain Reflectometry Time Domain Reflectometry
(TDR)(TDR)– Receiver Sensitivity and Receiver Sensitivity and
SquelchSquelch– J and K Voltage LevelsJ and K Voltage Levels– ChIRPChIRP
HS Electrical Test Spec On USB-IF Members SiteHS Electrical Test Spec On USB-IF Members Site
– Disconnect thresholdsDisconnect thresholds– Packet ParametersPacket Parameters– Suspend/ResumeSuspend/Resume– High Speed Hub ParametersHigh Speed Hub Parameters
Sync truncationSync truncation EOP dribbleEOP dribble etcetc
USB High Speed Electrical Testing Starts at a High LevelUSB High Speed Electrical Testing Starts at a High Level
May 8, 2001 6
USB HS ElectricalTest ModesUSB HS ElectricalTest Modes
High-speed Capable Devices/Hubs Must Support High-speed Capable Devices/Hubs Must Support Test Modes Test Modes
May 8, 2001 7
General HS ElectricalTest ProcedureGeneral HS ElectricalTest Procedure
Connect Device Under Test To Test Port on FixtureConnect Device Under Test To Test Port on Fixture Configure DUT With Test Mode SWConfigure DUT With Test Mode SW Isolate DUT from Host with High Speed RelayIsolate DUT from Host with High Speed Relay Make Appropriate Electrical MeasurementsMake Appropriate Electrical Measurements
May 8, 2001 8USB HS Test FixtureUSB HS Test Fixture
HS RelayHS RelayHS RelayHS RelayTest PortTest Port
InitializationInitializationPortPort
Diff ProbeDiff ProbeDataDataGeneratorGenerator
90 Ohms90 Ohms
PowerPowerSelectionSelection
CktCkt
PowerPowerSelectionSelection
CktCkt
Vbus1Vbus1 Vbus2Vbus2VccVcc
GndGnd
New Test Fixture(s)New Test Fixture(s)
Signal QualitySignal Quality TDRTDR Receiver SensitivityReceiver Sensitivity ChIRPChIRP J and K LevelsJ and K Levels Disconnect thresholdDisconnect threshold Packet parametersPacket parameters Suspend & ResumeSuspend & Resume Test ModesTest Modes
May 8, 2001 9
High Speed Device SignalHigh Speed Device SignalQuality Test FixtureQuality Test Fixture
Test PortTest Port Init PortInit Port
To Host ControllerTo Host
ControllerTo Device Under TestTo Device Under Test
Isolation relay powerIsolation relay power
Test SwitchTest SwitchDiff Probe Test PointDiff Probe Test Point
New Test Fixture(s)New Test Fixture(s)
May 8, 2001 10
9090
HS Signal QualityTest ProcedureHS Signal QualityTest Procedure
Put Device in Test Mode Put Device in Test Mode Test_PacketTest_Packet– Flip Test Fixture Relays Flip Test Fixture Relays
To Route Output toTo Route Output to90 Ohm Termination90 Ohm Termination
– Capture WaveformCapture Waveformon oscilloscopeon oscilloscope
– Analyze dataAnalyze data Data analysis is Data analysis is
performed by generating performed by generating an eye patternan eye pattern
Test Mode SW
OscilloscopeOscilloscope
USB HS Test FixtureUSB HS Test Fixture
HS RelayHS RelayHS RelayHS Relay
Differential ProbeDifferential Probe
DeviceDeviceUnderUnder TestTest
May 8, 2001 11
Eye Pattern GenerationEye Pattern Generation
Time vs. voltage test packet data is transferred Time vs. voltage test packet data is transferred from scope to PC through GPIBfrom scope to PC through GPIB
May 8, 2001 12
Eye Pattern GenerationEye Pattern Generation
Signal analysis scripts determine data rate from Signal analysis scripts determine data rate from zero volt crossovers zero volt crossovers – Crossovers indicated at zero crossings belowCrossovers indicated at zero crossings below
Mean bit time calculatedMean bit time calculated Reference frame created Reference frame created
from meanfrom mean
May 8, 2001 13
Eye Pattern GenerationEye Pattern Generation
Reference frame position is optimized by Reference frame position is optimized by minimizing least squares error betweenminimizing least squares error betweenreference frame and actual crossoversreference frame and actual crossovers
Reference points between Reference points between runs ignoredruns ignored
Optimized reference pointOptimized reference point
Actual crossoverActual crossover
May 8, 2001 14
hs plot
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
time
volt
s
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
1 bit time
Eye Pattern GenerationEye Pattern Generation
Data is parsed into Data is parsed into bit time internals bit time internals using optimized using optimized reference framereference frame
Eye pattern created Eye pattern created from bit time from bit time intervalsintervals
May 8, 2001 15
Passing Eye PatternPassing Eye Pattern
Example of passing High Speed Eye - Host Example of passing High Speed Eye - Host Controller at TP2Controller at TP2
May 8, 2001 16
Failing Eye PatternsFailing Eye Patterns
Min/Max voltage level failureMin/Max voltage level failure Caused by out of spec HS Caused by out of spec HS
terminationtermination
Jitter failureJitter failure Caused by noise from Caused by noise from
power supplypower supply
May 8, 2001 17
HS Device Receiver Sensitivityand Squelch Test ProcedureHS Device Receiver Sensitivityand Squelch Test Procedure
DUT is Placed In DUT is Placed In Test_SEO_NAK Test Mode Test_SEO_NAK Test Mode using Test Mode SWusing Test Mode SW
The test fixture replaces The test fixture replaces the host by switching the the host by switching the connection to the Data connection to the Data GeneratorGenerator
Data GeneratorData GeneratorGenerates IN PacketsGenerates IN Packets
Device Must RespondDevice Must Respondfor In Spec Packetsfor In Spec Packets
Device Must Not Respond Device Must Not Respond to Out of Spec Data to Out of Spec Data Generator OutputGenerator Output
Data GeneratorData GeneratorTest Mode
SW
USB 2.0 Test FixtureUSB 2.0 Test Fixture
HS RelayHS RelayHS RelayHS Relay
Device underDevice under testtest
SMASMA
May 8, 2001 18
Device response Device response to nominal to nominal packetspackets
Device response Device response to minimum to minimum packetspackets
Device must not Device must not respond to respond to packets below packets below squelch thresholdsquelch threshold
HS Device Receiver Sensitivity and Squelch Test ResultsHS Device Receiver Sensitivity and Squelch Test Results
DG packetDG packetDG packetDG packet Device ResponseDevice Response No Device ResponseNo Device ResponseNo Device ResponseNo Device Response
Minimum Receiver sensitivity thresholdMinimum Receiver sensitivity threshold
May 8, 2001 19
TDR Test ProcedureTDR Test Procedure
Device Under Test Device Under Test Placed In Placed In Test_SEO_NAK ModeTest_SEO_NAK Mode
Relay Switches Idle Data Relay Switches Idle Data Lines to TDR Lines to TDR
TDR BroadcastsTDR BroadcastsTest SignalTest Signal
TDR MeasuresTDR MeasuresSignal Reflections To Signal Reflections To Determine Termination Determine Termination And PCB ImpedanceAnd PCB Impedance
TDRTDRTest Mode
SW
USB 2.0 Test FixtureUSB 2.0 Test Fixture
HS RelayHS RelayHS RelayHS Relay
Device UnderDevice Under TestTest
SMASMA
May 8, 2001 20
Open voltage step indicates Open voltage step indicates connector connector
reference locationreference location
TDR Test ProcedureTDR Test Procedure
Determining connector reference locationDetermining connector reference location– TDR connected to test fixtureTDR connected to test fixture– Test fixture disconnected from device under testTest fixture disconnected from device under test– Voltage step occurs at connector end (open step)Voltage step occurs at connector end (open step)
May 8, 2001 21
ZHSTHRU70 to 110 Ohms
(red cursors)
ZHSTERM80 to 100 Ohms(yellow region)
USB connector
Excursion of ZHSTHRU passes using exception window
TDR Test ProcedureTDR Test Procedure
Measuring TDR responseMeasuring TDR response
May 8, 2001 22
Violates ZHSTHRU for > 800psViolates ZHSTHRU for > 800ps
TDR Test ProcedureTDR Test Procedure
TDR Test FailsTDR Test Fails– Cause: Using a ribbon cable between the PCB & USB connectorCause: Using a ribbon cable between the PCB & USB connector
May 8, 2001 23
Other Test ModesOther Test Modes
Test_J & Test_KTest_J & Test_K– Port enters and remains in the high-speedPort enters and remains in the high-speed
J or K stateJ or K state– Allows testing of output voltage and impedanceAllows testing of output voltage and impedance
when each output is high or lowwhen each output is high or low Test Force EnableTest Force Enable
– Allows testing disconnectAllows testing disconnect
May 8, 2001 24
ConclusionsConclusions
High Speed Electrical Testing is Comprehensive High Speed Electrical Testing is Comprehensive – Electrical TestingElectrical Testing
HS Signal QualityHS Signal Quality TDRTDR Receiver SensitivityReceiver Sensitivity Suspend/ResumeSuspend/Resume
– Repeater TestingRepeater Testing Sync truncation, EOP dribble, etcSync truncation, EOP dribble, etc
Well Documented TestsWell Documented Tests– Test ProceduresTest Procedures– Test SpecificationsTest Specifications