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WINTER 2014 ASSIGNMENT

PROGRAM MCA (REVISED FALL 2012)

SEMESTER FOURTH

SUBJECT CODE & NAME MCA4010- MICROPROSESSOR

CREDIT 4 BK ID B1 ! MA"# MARKS $0

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The central processing unit (CPU) is the electronic brain of the computer. CPU consists of Arithmetic Logic

Unit (ALU) and Control Unit (CU).

(I) A ' + ' L, ' U ' (ALU). The arithmetic logic unit (ALU) is responsible for arithmetic and logical

operations. Basically an Arithmetic-Logic Unit (ALU) is an electronic circuit used to carry out the arithmetic

operations li e addition! subtraction! multiplication and di"ision. #t also carries out logical operations li e

greater than! less than! e$ual to etc. #t performs the operation on the data pro"ided by the input de"ices. #t also

does the comparison operation %hich allo%s a program to ma e decisions based on its data input and results of

the pre"ious calculations. The ALU operates on the data a"ailable in the main memory and sends them bac

after processing again to main memory.

(II) C, , U ' (CU). CU controls the o"erall operations of the computer. it is the chief coordinator of all

the operations or acti"ities ta ing place in the computer system. #ts main functions are to control the transfer

of data and information bet%een "arious units and to initiate appropriate actions by the arithmetic-logic unit.

#t fetches instructions from the memory! decodes them! and directs them to "arious units to perform the

specified tas s.

#n addition to ALU and CU! CPU also has a set of registers for temporary storage of data! instructions!

addresses and intermediate results of calculation. The processor is plugged into the computer&s motherboard.

The processing capacity of a computer is measured in terms the amount of data processed by the CPU in one

operation.

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B) M , 5 U ' . 'emory unit stores the data! instructions! intermediate results and output temporarily!

during the processing of data. This memory is also called the main memory or primary memory of the

computer. The input data that is to be processed %ill be usually brought into the main memory before

processing. #t also stores the instructions re$uired for processing of data and any intermediate results. The

output is stored in memory before being transferred to the output de"ice. CPU can %or %ith the information

stored in the main memory. The follo%ing points are important as far as memory is concerned.! B' * 9 1 B5

1024 B5 * 9 1 K' ,35 (KB)

1024 K' ,35 * 9 1 M /35 (MB)

1024 M /35 * 9 1 G' /35 (GB)

The number of bits stored in a register is called a memory word. ifferent inds of primary memory are

andom Access 'emory ( A') and ead *nly 'emory ( *'). +ou can read and %rite data in A' but it is

"olatile meaning %hene"er the po%er is s%itched off the contents of A' is lost. ,o it is re$uired to store the

data in the secondary memory if the data is re$uired for the future use.

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calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction

$ueue. ecution unit use the instruction $ueue to e ecute the instructions. Both B#U and U %or

asynchronously to e ecute instructions by using Pipelining mechanism %hich means o"erlapping of instruction

fetch and e ecute mechanism.

The pipelining results in efficient use of system bus and increases system performance.The parts of B#U are/

i. #nstruction 0ueue

ii. ,egment egisters

iii. #nstruction Pointer

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The prefetched instruction bytes are stored in a first in first out (1#1*) group of registers called aninstruction queue for the ecution Unit ( U). 2hen the U is ready for its ne t instruction! it simply reads

the instruction from this instruction $ueue. This is much faster than sending out an address to the system

memory and to send bac the ne t instruction byte.

''# S R '* *

The B#U contains four 34-bit segment registers. These are/

i) tra ,egment ( ,) register!

ii) Code ,egment (C,) registers!

iii) ata ,egment ( ,) registers! and

i") ,tac ,egment (,,) registers.

'''# I * @ ', P,' (IP) : #t holds the 34 bit address of the ne t instruction to be e ecuted.

B) E @ ', U ' (EU )

#t decodes the instructions fetched by B#U! generates control signals and e ecutes the instruction # The main

parts of ecution unit are/

i) Control system!

ii) Arithmetic and Logic Unit (ALU)

iii) #nstruction decoder unit.

i") 1lag egister

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") 5eneral purpose registers and

"i) Pointers and inde registers

(') C, , S5* . Control system performs "arious internal operations.

('') A ' + ' / < , ' / @ ' . Arithmetic and logical unit performs different arithmetic operations li e

increment! decrement operations etc. and logical operations li e A6 ! * ! 6* T etc.

(''') I * @ ', D ,< . This is used to decode the instructions that ma e up a program %hen they are

being processed! and to determine in %hat actions must be ta en in order to process them.

(' ) F / R '* . 1lag register is a 34 bit register ha"ing 34 flip flops. 1lag egister sho%s the condition or

changes produced by the e ecution of an instruction and these flags get modified as and %hen mathematical or

logical operations are performed.

General Purpose Registers

7874 microprocessor contains eight general purpose registers. They are! AL! BL! CL! L! A9! B9! C9 and 9.

All these registers can store 7 bits (one byte) of data. A pairs of registers are also used to store 34 bits of data.

The register pairs are/ AL-A9! BL-B9! CL-C9 and L- 9 and these pairs are called as A:! B:! C: and :

respecti"ely.

P,' * / < I < R '* *

Stack Pointer Register: #t is a 34-bit register pointing to program stac in stac segment.

,ome other registers are also there in e ecution unit. These are

SI (*,@ ' < ). #t is a 34-bit register. ,# is used for inde ed! based inde ed and register indirect

addressing (these addressing modes are e plained in unit ;)! as %ell as a source data address in stringmanipulation instructions #.

DI (< * ' / ', ' < ). #t is a 34-bit register. # is used for inde ed! based inde ed and register indirect

addressing! as %ell as a destination data address in string manipulation instructions

BP (3/* ,' ). #t is a 34-bit register pointing to data in stac segment. BP register is usually used for

based! based inde ed or register indirect addressing.

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REP P '

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Because string operations inherently in"ol"e looping! the 7874 machine language includes a prefi that

considerably simplifies the use of string primiti"es %ith loops. This prefi has the machine code

3 3 3 3 38 8 3 <

%here! for the C'P, and ,CA, primiti"es! the < bit helps control the loop. By prefi ing '*=,! L* , and

,T*,! %hich do not affect the flags! %ith the P prefi 33338833! they are repeated the number of times

indicated by the C: register according to the follo%ing steps/3. #f (C:) > 8! e it the P operation.

?. Perform the specified primiti"e.

@. ecrement C: by 3.

;. epeat steps 3 through @.

1or the C'P, and ,CA, primiti"es! %hich do affect the flags! the prefi causes them to be repeated the number

of times indicated by the C: register or until the

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B) T/3 T / * / ',

#t is sometimes necessary to translate from one code to another. A terminal may communicate %ith the

computer using the BC #C ( tended Binary Coded ecimal #nterchange Code) alphanumeric code e"en

though the computer s soft%are is designed to %or %ith the A,C## (American ,tandard Code for #nformation

#nterchange) code! or "ice "ersa. Code con"ersions in"ol"ing fe%er than 7 bits (%hich accommodates up to ? 4

distinct entities) can be performed most easily by storing the desired code in an array of up to ? 4 bytes andletting the original code be the inde %ithin the array of the desired code "alues. #f the BC #C code %ere

being con"erted to the A,C## code! then the BC #C code "alue for DAD! %hich is 33888883! %ould be added to

the address of the beginning of the array. Then! by putting the A,C## code for A! %hich is 83888883! in the

array element ha"ing the address of the array plus 88C3! the code con"ersion is readily accomplished.

The 7874 has an instruction specifically designed for e ecuting this procedure. #t is the :LAT instruction. This

instruction may appear either as :LATB or :LAT *P . Both forms produce the follo%ing 3-byte machine

language instruction/

3338383333

#n the :LAT *P form! *P is a dummy operand that is normally the "ariable name associated %ith the

translation table and ser"es only to impro"e the readability of the program. The :LAT instruction assumes the

base address of the byte array is in the B: register and the byte to be con"erted is in the AL register. The

desired code "alue is ta en from the array and put in the AL register. 6one of the flags are affected.

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A *8 . K 5- ,< D/ / F, / *. After a "alid Eey closure! the ey code is entered as a byte code into the 1#1* A'! in the follo%ing format! in

scanned eyboard mode. The Eey code format contains @-bit contents of the internal ro% counter! @-bit

contents of the column counter and status of the ,9#1T and C6TL Eeys The data format of the Eey code in

scanned eyboard mode is sho%n in figure 7.?4.

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#n the sensor matri mode! the data from the return lines is directly entered into an appropriate ro% of sensor

A' that identifies the ro% of the sensor that changes its status. The ,9#1T and C6TL Eeys are ignored in this

mode. L bits represent the return lines. n represents the sensor A' ro% number that is e$ual to the ro%

number of the sensor array in %hich the status change %as detected. ata format of the sensor code in sensor

matri mode is sho%n in figure 7.?F.

F' @ !#2 . D/ / , / , + * *, ,< ' * *, / ' ,< #

FIFO S / @* W,

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(/) RS 2=2 * /

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F' @ . ? -P' D- 5 C, , P' A**'

RS2=2 , DB26 (26- ' D- 5 , , )

'ost of the pins in B-? connector are not needed for normal PC communications! and indeed! most ne% PCs

are e$uipped %ith male type connectors ha"ing only G pins. +ou can e tend normal cable limitation of 8 feet

to se"eral hundred feet %ith high-$uality cable by using a ? -pin B-? or G-pin B-G connector. ,-?@?

defines the purpose and signal timing for each of the ? linesJ ho%e"er! many applications use less than a

doHen.

B) IEEE-4!! S /

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K listener

K Tal er

All of %hich are connected through the # -;77 connector. A Tal er sends data messages to one or more

Listeners! %hich recei"e the data. The Controller manages the flo% of information on the 5P#B by sending

commands to all de"ices. A digital "oltmeter! for e ample! is a Tal er and is also a Listener. The 5P#B or #;77 bus is a "ery fle ible system and it allo%s the data to flo% bet%een any of the instruments on the bus! at a

speed suitable for the slo%est acti"e instrument. #t is possible to purchase 5P#B cards to incorporate into

computers that do not ha"e the interface fitted. As 5P#B cards are relati"ely cheap! this ma es the inclusion of

a 5P#B card into the system a "ery cost effect method of installing it.

The important ey features are/

K Up to 3 de"ices may be connected to one bus.

K Total bus length may be up to ?8 m and the distance bet%een de"ices may be up to ? m

K Communication is digital (as opposed to analog) and messages are sent one byte (7 bits) at a time.K ata rates may be up to 3 'byte sec

The connector used for the # ;77 bus is standardiHed as a ?;-%ay Amphenol F series type. This pro"ides

an ideal physical interface for the standard. The # ;77 or 5P#B connector is "ery similar in format to those

that %ere used for parallel printer ports on PCs.

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3) U ' */ S '/ B@* (USB) 676 10

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P/ / P ' I / (LPT)

The parallel printer interface (LPT) is located on the rear panel of the PC. The LPT stands for line printer. The

Parallel Port #nterface on the PC compatible computer is one of the most fle ible interfaces for connecting the

PC to a %ide range of de"ices. The interface %as originally intended purely for connection to printers but due tothe simple nature of the digital control lines it has found many other uses. #ts simplicity relies on the fact that

the data to and from the port forms an 7 bit binary on off pattern. Unli e serial ports %hich rely on a chip to do

the data transmission! parallel data is handled entirely %ith soft%are. This means that! user has complete

control of the actual on off condition of the output lines directly from his her program. This control is achie"ed

by %riting data to specific areas of PC # * memory. Parallel ports ha"e three registers/ one for data out! one for

output control lines and one for input control lines. The PC standard starts the # * ports for the first parallel

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interface at 8 @F7! and for the second at 8 ?F7. The first port is a bidirectional data registerJ it connects

directly to pins ? through G on the physical connector. The second port is a read-only status registerJ %hen the

parallel port is being used for a printer! this register reports se"eral aspects of printer status! such as being

online! out of paper! or busy. The third port is an output-only control register! %hich! among other things!

controls %hether interrupts are enabled.

B) U ' */ S '/ B@* (USB)

The t%o main problems associated %ith peripherals connected to computer systems today are Dplug and playD

and speed of data transfer. U,B (Uni"ersal ,erial Bus) is designed to o"ercome these problems. ach U,B port

pro"ides a single connector for any de"ice that pre"iously used parallel! serial! eyboard! and mouse or game

ports. U,B pro"ides a serial bus standard for connecting peripherals de"ices to PC %ith simplified addition and

remo"al. U,B can connect peripherals such as mice! eyboards! game pads and oystic s! scanners! digital

cameras! printers! e ternal storage! net%or ing components! etc. The design of U,B is standardiHed by the U,B

#mplementers 1orum (U,B-#1)! an industry standards body incorporating leading companies from the

computer and electronics industries. The figure belo% sho%s the typical Uni"ersal ,erial Bus (U,B).

F' @ . U ' */ S '/ B@* (USB)

U,B system consist of three units

3) U,B host

?) U,B Cable and

@) U,B e"ice.

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