MCF5282 ColdFire Microcontroller User’s Manual Sheets/Freescale Semi... · 2005-02-03 · Clock...

MCF5282 ColdFire® MicrocontrollerUser’s Manual

Devices Supported:MCF5280MCF5281

MCF5282UMRev. 2.311/2004

Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.

Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.

Learn More: For more information about Freescale products, pleasevisit www.freescale.com.

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.

© Freescale Semiconductor, Inc. 2004

MCF5282UMRev. 2.311/2004

How to Reach Us:

Home Page:www.freescale.com

E-mail:[email protected]

USA/Europe or Locations Not Listed:Freescale SemiconductorTechnical Information Center, CH3701300 N. Alma School RoadChandler, Arizona 85224+1-800-521-6274 or [email protected]

Europe, Middle East, and Africa:Freescale Halbleiter Deutschland GmbHTechnical Information CenterSchatzbogen 781829 Muenchen, Germany+44 1296 380 456 (English)+46 8 52200080 (English)+49 89 92103 559 (German)+33 1 69 35 48 48 (French)[email protected]

Japan:Freescale Semiconductor Japan Ltd.HeadquartersARCO Tower 15F1-8-1, Shimo-Meguro, Meguro-ku,Tokyo 153-0064, Japan0120 191014 or +81 3 5437 [email protected]

Asia/Pacific:Freescale Semiconductor Hong Kong Ltd.Technical Information Center2 Dai King StreetTai Po Industrial EstateTai Po, N.T., Hong Kong+800 [email protected]

For Literature Requests Only:Freescale Semiconductor Literature Distribution CenterP.O. Box 5405Denver, Colorado 802171-800-441-2447 or 303-675-2140Fax: [email protected]

OverviewColdFire Core

Enhanced Multiply-Accumulate Unit (EMAC)Cache

Static RAM (SRAM)ColdFire Flash Module (CFM)

Power ManagementSystem Control Module (SCM)

Clock ModuleInterrupt Controller ModulesEdge Port Module (EPORT)

Chip Select ModuleExternal Interface Module (EIM)

Synchronous DRAM Controller ModuleDMA Controller Module

Fast Ethernet Controller (FEC)Watchdog Timer Module

Programmable Interrupt Timer (PIT) Modules General Purpose Timer (GPT) Modules

FlexCAN ModuleGeneral Purpose I/O Module

I2C Module

3

4

5

7

8

9

10

11

12

13

15

16

17

18

19

24

6

20

25

26

21

23

22

DMA TimersQueued Serial Peripheral Interface Module (QSPI)

UART Modules

1

2

27

28

29

30

31

32

33

A

Chip Configuration Module (CCM)Queued Analog-to-Digital Converter (QADC)

Reset Controller ModuleDebug Support

IEEE 1149.1 Test Access Port (JTAG)Mechanical Data

Electrical CharacteristicsAppendix A: List of Memory Maps

INDIndex

Signal Descriptions 14

OverviewColdFire CoreEnhanced Multiply-Accumulate Unit (EMAC)CacheStatic RAM (SRAM)ColdFire Flash Module (CFM)Power ManagementSystem Control Module (SCM)Clock ModuleInterrupt Controller ModulesEdge Port Module (EPORT)Chip Select ModuleExternal Interface Module (EIM)Signal DescriptionsSynchronous DRAM Controller ModuleDMA Controller ModuleFast Ethernet Controller (FEC)Watchdog Timer ModuleProgrammable Interrupt Timer (PIT) Modules General Purpose Timer (GPT) Modules

FlexCAN ModuleGeneral Purpose I/O Module

I2C Module

3

4

5

7

8

9

10

11

12

13

14

15

16

17

18

19

24

6

20

25

26

21

23

22

DMA TimersQueued Serial Peripheral Interface Module (QSPI)UART Modules

1

2

27

28

29

30

31

32

33

A

Chip Configuration Module (CCM)Queued Analog-to-Digital Converter (QADC)Reset Controller ModuleDebug SupportIEEE 1149.1 Test Access Port (JTAG)Mechanical DataElectrical CharacteristicsAppendix A: List of Memory Maps

IND Index

MCF5282 Coldfire Microcontroller User’s Manual, Rev. 2.3

Freescale Semiconductor v

ContentsParagraphNumber

Title PageNumber

Chapter 1 Overview

1.1 MCF5282 Key Features.................................................................................................. 1-11.1.1 Version 2 ColdFire Core............................................................................................. 1-71.1.1.1 Cache ...................................................................................................................... 1-71.1.1.2 SRAM..................................................................................................................... 1-71.1.1.3 Flash........................................................................................................................ 1-81.1.1.4 Debug Module ........................................................................................................ 1-81.1.2 System Control Module .............................................................................................. 1-81.1.3 External Interface Module (EIM) ............................................................................... 1-91.1.4 Chip Select.................................................................................................................. 1-91.1.5 Power Management .................................................................................................... 1-91.1.6 General Input/Output Ports......................................................................................... 1-91.1.7 Interrupt Controllers (INTC0/INTC1) ........................................................................ 1-91.1.8 SDRAM Controller..................................................................................................... 1-91.1.9 Test Access Port........................................................................................................ 1-101.1.10 UART Modules......................................................................................................... 1-101.1.11 DMA Timers (DTIM0-DTIM3) ............................................................................... 1-111.1.12 General-Purpose Timers (GPTA/GPTB).................................................................. 1-111.1.13 Periodic Interrupt Timers (PIT0-PIT3)..................................................................... 1-111.1.14 Software Watchdog Timer........................................................................................ 1-111.1.15 Phase Locked Loop (PLL)........................................................................................ 1-111.1.16 DMA Controller........................................................................................................ 1-111.1.17 Reset.......................................................................................................................... 1-121.2 MCF5282-Specific Features ......................................................................................... 1-121.2.1 Fast Ethernet Controller (FEC)................................................................................. 1-121.2.2 FlexCAN................................................................................................................... 1-121.2.3 I2C Bus...................................................................................................................... 1-121.2.4 Queued Serial Peripheral Interface (QSPI)............................................................... 1-121.2.5 Queued Analog-to-Digital Converter (QADC) ........................................................ 1-13

Chapter 2 ColdFire Core

2.1 Processor Pipelines ......................................................................................................... 2-12.2 Processor Register Description....................................................................................... 2-22.2.1 User Programming Model .......................................................................................... 2-2


vi Freescale Semiconductor


Title PageNumber

2.2.1.1 Data Registers (D0–D7) ......................................................................................... 2-22.2.1.2 Address Registers (A0–A6).................................................................................... 2-22.2.1.3 Stack Pointer (A7) .................................................................................................. 2-22.2.1.4 Program Counter (PC) ............................................................................................ 2-32.2.1.5 Condition Code Register (CCR)............................................................................. 2-32.2.2 Programming Model ................................................................................................. 2-42.2.3 Supervisor Programming Model................................................................................. 2-42.2.3.1 Status Register (SR)................................................................................................ 2-52.2.3.2 Supervisor/User Stack Pointers (A7 and OTHER_A7).......................................... 2-62.2.3.3 Vector Base Register (VBR) .................................................................................. 2-62.2.3.4 Cache Control Register (CACR) ............................................................................ 2-62.2.3.5 Access Control Registers (ACR0, ACR1).............................................................. 2-72.2.3.6 Memory Base Address Registers (RAMBAR, FLASHBAR)................................ 2-72.3 Programming Model ....................................................................................................... 2-72.4 Additions to the Instruction Set Architecture ................................................................. 2-82.5 Exception Processing Overview ..................................................................................... 2-82.6 Exception Stack Frame Definition................................................................................ 2-102.7 Processor Exceptions .................................................................................................... 2-112.7.1 Access Error Exception ............................................................................................ 2-112.7.2 Address Error Exception........................................................................................... 2-122.7.3 Illegal Instruction Exception..................................................................................... 2-122.7.4 Divide-By-Zero......................................................................................................... 2-122.7.5 Privilege Violation.................................................................................................... 2-122.7.6 Trace Exception ........................................................................................................ 2-122.7.7 Unimplemented Line-A Opcode............................................................................... 2-132.7.8 Unimplemented Line-F Opcode ............................................................................... 2-132.7.9 Debug Interrupt......................................................................................................... 2-132.7.10 RTE and Format Error Exception............................................................................. 2-132.7.11 TRAP Instruction Exception..................................................................................... 2-132.7.12 Interrupt Exception ................................................................................................... 2-142.7.13 Fault-on-Fault Halt ................................................................................................... 2-142.7.14 Reset Exception ........................................................................................................ 2-142.8 Instruction Execution Timing ....................................................................................... 2-192.8.1 Timing Assumptions................................................................................................. 2-192.8.2 MOVE Instruction Execution Times ........................................................................ 2-202.9 Standard One Operand Instruction - Execution Times ................................................. 2-212.10 Standard Two Operand Instruction - Execution Times ................................................ 2-222.11 Miscellaneous Instruction Execution Times................................................................. 2-242.12 EMAC Instruction Execution Times ............................................................................ 2-242.13 Branch Instruction Execution Times ............................................................................ 2-262.14 ColdFire Instruction Set Architecture Enhancements .................................................. 2-26


Freescale Semiconductor vii


Title PageNumber

Chapter 3 Enhanced Multiply-Accumulate Unit (EMAC)

3.1 Multiply-Accumulate Unit.............................................................................................. 3-13.2 Introduction to the MAC................................................................................................. 3-23.3 General Operation........................................................................................................... 3-33.4 Memory Map/Register Set.............................................................................................. 3-33.4.1 MAC Status Register (MACSR)................................................................................. 3-33.4.1.1 Fractional Operation Mode..................................................................................... 3-53.4.2 Mask Register (MASK) .............................................................................................. 3-73.5 MAC Instruction Set Summary ...................................................................................... 3-83.5.1 MAC Instruction Execution Times............................................................................. 3-83.5.2 Data Representation.................................................................................................... 3-83.5.3 MAC Opcodes ............................................................................................................ 3-9

Chapter 4 Cache

4.1 Cache Features ................................................................................................................ 4-14.2 Cache Physical Organization .......................................................................................... 4-14.3 Cache Operation ............................................................................................................. 4-24.3.1 Interaction with Other Modules.................................................................................. 4-24.3.2 Memory Reference Attributes .................................................................................... 4-34.3.3 Cache Coherency and Invalidation ............................................................................. 4-34.3.4 Reset............................................................................................................................ 4-34.3.5 Cache Miss Fetch Algorithm/Line Fills...................................................................... 4-34.4 Cache Programming Model ............................................................................................ 4-54.4.1 Cache Registers Memory Map ................................................................................... 4-54.4.2 Cache Registers........................................................................................................... 4-64.4.2.1 Cache Control Register (CACR) ............................................................................ 4-64.4.2.2 Access Control Registers (ACR0, ACR1).............................................................. 4-9

Chapter 5 Static RAM (SRAM)

5.1 SRAM Features............................................................................................................... 5-15.2 SRAM Operation ............................................................................................................ 5-15.3 SRAM Programming Model........................................................................................... 5-15.3.1 SRAM Base Address Register (RAMBAR)............................................................... 5-15.3.2 SRAM Initialization.................................................................................................... 5-3


viii Freescale Semiconductor


Title PageNumber

5.3.3 SRAM Initialization Code .......................................................................................... 5-35.3.4 Power Management .................................................................................................... 5-4

Chapter 6 ColdFire Flash Module (CFM)

6.1 Features ........................................................................................................................... 6-16.2 Block Diagram................................................................................................................ 6-16.3 Memory Map .................................................................................................................. 6-46.3.1 CFM Configuration Field ........................................................................................... 6-56.3.2 Flash Base Address Register (FLASHBAR) .............................................................. 6-56.3.3 CFM Registers ............................................................................................................ 6-76.3.4 Register Descriptions.................................................................................................. 6-86.3.4.1 CFM Configuration Register (CFMCR)................................................................. 6-86.3.4.2 CFM Clock Divider Register (CFMCLKD)........................................................... 6-96.3.4.3 CFM Security Register (CFMSEC)...................................................................... 6-106.3.4.4 CFM Protection Register (CFMPROT)................................................................ 6-126.3.4.5 CFM Supervisor Access Register (CFMSACC) .................................................. 6-136.3.4.6 CFM Data Access Register (CFMDACC) ........................................................... 6-146.3.4.7 CFM User Status Register (CFMUSTAT) ........................................................... 6-156.3.4.8 CFM Command Register (CFMCMD)................................................................. 6-166.4 CFM Operation ............................................................................................................. 6-166.4.1 Read Operations........................................................................................................ 6-176.4.2 Write Operations....................................................................................................... 6-176.4.3 Program and Erase Operations ................................................................................. 6-176.4.3.1 Setting the CFMCLKD Register .......................................................................... 6-176.4.3.2 Program, Erase, and Verify Sequences................................................................. 6-186.4.3.3 Flash Valid Commands......................................................................................... 6-196.4.3.4 Flash User Mode Illegal Operations ..................................................................... 6-226.4.4 Stop Mode................................................................................................................. 6-226.4.5 Master Mode ............................................................................................................. 6-236.5 Flash Security Operation .............................................................................................. 6-236.5.1 Back Door Access..................................................................................................... 6-246.5.2 Erase Verify Check................................................................................................... 6-246.6 Reset.............................................................................................................................. 6-246.7 Interrupts ....................................................................................................................... 6-24

Chapter 7 Power Management


Freescale Semiconductor ix


Title PageNumber

7.1 Features ........................................................................................................................... 7-17.2 Memory Map and Registers............................................................................................ 7-17.2.1 Programming Model ................................................................................................... 7-17.2.2 Memory Map .............................................................................................................. 7-27.2.3 Register Descriptions.................................................................................................. 7-27.2.3.1 Low-Power Interrupt Control Register (LPICR).................................................... 7-27.2.3.2 Low-Power Control Register (LPCR) .................................................................... 7-47.3 Functional Description.................................................................................................... 7-57.3.1 Low-Power Modes...................................................................................................... 7-57.3.1.1 Run Mode ............................................................................................................... 7-57.3.1.2 Wait Mode .............................................................................................................. 7-67.3.1.3 Doze Mode.............................................................................................................. 7-67.3.1.4 Stop Mode............................................................................................................... 7-67.3.1.5 Peripheral Shut Down............................................................................................. 7-67.3.2 Peripheral Behavior in Low-Power Modes ................................................................ 7-67.3.2.1 ColdFire Core ......................................................................................................... 7-67.3.2.2 Static Random-Access Memory (SRAM) .............................................................. 7-67.3.2.3 Flash........................................................................................................................ 7-77.3.2.4 System Control Module (SCM).............................................................................. 7-77.3.2.5 SDRAM Controller (SDRAMC) ............................................................................ 7-77.3.2.6 Chip Select Module ................................................................................................ 7-77.3.2.7 DMA Controller (DMAC0–DMA3)....................................................................... 7-77.3.2.8 UART Modules (UART0, UART1, and UART2) ................................................. 7-87.3.2.9 I2C Module............................................................................................................. 7-87.3.2.10 Queued Serial Peripheral Interface (QSPI)............................................................. 7-87.3.2.11 DMA Timers (DMAT0–DMAT3) ......................................................................... 7-87.3.2.12 Interrupt Controllers (INTC0, INTC1) ................................................................... 7-97.3.2.13 Fast Ethernet Controller (FEC)............................................................................... 7-97.3.2.14 I/O Ports.................................................................................................................. 7-97.3.2.15 Reset Controller ...................................................................................................... 7-97.3.2.16 Chip Configuration Module.................................................................................... 7-97.3.2.17 Clock Module ....................................................................................................... 7-107.3.2.18 Edge Port .............................................................................................................. 7-107.3.2.19 Watchdog Timer ................................................................................................... 7-107.3.2.20 Programmable Interrupt Timers (PIT0, PIT1, PIT2 and PIT3) ............................ 7-107.3.2.21 Queued Analog-to-Digital Converter (QADC) .................................................... 7-117.3.2.22 General Purpose Timers (GPTA and GPTB) ....................................................... 7-117.3.2.23 FlexCAN............................................................................................................... 7-117.3.2.24 ColdFire Flash Module ......................................................................................... 7-137.3.2.25 BDM ..................................................................................................................... 7-137.3.2.26 JTAG..................................................................................................................... 7-13


x Freescale Semiconductor


Title PageNumber

7.3.3 Summary of Peripheral State During Low-Power Modes ........................................ 7-13

Chapter 8 System Control Module (SCM)

8.1 Overview......................................................................................................................... 8-18.2 Features ........................................................................................................................... 8-18.3 Memory Map and Register Definition............................................................................ 8-18.4 Register Descriptions ...................................................................................................... 8-28.4.1 Internal Peripheral System Base Address Register (IPSBAR)................................... 8-28.4.2 Memory Base Address Register (RAMBAR) ............................................................ 8-38.4.3 Core Reset Status Register (CRSR)............................................................................ 8-48.4.4 Core Watchdog Control Register (CWCR) ................................................................ 8-58.4.5 Core Watchdog Service Register (CWSR)................................................................. 8-78.5 Internal Bus Arbitration .................................................................................................. 8-78.5.1 Overview..................................................................................................................... 8-88.5.2 Arbitration Algorithms ............................................................................................... 8-98.5.2.1 Round-Robin Mode ................................................................................................ 8-98.5.2.2 Fixed Mode............................................................................................................. 8-98.5.3 Bus Master Park Register (MPARK).......................................................................... 8-98.6 System Access Control Unit (SACU)........................................................................... 8-118.6.1 Overview................................................................................................................... 8-118.6.2 Features..................................................................................................................... 8-118.6.3 Memory Map/Register Definition ............................................................................ 8-128.6.3.1 Master Privilege Register (MPR) ........................................................................ 8-138.6.3.2 Peripheral Access Control Registers (PACR 0–PACR8)..................................... 8-138.6.3.3 Grouped Peripheral Access Control Registers (GPACR0 & GPACR1) .............. 8-15

Chapter 9 Clock Module

9.1 Features ........................................................................................................................... 9-19.2 Modes of Operation ........................................................................................................ 9-19.2.1 Normal PLL Mode...................................................................................................... 9-19.2.2 1:1 PLL Mode............................................................................................................. 9-19.2.3 External Clock Mode .................................................................................................. 9-19.3 Low-power Mode Operation .......................................................................................... 9-19.4 Block Diagram................................................................................................................ 9-29.5 Signal Descriptions ......................................................................................................... 9-49.5.1 EXTAL ....................................................................................................................... 9-4


Freescale Semiconductor xi


Title PageNumber

9.5.2 XTAL.......................................................................................................................... 9-59.5.3 CLKOUT .................................................................................................................... 9-59.5.4 CLKMOD[1:0] ........................................................................................................... 9-59.5.5 RSTOUT..................................................................................................................... 9-59.6 Memory Map and Registers............................................................................................ 9-59.6.1 Module Memory Map................................................................................................. 9-59.6.2 Register Descriptions.................................................................................................. 9-69.6.2.1 Synthesizer Control Register (SYNCR) ................................................................. 9-69.6.2.2 Synthesizer Status Register (SYNSR) .................................................................... 9-89.7 Functional Description.................................................................................................. 9-109.7.1 System Clock Modes ................................................................................................ 9-109.7.2 Clock Operation During Reset.................................................................................. 9-119.7.3 System Clock Generation ......................................................................................... 9-119.7.4 PLL Operation .......................................................................................................... 9-119.7.4.1 Phase and Frequency Detector (PFD)................................................................... 9-129.7.4.2 Charge Pump/Loop Filter ..................................................................................... 9-139.7.4.3 Voltage Control Output (VCO) ............................................................................ 9-139.7.4.4 Multiplication Factor Divider (MFD)................................................................... 9-139.7.4.5 PLL Lock Detection ............................................................................................. 9-139.7.4.6 PLL Loss of Lock Conditions............................................................................... 9-149.7.4.7 PLL Loss of Lock Reset ....................................................................................... 9-159.7.4.8 Loss of Clock Detection ....................................................................................... 9-159.7.4.9 Loss of Clock Reset .............................................................................................. 9-159.7.4.10 Alternate Clock Selection ..................................................................................... 9-159.7.4.11 Loss of Clock in Stop Mode ................................................................................. 9-16

Chapter 10 Interrupt Controller Modules

10.1 68K/ColdFire Interrupt Architecture Overview ........................................................... 10-110.1.1 Interrupt Controller Theory of Operation ................................................................. 10-210.1.1.1 Interrupt Recognition............................................................................................ 10-310.1.1.2 Interrupt Prioritization .......................................................................................... 10-310.1.1.3 Interrupt Vector Determination ............................................................................ 10-310.2 Memory Map ................................................................................................................ 10-410.3 Register Descriptions .................................................................................................... 10-510.3.1 Interrupt Pending Registers (IPRHn, IPRLn) ........................................................... 10-510.3.2 Interrupt Mask Register (IMRHn, IMRLn) .............................................................. 10-710.3.3 Interrupt Force Registers (INTFRCHn, INTFRCLn) ............................................... 10-810.3.4 Interrupt Request Level Register (IRLRn) ............................................................. 10-1010.3.5 Interrupt Acknowledge Level and Priority Register (IACKLPRn) ........................ 10-10


xii Freescale Semiconductor


Title PageNumber

10.3.6 Interrupt Control Register (ICRnx, (x = 1, 2,..., 63)).............................................. 10-1110.3.6.1 Interrupt Sources................................................................................................. 10-1110.3.7 Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)............. 10-1510.4 Prioritization Between Interrupt Controllers .............................................................. 10-1610.5 Low-Power Wakeup Operation .................................................................................. 10-16

Chapter 11 Edge Port Module (EPORT)

11.1 Introduction................................................................................................................... 11-111.2 Low-Power Mode Operation ........................................................................................ 11-111.3 Interrupt/General-Purpose I/O Pin Descriptions........................................................... 11-211.4 Memory Map and Registers.......................................................................................... 11-311.4.1 Memory Map ............................................................................................................ 11-311.4.2 Registers.................................................................................................................... 11-311.4.2.1 EPORT Pin Assignment Register (EPPAR)......................................................... 11-311.4.2.2 EPORT Data Direction Register (EPDDR).......................................................... 11-411.4.2.3 Edge Port Interrupt Enable Register (EPIER) ...................................................... 11-511.4.2.4 Edge Port Data Register (EPDR).......................................................................... 11-511.4.2.5 Edge Port Pin Data Register (EPPDR) ................................................................. 11-611.4.2.6 Edge Port Flag Register (EPFR)........................................................................... 11-6

Chapter 12 Chip Select Module

12.1 Overview....................................................................................................................... 12-112.2 Chip Select Module Signals.......................................................................................... 12-112.3 Chip Select Operation................................................................................................... 12-312.3.1 General Chip Select Operation ................................................................................. 12-312.3.1.1 8-, 16-, and 32-Bit Port Sizing.............................................................................. 12-412.3.1.2 External Boot Chip Select Operation ................................................................... 12-412.4 Chip Select Registers .................................................................................................... 12-512.4.1 Chip Select Module Registers................................................................................... 12-612.4.1.1 Chip Select Address Registers (CSAR0–CSAR6) ............................................... 12-612.4.1.2 Chip Select Mask Registers (CSMR0–CSMR6) .................................................. 12-712.4.1.3 Chip Select Control Registers (CSCR0–CSCR6)................................................. 12-8

Chapter 13 External Interface Module (EIM)


Freescale Semiconductor xiii


Title PageNumber

13.1 Features ......................................................................................................................... 13-113.2 Bus and Control Signals ............................................................................................... 13-113.3 Bus Characteristics ....................................................................................................... 13-113.4 Data Transfer Operation ............................................................................................... 13-213.4.1 Bus Cycle Execution................................................................................................. 13-313.4.2 Data Transfer Cycle States ....................................................................................... 13-413.4.3 Read Cycle................................................................................................................ 13-613.4.4 Write Cycle ............................................................................................................... 13-713.4.5 Fast Termination Cycles ........................................................................................... 13-813.4.6 Back-to-Back Bus Cycles ......................................................................................... 13-913.4.7 Burst Cycles............................................................................................................ 13-1013.4.7.1 Line Transfers ..................................................................................................... 13-1013.4.7.2 Line Read Bus Cycles......................................................................................... 13-1013.4.7.3 Line Write Bus Cycles........................................................................................ 13-1213.5 Misaligned Operands .................................................................................................. 13-14

Chapter 14 Signal Descriptions

14.1 Overview....................................................................................................................... 14-114.1.1 Single-Chip Mode................................................................................................... 14-1714.1.2 External Boot Mode................................................................................................ 14-1714.2 MCF5282 External Signals......................................................................................... 14-1814.2.1 External Interface Module (EIM) Signals .............................................................. 14-1814.2.1.1 Address Bus (A[23:0])........................................................................................ 14-1814.2.1.2 Data Bus (D[31:0]) ............................................................................................. 14-1814.2.1.3 Byte Strobes (BS[3:0]) ....................................................................................... 14-1814.2.1.4 Output Enable (OE) ............................................................................................ 14-1914.2.1.5 Transfer Acknowledge (TA)............................................................................... 14-1914.2.1.6 Transfer Error Acknowledge (TEA)................................................................... 14-1914.2.1.7 Read/Write (R/W)............................................................................................... 14-1914.2.1.8 Transfer Size(SIZ[1:0]) ...................................................................................... 14-1914.2.1.9 Transfer Start (TS).............................................................................................. 14-2014.2.1.10 Transfer In Progress (TIP) .................................................................................. 14-2014.2.1.11 Chip Selects (CS[6:0]) ........................................................................................ 14-2014.2.2 SDRAM Controller Signals .................................................................................... 14-2014.2.2.1 SDRAM Row Address Strobe (SRAS) .............................................................. 14-2014.2.2.2 SDRAM Column Address Strobe (SCAS) ......................................................... 14-2014.2.2.3 SDRAM Write Enable (DRAMW) .................................................................... 14-2114.2.2.4 SDRAM Bank Selects (SDRAM_CS[1:0])........................................................ 14-2114.2.2.5 SDRAM Clock Enable (SCKE).......................................................................... 14-21


xiv Freescale Semiconductor


Title PageNumber

14.2.3 Clock and Reset Signals ......................................................................................... 14-2114.2.3.1 Reset In (RSTI)................................................................................................... 14-2114.2.3.2 Reset Out (RSTO)............................................................................................... 14-2114.2.3.3 EXTAL ............................................................................................................... 14-2114.2.3.4 XTAL.................................................................................................................. 14-2114.2.3.5 Clock Output (CLKOUT)................................................................................... 14-2114.2.4 Chip Configuration Signals .................................................................................... 14-2214.2.4.1 RCON ................................................................................................................. 14-2214.2.4.2 CLKMOD[1:0] ................................................................................................... 14-2214.2.5 External Interrupt Signals ....................................................................................... 14-2214.2.5.1 External Interrupts (IRQ[7:1]) ............................................................................ 14-2214.2.6 Ethernet Module Signals......................................................................................... 14-2214.2.6.1 Management Data (EMDIO) .............................................................................. 14-2214.2.6.2 Management Data Clock (EMDC) ..................................................................... 14-2214.2.6.3 Transmit Clock (ETXCLK)................................................................................ 14-2214.2.6.4 Transmit Enable (ETXEN) ................................................................................. 14-2314.2.6.5 Transmit Data 0 (ETXD0) .................................................................................. 14-2314.2.6.6 Collision (ECOL)................................................................................................ 14-2314.2.6.7 Receive Clock (ERXCLK) ................................................................................. 14-2314.2.6.8 Receive Data Valid (ERXDV)............................................................................ 14-2314.2.6.9 Receive Data 0 (ERXD0) ................................................................................... 14-2314.2.6.10 Carrier Receive Sense (ECRS) ........................................................................... 14-2314.2.6.11 Transmit Data 1–3 (ETXD[3:1]) ........................................................................ 14-2314.2.6.12 Transmit Error (ETXER).................................................................................... 14-2414.2.6.13 Receive Data 1–3 (ERXD[3:1]).......................................................................... 14-2414.2.6.14 Receive Error (ERXER) ..................................................................................... 14-2414.2.7 Queued Serial Peripheral Interface (QSPI) Signals................................................ 14-2414.2.7.1 QSPI Synchronous Serial Output (QSPI_DOUT).............................................. 14-2414.2.7.2 QSPI Synchronous Serial Data Input (QSPI_DIN) ............................................ 14-2414.2.7.3 QSPI Serial Clock (QSPI_CLK) ........................................................................ 14-2414.2.7.4 QSPI Chip Selects (QSPI_CS[3:0]).................................................................... 14-2414.2.8 FlexCAN Signals .................................................................................................... 14-2514.2.8.1 FlexCAN Transmit (CANTX)............................................................................ 14-2514.2.8.2 FlexCAN Receive (CANRX) ............................................................................. 14-2514.2.9 I2C Signals .............................................................................................................. 14-2514.2.9.1 Serial Clock (SCL) ............................................................................................. 14-2514.2.9.2 Serial Data (SDA)............................................................................................... 14-2514.2.10 UART Module Signals ........................................................................................... 14-2514.2.10.1 Transmit Serial Data Output (UTXD[2:0]) ........................................................ 14-2514.2.10.2 Receive Serial Data Input (URXD[2:0]) ............................................................ 14-2514.2.10.3 Clear-to-Send (UCTS[1:0]) ................................................................................ 14-26


Freescale Semiconductor xv


Title PageNumber

14.2.10.4 Request-to-Send (URTS[1:0]) ............................................................................ 14-2614.2.11 General Purpose Timer Signals .............................................................................. 14-2614.2.11.1 GPTA[3:0] .......................................................................................................... 14-2614.2.11.2 GPTB[3:0] .......................................................................................................... 14-2614.2.11.3 External Clock Input (SYNCA/SYNCB) ........................................................... 14-2614.2.12 DMA Timer Signals................................................................................................ 14-2614.2.12.1 DMA Timer 0 Input (DTIN0)............................................................................. 14-2614.2.12.2 DMA Timer 0 Output (DTOUT0)...................................................................... 14-2714.2.12.3 DMA Timer 1 Input (DTIN1)............................................................................. 14-2714.2.12.4 DMA Timer 1 Output (DTOUT1)...................................................................... 14-2714.2.12.5 DMA Timer 2 Input (DTIN2)............................................................................. 14-2714.2.12.6 DMA Timer 2 Output (DTOUT2)...................................................................... 14-2714.2.12.7 DMA Timer 3 Input (DTIN3)............................................................................. 14-2714.2.12.8 DMA Timer 3 Output (DTOUT3)...................................................................... 14-2714.2.13 Analog-to-Digital Converter Signals ...................................................................... 14-2714.2.13.1 QADC Analog Input (AN0/ANW)..................................................................... 14-2814.2.13.2 QADC Analog Input (AN1/ANX)...................................................................... 14-2814.2.13.3 QADC Analog Input (AN2/ANY)...................................................................... 14-2814.2.13.4 QADC Analog Input (AN3/ANZ) ...................................................................... 14-2814.2.13.5 QADC Analog Input (AN52/MA0).................................................................... 14-2814.2.13.6 QADC Analog Input (AN53/MA1).................................................................... 14-2814.2.13.7 QADC Analog Input (AN55/TRIG1)................................................................. 14-2814.2.13.8 QADC Analog Input (AN56/TRIG2)................................................................. 14-2814.2.14 Debug Support Signals ........................................................................................... 14-2914.2.14.1 JTAG_EN ........................................................................................................... 14-2914.2.14.2 Development Serial Clock/Test Reset (DSCLK/TRST) .................................... 14-2914.2.14.3 Breakpoint/Test Mode Select (BKPT/TMS) ...................................................... 14-2914.2.14.4 Development Serial Input/Test Data (DSI/TDI)................................................. 14-2914.2.14.5 Development Serial Output/Test Data (DSO/TDO)........................................... 14-2914.2.14.6 Test Clock (TCLK)............................................................................................. 14-3014.2.14.7 Debug Data (DDATA[3:0])................................................................................ 14-3014.2.14.8 Processor Status Outputs (PST[3:0]) .................................................................. 14-3014.2.15 Test Signals............................................................................................................. 14-3114.2.15.1 Test (TEST) ........................................................................................................ 14-3114.2.16 Power and Reference Signals ................................................................................. 14-3114.2.16.1 QADC Analog Reference (VRH, VRL)............................................................. 14-3114.2.16.2 QADC Analog Supply (VDDA, VSSA) ............................................................ 14-3114.2.16.3 PLL Analog Supply (VDDPLL, VSSPLL) ........................................................ 14-3114.2.16.4 QADC Positive Supply (VDDH)........................................................................ 14-3114.2.16.5 Power for Flash Erase/Program (VPP) ............................................................... 14-3114.2.16.6 Power and Ground for Flash Array (VDDF, VSSF) .......................................... 14-31


xvi Freescale Semiconductor


Title PageNumber

14.2.16.7 Standby Power (VSTBY) ................................................................................... 14-3114.2.16.8 Positive Supply (VDD)....................................................................................... 14-3114.2.16.9 Ground (VSS) ..................................................................................................... 14-32

Chapter 15 Synchronous DRAM Controller Module

15.1 Overview....................................................................................................................... 15-115.1.1 Definitions ................................................................................................................ 15-115.1.2 Block Diagram and Major Components ................................................................... 15-115.2 SDRAM Controller Operation...................................................................................... 15-315.2.1 DRAM Controller Signals ........................................................................................ 15-415.2.2 Memory Map for SDRAMC Registers..................................................................... 15-415.2.2.1 DRAM Control Register (DCR)........................................................................... 15-515.2.2.2 DRAM Address and Control Registers (DACR0/DACR1) ................................. 15-615.2.2.3 DRAM Controller Mask Registers (DMR0/DMR1) ............................................ 15-815.2.3 General Synchronous Operation Guidelines............................................................. 15-915.2.3.1 Address Multiplexing ........................................................................................... 15-915.2.3.2 SDRAM Byte Strobe Connections ..................................................................... 15-1315.2.3.3 Interfacing Example............................................................................................ 15-1315.2.3.4 Burst Page Mode................................................................................................. 15-1315.2.3.5 Auto-Refresh Operation...................................................................................... 15-1515.2.3.6 Self-Refresh Operation ....................................................................................... 15-1615.2.4 Initialization Sequence............................................................................................ 15-1715.2.4.1 Mode Register Settings....................................................................................... 15-1815.3 SDRAM Example ....................................................................................................... 15-1815.3.1 SDRAM Interface Configuration............................................................................ 15-2015.3.2 DCR Initialization................................................................................................... 15-2015.3.3 DACR Initialization................................................................................................ 15-2015.3.4 DMR Initialization.................................................................................................. 15-2215.3.5 Mode Register Initialization ................................................................................... 15-2315.3.6 Initialization Code................................................................................................... 15-23

Chapter 16 DMA Controller Module

16.1 Overview....................................................................................................................... 16-116.1.1 DMA Module Features ............................................................................................. 16-216.2 DMA Request Control (DMAREQC) .......................................................................... 16-216.3 DMA Transfer Overview.............................................................................................. 16-4


Freescale Semiconductor xvii


Title PageNumber

16.4 DMA Controller Module Programming Model............................................................ 16-416.4.1 Source Address Registers (SAR0–SAR3) ................................................................ 16-516.4.2 Destination Address Registers (DAR0–DAR3) ....................................................... 16-616.4.3 Byte Count Registers (BCR0–BCR3) ...................................................................... 16-716.4.4 DMA Control Registers (DCR0–DCR3).................................................................. 16-716.4.5 DMA Status Registers (DSR0–DSR3) ................................................................... 16-1016.5 DMA Controller Module Functional Description ...................................................... 16-1116.5.1 Transfer Requests (Cycle-Steal and Continuous Modes) ....................................... 16-1116.5.2 Data Transfer Modes .............................................................................................. 16-1216.5.2.1 Dual-Address Transfers ...................................................................................... 16-1216.5.3 Channel Initialization and Startup .......................................................................... 16-1216.5.3.1 Channel Prioritization......................................................................................... 16-1216.5.3.2 Programming the DMA Controller Module ....................................................... 16-1216.5.4 Data Transfer .......................................................................................................... 16-1316.5.4.1 Auto-Alignment.................................................................................................. 16-1316.5.4.2 Bandwidth Control.............................................................................................. 16-1416.5.5 Termination............................................................................................................. 16-14

Chapter 17 Fast Ethernet Controller (FEC)

17.1 Overview....................................................................................................................... 17-117.1.1 Features..................................................................................................................... 17-117.2 Modes of Operation ...................................................................................................... 17-117.2.1 Full and Half Duplex Operation ............................................................................... 17-217.2.2 Interface Options....................................................................................................... 17-217.2.2.1 10 Mbps and 100 Mbps MII Interface.................................................................. 17-217.2.2.2 10 Mpbs 7-Wire Interface Operation.................................................................... 17-217.2.3 Address Recognition Options ................................................................................... 17-217.2.4 Internal Loopback ..................................................................................................... 17-217.3 FEC Top-Level Functional Diagram ............................................................................ 17-317.4 Functional Description.................................................................................................. 17-417.4.1 Initialization Sequence.............................................................................................. 17-417.4.1.1 Hardware Controlled Initialization ....................................................................... 17-417.4.2 User Initialization (Prior to Asserting ECR[ETHER_EN])...................................... 17-517.4.3 Microcontroller Initialization.................................................................................... 17-617.4.4 User Initialization (After Asserting ECR[ETHER_EN]) ......................................... 17-617.4.5 Network Interface Options........................................................................................ 17-617.4.6 FEC Frame Transmission ......................................................................................... 17-717.4.7 FEC Frame Reception............................................................................................... 17-817.4.8 Ethernet Address Recognition .................................................................................. 17-9


xviii Freescale Semiconductor


Title PageNumber

17.4.9 Hash Algorithm....................................................................................................... 17-1117.4.10 Full Duplex Flow Control....................................................................................... 17-1417.4.11 Inter-Packet Gap (IPG) Time.................................................................................. 17-1517.4.12 Collision Handling.................................................................................................. 17-1517.4.13 Internal and External Loopback.............................................................................. 17-1517.4.14 Ethernet Error-Handling Procedure ........................................................................ 17-1517.4.14.1 Transmission Errors............................................................................................ 17-1617.4.14.2 Reception Errors ................................................................................................. 17-1617.5 Programming Model ................................................................................................... 17-1717.5.1 Top Level Module Memory Map ........................................................................... 17-1717.5.2 Detailed Memory Map (Control/Status Registers) ................................................. 17-1717.5.3 MIB Block Counters Memory Map........................................................................ 17-1817.5.4 Registers.................................................................................................................. 17-2017.5.4.1 Ethernet Interrupt Event Register (EIR) ............................................................. 17-2017.5.4.2 Interrupt Mask Register (EIMR) ........................................................................ 17-2317.5.4.3 Receive Descriptor Active Register (RDAR)..................................................... 17-2317.5.4.4 Transmit Descriptor Active Register (TDAR) ................................................... 17-2417.5.4.5 Ethernet Control Register (ECR)........................................................................ 17-2517.5.4.6 MII Management Frame Register (MMFR) ....................................................... 17-2617.5.4.7 MII Speed Control Register (MSCR) ................................................................. 17-2717.5.4.8 MIB Control Register (MIBC) ........................................................................... 17-2917.5.4.9 Receive Control Register (RCR) ........................................................................ 17-3017.5.4.10 Transmit Control Register (TCR)....................................................................... 17-3117.5.4.11 Physical Address Low Register (PALR) ............................................................ 17-3217.5.4.12 Physical Address High Register (PAUR) ........................................................... 17-3317.5.4.13 Opcode/Pause Duration Register (OPD) ............................................................ 17-3417.5.4.14 Descriptor Individual Upper Address Register (IAUR) ..................................... 17-3417.5.4.15 Descriptor Individual Lower Address (IALR) ................................................... 17-3517.5.4.16 Descriptor Group Upper Address (GAUR) ........................................................ 17-3617.5.4.17 Descriptor Group Lower Address (GALR) ........................................................ 17-3617.5.4.18 FIFO Transmit FIFO Watermark Register (TFWR) .......................................... 17-3717.5.4.19 FIFO Receive Bound Register (FRBR).............................................................. 17-3817.5.4.20 FIFO Receive Start Register (FRSR) ................................................................. 17-3917.5.4.21 Receive Descriptor Ring Start (ERDSR)............................................................ 17-3917.5.4.22 Transmit Buffer Descriptor Ring Start (ETSDR)............................................... 17-4017.5.4.23 Receive Buffer Size Register (EMRBR) ............................................................ 17-4117.6 Buffer Descriptors....................................................................................................... 17-4217.6.1 Driver/DMA Operation with Buffer Descriptors.................................................... 17-4217.6.1.1 Driver/DMA Operation with Transmit BDs....................................................... 17-4217.6.1.2 Driver/DMA Operation with Receive BDs ........................................................ 17-4317.6.2 Ethernet Receive Buffer Descriptor (RxBD).......................................................... 17-43


Freescale Semiconductor xix


Title PageNumber

17.6.3 Ethernet Transmit Buffer Descriptor (TxBD) ........................................................ 17-45

Chapter 18 Watchdog Timer Module

18.1 Introduction................................................................................................................... 18-118.2 Low-Power Mode Operation ........................................................................................ 18-118.3 Block Diagram.............................................................................................................. 18-218.4 Signals........................................................................................................................... 18-218.5 Memory Map and Registers.......................................................................................... 18-218.5.1 Memory Map ............................................................................................................ 18-218.5.2 Registers.................................................................................................................... 18-318.5.2.1 Watchdog Control Register (WCR)...................................................................... 18-318.5.2.2 Watchdog Modulus Register (WMR)................................................................... 18-418.5.2.3 Watchdog Count Register (WCNTR)................................................................... 18-518.5.2.4 Watchdog Service Register (WSR) ...................................................................... 18-5

Chapter 19 Programmable Interrupt Timer Modules (PIT0–PIT3)

19.1 Overview....................................................................................................................... 19-119.2 Block Diagram.............................................................................................................. 19-119.3 Low-Power Mode Operation ........................................................................................ 19-219.4 Signals........................................................................................................................... 19-219.5 Memory Map and Registers.......................................................................................... 19-319.5.1 Memory Map ............................................................................................................ 19-319.5.2 Registers.................................................................................................................... 19-319.5.2.1 PIT Control and Status Register (PCSR).............................................................. 19-419.5.2.2 PIT Modulus Register (PMR)............................................................................... 19-519.5.2.3 PIT Count Register (PCNTR)............................................................................... 19-619.6 Functional Description.................................................................................................. 19-619.6.1 Set-and-Forget Timer Operation............................................................................... 19-619.6.2 Free-Running Timer Operation ................................................................................ 19-719.6.3 Timeout Specifications ............................................................................................. 19-719.7 Interrupt Operation ....................................................................................................... 19-7

Chapter 20 General Purpose Timer Modules

(GPTA and GPTB)


xx Freescale Semiconductor


Title PageNumber

20.1 Features ......................................................................................................................... 20-120.2 Block Diagram.............................................................................................................. 20-220.3 Low-Power Mode Operation ........................................................................................ 20-320.4 Signal Description......................................................................................................... 20-320.4.1 GPTn[2:0] ................................................................................................................. 20-320.4.2 GPTn3....................................................................................................................... 20-320.4.3 SYNCn...................................................................................................................... 20-420.5 Memory Map and Registers.......................................................................................... 20-420.5.1 GPT Input Capture/Output Compare Select Register (GPTIOS) ............................. 20-520.5.2 GPT Compare Force Register (GPCFORC)............................................................. 20-620.5.3 GPT Output Compare 3 Mask Register (GPTOC3M).............................................. 20-620.5.4 GPT Output Compare 3 Data Register (GPTOC3D)................................................ 20-720.5.5 GPT Counter Register (GPTCNT) ........................................................................... 20-720.5.6 GPT System Control Register 1 (GPTSCR1)........................................................... 20-820.5.7 GPT Toggle-On-Overflow Register (GPTTOV)...................................................... 20-920.5.8 GPT Control Register 1 (GPTCTL1)........................................................................ 20-920.5.9 GPT Control Register 2 (GPTCTL2)...................................................................... 20-1020.5.10 GPT Interrupt Enable Register (GPTIE) ................................................................ 20-1020.5.11 GPT System Control Register 2 (GPTSCR2)......................................................... 20-1120.5.12 GPT Flag Register 1 (GPTFLG1)........................................................................... 20-1220.5.13 GPT Flag Register 2 (GPTFLG2)........................................................................... 20-1220.5.14 GPT Channel Registers (GPTCn)........................................................................... 20-1320.5.15 Pulse Accumulator Control Register (GPTPACTL) .............................................. 20-1420.5.16 Pulse Accumulator Flag Register (GPTPAFLG).................................................... 20-1520.5.17 Pulse Accumulator Counter Register (GPTPACNT) ............................................. 20-1620.5.18 GPT Port Data Register (GPTPORT)..................................................................... 20-1620.5.19 GPT Port Data Direction Register (GPTDDR)....................................................... 20-1720.6 Functional Description................................................................................................ 20-1720.6.1 Prescaler.................................................................................................................. 20-1720.6.2 Input Capture .......................................................................................................... 20-1720.6.3 Output Compare...................................................................................................... 20-1820.6.4 Pulse Accumulator.................................................................................................. 20-1820.6.5 Event Counter Mode............................................................................................... 20-1820.6.6 Gated Time Accumulation Mode ........................................................................... 20-1920.6.7 General-Purpose I/O Ports ...................................................................................... 20-1920.7 Reset............................................................................................................................ 20-2120.8 Interrupts ..................................................................................................................... 20-2120.8.1 GPT Channel Interrupts (CnF) ............................................................................... 20-2120.8.2 Pulse Accumulator Overflow (PAOVF)................................................................. 20-2220.8.3 Pulse Accumulator Input (PAIF) ............................................................................ 20-2220.8.4 Timer Overflow (TOF) ........................................................................................... 20-22


Freescale Semiconductor xxi


Title PageNumber

Chapter 21 DMA Timers (DTIM0–DTIM3)

21.1 Overview....................................................................................................................... 21-121.1.1 Key Features ............................................................................................................. 21-121.2 DMA Timer Programming Model ................................................................................ 21-221.2.1 Prescaler.................................................................................................................... 21-221.2.2 Capture Mode ........................................................................................................... 21-221.2.3 Reference Compare................................................................................................... 21-221.2.4 Output Mode ............................................................................................................. 21-221.2.5 Memory Map ............................................................................................................ 21-221.2.6 DMA Timer Mode Registers (DTMRn)................................................................... 21-321.2.7 DMA Timer Extended Mode Registers (DTXMRn)................................................ 21-421.2.8 DMA Timer Event Registers (DTERn) .................................................................... 21-521.2.9 DMA Timer Reference Registers (DTRRn)............................................................. 21-621.2.10 DMA Timer Capture Registers (DTCRn) ................................................................ 21-621.2.11 DMA Timer Counters (DTCNn) .............................................................................. 21-721.3 Using the DMA Timer Modules ................................................................................... 21-721.3.1 Code Example........................................................................................................... 21-821.3.2 Calculating Time-Out Values ................................................................................... 21-9

Chapter 22 Queued Serial Peripheral Interface

(QSPI) Module

22.1 Overview....................................................................................................................... 22-122.2 Features ......................................................................................................................... 22-122.3 Module Description ...................................................................................................... 22-122.3.1 Interface and Signals................................................................................................. 22-122.3.2 Internal Bus Interface................................................................................................ 22-222.4 Operation ...................................................................................................................... 22-322.4.1 QSPI RAM................................................................................................................ 22-422.4.1.1 Receive RAM ....................................................................................................... 22-522.4.1.2 Transmit RAM...................................................................................................... 22-522.4.1.3 Command RAM.................................................................................................... 22-522.4.2 Baud Rate Selection.................................................................................................. 22-522.4.3 Transfer Delays......................................................................................................... 22-622.4.4 Transfer Length......................................................................................................... 22-722.4.5 Data Transfer ............................................................................................................ 22-722.5 Programming Model ..................................................................................................... 22-7


xxii Freescale Semiconductor


Title PageNumber

22.5.1 QSPI Mode Register (QMR) .................................................................................... 22-822.5.2 QSPI Delay Register (QDLYR) ............................................................................. 22-1022.5.3 QSPI Wrap Register (QWR)................................................................................... 22-1122.5.4 QSPI Interrupt Register (QIR)................................................................................ 22-1222.5.5 QSPI Address Register (QAR) ............................................................................... 22-1322.5.6 QSPI Data Register (QDR)..................................................................................... 22-1322.5.7 Command RAM Registers (QCR0–QCR15).......................................................... 22-1322.5.8 Programming Example ........................................................................................... 22-15

Chapter 23 UART Modules

23.1 Overview....................................................................................................................... 23-123.2 Serial Module Overview............................................................................................... 23-223.3 Register Descriptions .................................................................................................... 23-223.3.1 UART Mode Registers 1 (UMR1n).......................................................................... 23-423.3.2 UART Mode Register 2 (UMR2n) ........................................................................... 23-623.3.3 UART Status Registers (USRn) ............................................................................... 23-723.3.4 UART Clock Select Registers (UCSRn) .................................................................. 23-823.3.5 UART Command Registers (UCRn) ........................................................................ 23-923.3.6 UART Receive Buffers (URBn)............................................................................. 23-1123.3.7 UART Transmit Buffers (UTBn) ........................................................................... 23-1123.3.8 UART Input Port Change Registers (UIPCRn)...................................................... 23-1223.3.9 UART Auxiliary Control Register (UACRn)......................................................... 23-1323.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn)..................................... 23-1323.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n) ..................................... 23-1423.3.12 UART Input Port Register (UIPn) .......................................................................... 23-1523.3.13 UART Output Port Command Registers (UOP1n/UOP0n) ................................... 23-1523.4 UART Module Signal Definitions .............................................................................. 23-1623.5 Operation .................................................................................................................... 23-1723.5.1 Transmitter/Receiver Clock Source........................................................................ 23-1723.5.1.1 Programmable Divider........................................................................................ 23-1723.5.1.2 Calculating Baud Rates....................................................................................... 23-1823.5.2 Transmitter and Receiver Operating Modes........................................................... 23-1923.5.2.1 Transmitter.......................................................................................................... 23-1923.5.2.2 Receiver .............................................................................................................. 23-2023.5.2.3 FIFO Stack.......................................................................................................... 23-2123.5.3 Looping Modes ....................................................................................................... 23-2223.5.3.1 Automatic Echo Mode........................................................................................ 23-2223.5.3.2 Local Loop-Back Mode...................................................................................... 23-2323.5.3.3 Remote Loop-Back Mode................................................................................... 23-23


Freescale Semiconductor xxiii


Title PageNumber

23.5.4 Multidrop Mode...................................................................................................... 23-2423.5.5 Bus Operation ......................................................................................................... 23-2523.5.5.1 Read Cycles ........................................................................................................ 23-2523.5.5.2 Write Cycles ....................................................................................................... 23-2523.5.6 Programming .......................................................................................................... 23-2523.5.6.1 Interrupt and DMA Request Initialization.......................................................... 23-2623.5.6.2 UART Module Initialization Sequence .............................................................. 23-27

Chapter 24 I2C Interface

24.1 Overview..............................

Date post:	31-Mar-2020
Category:	Documents
Upload:	others
View:	5 times
Download:	0 times

MCF5282 ColdFire Microcontroller User’s Manual Sheets/Freescale Semi... · 2005-02-03 · Clock...

Documents