Measuring Statistical Variations in Large Numbers of Nano-scale Quantum Devices at Low Temperatures

7/30/2019 Measuring Statistical Variations in Large Numbers of Nano-scale Quantum Devices at Low Temperatures

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Adam Esmail Part III Project May 2012

Measuring Statistical Variations in Large Numbers of

Nano-scale Quantum Devices at Low TemperaturesAdam Esmail

Supervisor: Prof. Charles Smith

Abstract

A quantum multiplexer circuit was designed in order to measure statistical variations inthe pinch-off voltage of 56 split-gate transistors at a temperature of 300 mK. The deviceswere fabricated on a GaAs/AlGaAs modulation-doped heterostructure wafer. The multiplexer

operation was optimised through preliminary tests in which the depletion gate width and typeof insulator used were varied. Polyimide was found to be the most suitable insulator. Twodevices were successfully fabricated and both shown a normal distribution of split gate pinch-off voltages: one device measured all 56 split-gate devices with a mean pinch-off voltage of0.7190 V ( = 0.0564 V), the other device measured 28 devices with a mean pinch-off voltageof 0.6837 V ( = 0.0547 V). This proves the concept that the multiplexer can be used measuremany devices on a single chip and perform statistical analyses on the attributes of nano-scalequantum devices efficiently. The next stage is to fabricate the device on a higher quality waferand optimise the experimental set-up such that quantised conductance can be observed, thusallowing us to measure the statistical variations of the width of the first quantised plateau andthe 0.7 structure.

1 Introduction

One of the simplest mesoscopic semiconductor devices is the quantum wire, consisting of a singlesplit gate [1]. These devices have been measured for the last 25 years, providing many interestingresults, such the quantisation of conductance through a 1D channel in integer steps of 2 e2/h. Despitethe large number of experiments which have been performed using quantum wires, there have beenvery few studies on the yield and reproducibility of such devices. Yang et al. were the first to attemptsuch studies: over 500 split-gate devices were fabricated, but only six devices could be fabricatedon a single microchip due to the limited number of contacts on a standard chip carrier [2]. Thismeant that a lot of time was spent on fabrication, cooling the samples down to low temperatures andmeasurements to get the data required for a statistical analysis.

The aim of this project is to overcome this limitation by fabricating a quantum multiplexer, adevice which will allow us to measure many more devices using the same number of contacts.This device can be used to measure a large sample of split-gate devices on a single microchip andstudy the statistical variations of certain characteristics such as the pinch-off voltage, width of thefirst conductance plateau and the 0.7 structure. Split-gate technology has many novel applications,including quantum computing [3], quantum dot fabrication [4] and metrology [5], and measuringthe statistical variations of a large number of split-gate devices will be the first practical test of thescalability of this technology in these contexts [6].

In section 2 of this report, I describe the background physics involved with the QuantumMultiplexer. The first part discusses quantum transport, including the manifestation of quantisedconductance and the second part describes the system in which this can be observed. In section3, I outline the methods to fabricate semiconductor devices and low-temperature measurement. In

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section 4, I present the results and discuss them. Finally, in section 5, I discuss possible avenues offurther work and conclude the findings of the project.

2 Background Theory

2.1 Quasi-One-Dimensional Electron Transport

2.1.1 Ballistic Transport

The conductance of a two dimensional electron gas (2DEG) in a system with dimensions larger thanthe electrons mean free path is best described using the Drude model, where electrons diffusethrough the system via many inelastic scattering events, due to electron-electron and electron-phonon interactions. Each inelastic scattering event causes the phase coherence of the electronwavefunction to break. The conductance (G) of a system of length L, and cross-sectional area Ais given by

G =A

L=

A

Lene =

Ae2ne

Lm

, (2.1)

where ne is the electron density, is the electron mobility, is the mean time between inelasticscattering events and m is the effective mass of the electron, which is inversely proportional to thecurvature of the electronic dispersion curves, (h2/me) (2E/k2)1.

In a one-dimensional system, provided that the constrained dimensions are comparable to theelectrons inelastic mean free path (also known as the phase breaking length), the electrons will travelthrough the device without inelastic scattering. This is known as ballistic transport. In this regime, thephase coherence of the electron wavefunction is preserved throughout transport. The phase breakinglength varies with temperature, and at sufficiently low temperatures it is on the order of 1 m for highquality Si or GaAs semiconductors.

In the ballistic 1D transport regime, the Drude model no longer applies and the conductance is

given by the Landauer formula as will be discussed in section 2.1.3.

2.1.2 The Quasi-1D System

To form a quasi-1D channel, a transverse confining potential V(y) is applied to an electron gas, whichis defined in the (x,y) plane. The electrons are now confined in the y and z-axes but are free to movein the x-direction. The dispersion relation, derived from Schrodingers equation, has the form

Ekx,l = E0,l +h2k2x2m

, l = 0, 1, ... (2.2)

This equation defines a series of 1D dispersion curves or subbands. Each subband is labelled

with an integer l and the energy at the bottom, or edge, of the lth subband is E0,l.The density of states of the lth 1D subband is given by

l(E) =dnldE

, (2.3)

where nl is the 1D carrier density (number of states per unit length) in the lth subband. For a

1D system of length L with periodic boundary conditions, the wavenumber kx is given by 2n/L,where n is an integer. Hence the k-space interval between states is kx = 2/L. Therefore, writingthe wave-function of the highest occupied state as k, the 1D carrier density per subband is

nl = 2 (2k/kx)

L =

2k

, (2.4)

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where the factor of 2 is included for the spin degeneracy of the electron system1. Rearranging andsubstituting equation 2.4, we have

nl =2

h

2m(E E0,l). (2.5)

Using equation 2.5, we then get the 1D density of states for a single subband,

l(E) =

2m

h(E E0,l)1/2. (2.6)

Each subband of a 1D system is an independent dynamically 1D system, and therefore the totaldensity of states of a 1D system is the sum of the density of states in each 1D subband. Hence thedensity of states of the whole system is

1D = l

l(E) = l,E0,lE

2m

h(E E0,l)1/2. (2.7)

Figure 2.1: Total 1D density of states as a function of energy, where the first four subbands areoccupied. Taken from ref. [7].

A plot of the 1D density of states for a square well is shown in Fig. 2.1. The density of statesshows a singularity at the subband edges (i.e. when E = E0,l), but in a real 1D system disorder and

temperature smear out the density of states, reducing these singularities to sharp peaks.In a truly one-dimensional system, the confining potential is infinitely narrow and therefore thesecond subband is infinitely higher than the first. However, real quantum wires have finite width,and are said to be quasi-one-dimenisional. If the temperature is low enough such that only thefirst subband is occupied (i.e. kBT E0,1), then the quantum wire can be considered to be a one-dimensional system [8].

2.1.3 Quantised Conductance

The formula for quantised conductance, given in equation (2.3), is formally derived using theLandauer-Buttiker formalism. For the sake of brevity the full derivation is not given in this report, but

1This is suitable for a GaAs system. For Si, this factor would be 4 due to the additional valley degeneracy, but in thisreport we are only considering GaAs systems.

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can be found in refs. [8, 9]. Let us first consider the case of a perfect quasi-1D conductor, where thereis no potential barrier between the source and drain reservoirs (i.e. perfect transmission through theconductor) and that current in each subband does not scatter into another. The total conductancethough such a device can be derived to be

G =

dI

dV = N

2e2

h , (2.8)where N is the number of occupied subbands. This implies that the conductance is quantised is

units of 2e2/h, assuming that the temperature is low enough such that the subbands are either fullytransmitted or not occupied at all. The factor of 2 is removed when a high magnetic field is applied,

breaking the spin degeneracy.The quantisation of conductance in a 1D system is a remarkable result, which arises from the

cancellation of energy dependent terms for the current through the system. The group velocity ofelectrons v E and the density of states (E) 1/E and as the current I v (E)eV, the twoterms cancel and the resistance (V/I) only depends on e and Plancks constant, h [1].

In experimentally-realised 1D wires, the quantised steps orplateaux are not perfectly sharp buthave a finite spread to them wider than the thermal energy or excitation voltage. Quantum wires areformed using a split-gate devices, which are not perfect 1D devices but have a confining potential inthe direction of transmission. This confining potential is a smoothly varying function of position (thisgives the overall electrostatic potential as V(x,y) rather than V(y)). Hence, we need the Landauerformalism to describe the conductance when the transmission probability is not exactly unity for allenergies.

Figure 2.2: A schematic diagram of a 1D constriction, denoting the chemical potentials of thereservoirs (s, d) and leads (A, B). Taken from ref. [8].

The original formalism, proposed by Landauer (1957), derived the conductance through thepotential barrier of a 1D device in terms of the probabilities of transmission, T and reflection, R.Assuming the device is connected to the reservoirs by perfect 1D leads, the conductance was shown

to beG =

2e2

h

T

R. (2.9)

The chemical potential used to calculate this value are those in the 1D leads, A and B, as shownin Fig. 2.2. In the case of perfect transmission (T = 1, R = 0), the conductance tends to infinity,which, for a perfect conductor with zero resistance, makes sense. However, in 1981 Economouand Soukoulis [10] calculated the conductance using the chemical potential of the source and drainreservoirs s and d to be

G =2e2

hT. (2.10)

This was a surprising result, showing that even for a perfect conductor the conduction is finite.

Imry identified this as a consequence of the contact resistances between each of the leads and thereservoirs [8, 11].

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2.1.4 Electrostatic Potential in a 1D System

Figure 2.5: A typical saddle-point potential.

In 1990, Buttiker [9] presented a method of calculating the conductance through a 1D system byapproximating the electrostatic potential V(x,y) of the bottleneck of the 1D constriction as a saddle-

point, which to second order is

V(x,y) = V0

1

2m2x x2 +

1

2m2yy2, (2.11)

where V0 is the potential at the saddle-point, and x and y describe the curvatures of thepotentials in the x and y directions, respectively. In the y direction, the confinement is parabolicand gives rise to 1D subbands with threshold energies

El = V0 + hy

l +

1

2

. (2.12)

Classically, we would expect that the subbands which have this threshold energy below the Fermilevel are fully transmitted (open) and those which have this energy above the Fermi level are perfectlyreflected (closed). It is quantum-mechanical tunnelling which allows for subbands to not be completely

open or closed, but have a probability of transmission Tl,m. This is calculated in ref. [12] and is givenby

Tl,m = lm1

1 + e l, (2.13)

where l and m denote the incident and outgoing subband, respectively, and l is the dimensionlessvariable expressed as

l =2(E El)

hx=

2

E hy

l + 12 V0

hx. (2.14)

Only transmission probabilities where l = m are non-zero, and because of the quadratic formof the saddle-point there is no subband mixing. The transmission probability is close to zero forE

E

l, and close to unity for E

E

l. The energy range over which T changes between these two

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Figure 2.3: Transmission probabilities Tnn for n = 0, 1, 2 and 3 and the total transmission probabilityT = n Tnn as a function of(E V0)/hx for the ratio y/x = 3. Taken from [9].

Figure 2.4: Total conductance as a function of(E

V0)/hx for different saddle-point potentials. The

ratio y/x is incremented fro 0 to 5 in steps of 0.25. Taken from [9].

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extremes is determined by x. The total conductance through the saddle point is simply the sum ofthe conductances of each subband:

G(E) =2e2

h l

Tl,l(E) (l = 0,1,2,3,..). (2.15)

Figure 2.3 shows a typical conductance trace through a saddle-point potential, distinguishingbetween the total conductance (T) and the conductance of each subband (T00, T11...). Figure 2.4 showshow this trace changes with the ratio y/x, which describes the degree of confinement. Well-defined conductance plateaux form ify/x 1, and the plateaux become more longer and flatteras this ratio increases [13].The saddle-point potential is accepted as a good approximate model for real quantum wires nearpinch-off and we should expect to see such quantisation when measuring the conductance of oursplit-gate devices at low temperatures.

2.2 Experimental Realisation of 1D Systems

2.2.1 The HEMT Structure

Figure 2.6: A schematic diagram of an MBE grown HEMT wafer. Taken from [14].

The material system of choice for the study of 1D devices is the GaAs/AlxGa1xAs modulation-doped heterostructure, more commonly referred to as the High Electron Mobility Transistor (HEMT).Figure 2.6 shows a schematic diagram of the HEMT wafer. Such HEMT wafers are grown byMolecular Beam Epitaxy (MBE).The band structure of the HEMT is shown on Fig. 2.7.The electrons originate from the Si-doped AlGaAs region at the top of the structure, and diffuse downthrough the structure and into the GaAs. However, at low temperatures, the difference in band gaps2

form a potential barrier, preventing the electrons from diffusing back into the AlGaAs. The ioniseddonors give rise to a large electric fields which trap the electrons at the heterostructure interface. Theresultant high charge density causes band bending (according to Poissons equation), which createsa triangular potential well at the interface. The electrons collect here to form a two-dimensionalelectron gas (2DEG).

The 2DEG is separated spatially from the donors by a spacer layer (hence the term modulation-doped), which reduces the electron-ion scattering and hence gives the material a higher mobility

2The mole fraction of Al x = 0.33 for Cavendish grown wafers, giving a band gap of 1.88 eV at 300 K. The band gap ofGaAs is 1.424 eV.

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Figure 2.7: A schematic diagram of the band structure of a typical HEMT device. Taken from [8].

than its non-modulation-doped counterpart [13]. Only 10% of the electrons from the donors reachthe 2DEG. The other 90% are absorbed by the large number of surface states present in GaAs, leavingthe surface negatively charged. This causes the Fermi level to be pinned near the middle of the bandgap if there is no gate bias.

A gate bias is applied via a surface (or top) gate fabricated onto the HEMT structure. Applyinga gate voltage changes the position of the conduction band relative to the Fermi level, which in turnaffects the shape of the band as spatial changes in the local charge density determine the bending ofthe bands. Applying a negative voltage will deplete electrons from the 2DEG in the potential well,and applying a sufficiently large negative voltage will deplete the channel completely. This is knownas the pinch-off gate voltage [15].

The form of the conduction band can be deduced given Poissons equation, the carrier density

and the applied gate voltage. Although it is possible to calculate the band structure accurately usingnumerical methods, an analytical method is shown in [15] where some simplifications have beenmade to give reasonably accurate estimates.

2.2.2 Split-gate Devices

Figure 2.8: A schematic diagram of a split-gate device fabricated on a HEMT structure. Applying anegative voltage to the split gate depletes electrons from the 2DEG underneath, leaving a narrowconstriction between the two electron reservoirs. Image generated by R. W. Faulks and takenfrom [13].

Quantum wires are experimentally realised by fabricating split-gate devices onto the HEMT structureusing electron-beam (e-beam) lithography. A narrow constriction is defined in the 2DEG by applyinga negative bias to the split-gate, depleting the region below of electrons. Electrons are confined in the

vertical direction by the band profile of the heterostructure, and in the transverse direction by theelectrostatic potential of the split-gate. A systematic diagram of a split-gate is shown in Fig. 2.8.

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Figure 2.9: (a) The conductance of a typical split-gate device as a function of split-gate voltage,measured at a temperature of 100 mK. The change of gradient of the conductance trace at i indicates

the definition of a 1D channel. (b) The same data, but corrected for series resistance. The arrowdenotes the 0.7 structure. Taken from [13].

To observe quantised conductance, transport must be ballistic, and hence dimensions of the split-gate must be comparable to the phase breaking length of electrons ( 1 m at temperatures 2K).Quantised conductance in such short split-gate devices was first seen in 1988 [16, 17]. The phase

breaking length is dependent on temperature, so we would expect the plateaux will be better resolvedat much lower temperatures. Figure 2.9(a) shows the conductance trace of a typical split-gate device.Initally as the gate voltage is swept negatively from 0 V, the conductance drops as the electronsare depleted underneath the split gate. At point i - the definition point - the 2DEG is sufficientlydepleted such that the constriction is to the order of the phase breaking length, defining the quasi-1Dchannel. As the gate voltage decreases further, the trace shows series of steps at increasingly lowerconductance values until pinch-off, where no more electrons flow through the channel. Figure 2.9(b)shows the same data but corrected for series resistance (as will be described in section 3.3.2) showingthat the quantisation of plateaux is indeed in units of 2e2/h [13].

2.2.3 The 0.7 Structure

In Fig. 2.9(b), the black arrow points at a conductance anomaly at around 0.7 (2e2/h) whichcommonly occurs for split gate devices. This is known as the 0.7 structure and cannot be explainedusing the simple model neglecting electron-electron interactions. It was so unexpected that for a longtim it was considered as an impurity effect. This structure was systematically studied by Thomas et

al. in 1996 [18]. There is no consensus as to its origin [19].As yet, there has been no large scale statistical study on the height of the 0.7 structure.

Experimental studies have shown that this anomaly does not always appear at 0.7 but falls withina range of conductances between (0.5 0.8) (2e2/h), with possible correlations with the 2DEGcarrier density. By measuring a high yield of quantum wires with the 0.7 structure present, we will

be able to perform a statistical analysis on its conductance position, giving further clues to the physicsbehind it.

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Figure 3.1: A schematic diagram of the quantum multiplexer. The gates and central ohmic contactsare labelled in the same manner as the labelling scheme for the standard chip carrier packages usedin the research group. The bottom ohmic contacts are labelled by the corresponding path numbers.

3 Methods

3.1 Operation of the Quantum Multiplexer

A schematic diagram of the multiplexer circuit is shown in Fig. 3.1. Eights outputs are controlled bysix gates, meaning that there are fewer voltage sources needed to control the multiplexer than eightsimple channels that could be turned on or off. This is especially desirable for complex devices asthere are a limited number of contacts on standard chip carriers.

The multiplexer works by splitting the conducting channel like a tree structure into eventuallyeight separate conducting paths. Stripe depletion gates3 are fabricated at each branching point ofthe conducting channel. By pinching off the 2DEG at certain points, the current from the sourceterminal (C1) is forced to flow down a single path, the other seven paths being cut off.

We can use one gate (e.g. A1) to cut off more than one branch (at points A and C). However, it

is necessary to run over an area of the channel which we do not want to cut off (i.e. point B in thiscase). We need to find a way of insulating this gate from the 2DEG at point B. The same argumentcan be made for all of the gates and these insulators are marked in red in Fig. 3.1.

We want there to be a sufficiently large difference in pinch-off voltage between the insulated anduninsulated gates (in the case of gate A1 points B and A, respectively) such that we can bias thegate to an intermediate voltage where the current is pinched off at A (and C) and not at B. Table 1shows which gates need to be turned ON or OFF in order to select single paths.

We will use this multiplexer to measure an array of split gates and this will be discussed in section3.3.2. It is estimated that the pinch-off voltage for the split gates will be around 2 to 3 V and it isnecessary for the voltage on the multiplexer addressing gates to be larger than this.

3

In this report, a depletion gate denotes a single stripe going over a single channel and a top gate denotes the entiremetallised area connecting the depletion gates to pads which can be bonded to.

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Addressing Gate L2 A1 B1 D1 E1 H1

Path 1 OFF OFF OFF ON ON ON

Path 2 ON OFF OFF ON ON OFF

Path 3 OFF ON OFF ON OFF ON

Path 4 ON ON OFF ON OFF OFF

Path 5 OFF OFF ON OFF ON ONPath 6 ON OFF ON OFF OFF ON

Path 7 OFF ON ON OFF OFF ON

Path 8 ON ON ON OFF OFF OFF

Table 1: A table showing which addressing gates need to be ON (i.e. to be applied with a sufficientnegative gate voltage such that uninsulated gates have pinched off but insulated ones have not) orOFF (no applied voltage) in order to select a path.

3.1.1 Tuning the Pinch-off of the Depletion Gates

Figure 3.2: The layout of the full test structure with insulator and screening gate.

There are various ways in which the depletion gates can be modified in order to (negatively) increasethe pinch-off. Three methods were investigated for the purposes of this report. By modelling the

potential of the 2DEG due to the depletion gate in each case, we can predict what method will providethe largest pinch-off difference. The stripe gate model used was constructed from the addition

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potential of two semi-infinite triangles, following a method described in refs. [20] and [21]. Usingthis model, the formula for the potential of a infinitely long stripe gate occupying |x| < a, due to anapplied gate voltage Vg is

(x, d) =Vg

arctan

a + x

d

+ arctana x

d , (3.1)

where d is the depth of the 2DEG.The pinch-off potential of a 2DEG has several components but can be estimated as the parallel-platecapactitor voltage to remove the charge density en2Dd/0. There is an additional contributionfrom the Fermi level, but this is very small for wafers with d > 25 nm and can be neglected [21].

The theoretical pinch-off voltage can be compared with experiment by fabricating test structureswhich we can measure the pinch-off voltage of the 2DEG as we change the parameters of thedepletion gate. An example of a test structure is shown in Fig. 3.2.

I. Decreasing the Stripe-gate Width Figure 3.5 shows the potential from stripe gates with 2a = 20,

5, 2 and 1 m. The gate voltage is chosen in this example to be -0.22 V, and the depth of the 2DEG forthe wafer of choice is 90 nm4. The estimated potential necessary to pinch-off the 2DEG is shown inorange (Vp = 0.2003 V): if the potential of the stripe gate reaches this orange line, then the channelwill begin to pinch-off. For a given gate voltage, the thinner gates have a smaller negative potentialat the centre than the thicker ones. This implies that the thinner gates need a more negative appliedgate voltage to pinch-off the channel.

Figure 3.3: A close up of the two channels of the test structure designed to measure pinch-off forvarying stripe gate width. This example compares a 20 m gate (left channel) and a 1 m gate (rightchannel).

II. Adding an Insulator Between the 2DEG and the Top Gates The distance between the 2DEGand the top gates can be physically increased by adding a layer of insulating material between them,in order to reduce the effect of the gate potential. This results in a shift in the pinch-off voltage:

Vp

en2Dd

0 en2Dt

0, (3.2)

where n2D is the carrier density, and t are the relative dielectric constant the thickness of theinsulator, respectively. Hence we aim to have a low- insulator. The thickness will depend on thefabrication process on the application of the insulator. Figure 3.6 shows a simulation of the effect ofthe pinch-off voltage with an insulator of typical thickness in comparison to a gate potential of 1 V.We will use SiO2 (= 3.9, t = 100 nm) and Polyimide (= 3.4, t 700 900 nm) and compare thepinch-off voltages in the experimental results.

4To be consistent with the wafer used in the experiment.

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Figure 3.4: A close up of the two channels of the test structure designed to measure pinch-off for agate with an insulator underneath (right channel).

Figure 3.7: A close up of the two channels of the test structure designed to measure pinch-off for agate with an screening gate underneath (right channel).

III. Adding a Screening Gate Between the 2DEG and the Insulator The gate potential can bescreened completely from the 2DEG by adding a screening gate - this is simply a metallised gate(fabricated similarly to the top gate, see section ??) that acts as to shield the gate potential. If thescreening gate is kept at ground, then in theory the channel should not pinch off. The insulator is stillrequired in order to separate the screening gate from the top gate.

3.2 Fabrication

The test structures and the multiplexer were fabricated on a W0091 HEMT wafer with carrier densityn2D = 1.6 1011cm2 and mobility = 9.023 105 cm2 V1 s1. The devices were mostly fabricatedusing optical lithography. Optical lithography cannot define features smaller than 1 m, so e-beamlithography was used to fabricate the split gates. For brevity, this report only includes the basicoutline of fabrication. Details of fabrication techniques can be founds in Refs. [13] and [8].

3.2.1 Optical Lithography

The following outlines the sequential steps in making the optically defined features.

1. To start with, a semiconductor wafer is cleaved into an appropriate sized chip to processing

which contains many devices which will be individually cleaved after fabrication.2. Etching a mesa: A mesa is a raised, electrically isolated region of the 2DEG and is the

conducting channel in the chip. The chip is coated with a polymer photoresist (using a spinnerto ensure an evenly spread coat) and is then exposed to UV light through a designed maskwhich in order to define the shape of the desired feature the mesa in this case on thechip. The mesa is etched, using sulphuric acid solution, to the depth of the 2DEG layer. Theremaining photoresist on the is removed with acetone.

3. Ohmic contacts: These electrically contact the 2DEG. The chip is coated with photoresist,exposed through the ohmic-contact mask pattern and developed. AuGeNi alloy is thenevaporated onto the chip surface under a high vacuum. Unwanted metal and photoresist are

then lifted off by soaking the chip in acetone. The chip is then thermally annealed so that themetal diffuses into the wafer such that it contacts the 2DEG.

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20 15 10 5 0 5 10 15 200.25

0.2

0.15

0.1

0.05

0

Potential across stripe gate, d = 90nm, Vg = 0.22V

x (m)

Potential(V)

20 m

5 m

2 m

1 m

Est. Pinchoff

Figure 3.5: The potential across different widths of stripe gate at gate voltage -0.22V. The pinch-offpotential for a 2DEG with carrier denisty n2D = 1.6 1011cm2 and depth d = 90 nm is calculated to

be Vp = 0.2003 V.

20 15 10 5 0 5 10 15 208

7

6

5

4

3

2

1

0

Potential across stripe gate, d = 90nm, Vg = 1V

x (m)

Potential(V)

Gate potential

Estimate pinchoff no insulatorEstimate pinchoff SiO

2100 nm

Estimate pinchoff Polyimide 800 nm

Figure 3.6: The potential across a 20 m stripe gate at gate voltage -0.22V in comparison with

theoretical pinch-off potentials. For SiO2: Vp = 0.9420 V. For polyimide: Vp = 7.0065 V.

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4. Screening gate (optional): The chip is coated with photoresist, exposed to UV light underthe appropriate mask, and developed. The gates are metallised (typically 20/60 nm Ti/Au)in a thermal evaporator at high vacuum. During evaporation, the chip is attached to aRotatilt mechanism, which continuously holds the chip at a chosen angle (typically 45) andcontinuously rotates, such that the walls of the mesa are also metallised, ensuring the metal is

continuous over the mesa. Unwanted metal and photoresist are then lifted off by soaking thechip in acetone.

5. Insulator (optional): Either the chip is coated with 100 nm of silicon dioxide (SiO2) by CVD5,

coated with photoresist, exposed through a mask and developed using HF6 or polyimideis spun on the chip, exposed through a mask and developed using a standard polyimidedeveloper. The thickness of the resulting polyimide ranges between 700 900 nm.

6. Top gate: Same as 4.

3.2.2 E-beam Lithography

A layer of PMMA resist is spun on the chip and the chip is baked. The gate pattern is then writtenin the PMMA using the electron beam and the pattern is developed using a standard developer.10/60 nm Ti/Au is metallised for a standard set of split gates. The gates must be continuous withoptically-defined gates. [13].

3.2.3 Bonding and Packaging Devices

Finally, the chip is divided into individual devices and are glued into chip carriers and the gate andohmic pads on the device are bonded to the twenty contacts on the carrier.

3.3 Low-temperature Two-terminal Measurement

Figure 3.8: The electrical circuit for a two-terminal, constant voltage measurement.

As discussed in section 2.1, it is necessary to perform measurements on these devices at lowtemperatures such that the electrons travel ballistically. The specific cooling methods for measuringthe test structures (4.2 K) and the multiplexer (300 mK) are described in sections 3.3.2 and 3.3.3,respectively.

In all devices, the two-terminal conductance of each device was measured using the circuit inFig. 3.8. In this circuit, the input voltage is divided by 104 to give a constant voltage, VB, acrossthe device. The current output, Is is amplified by a 10

7 gain current pre-amplifier. The capacitor isused to compensate for the input offset voltage of the current pre-amp. The output voltage from

5Chemical Vapour Deposition6Hydrofluoric Acid

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the pre-amp is then measured using a lock-in amplifier, which detects the signal given at a referencefrequency. This is usually 77 Hz, but any frequency away from the 50 Hz mains frequency andits harmonics is acceptable. A spectral analyser can be used to determine the frequencies with thelargest signal-to-noise ratio. The signal is then recorded using a measurement computer connectedvia a GPIB interface. Since VB is constant, the conductance is proportional to Is, plus a series resistance

contribution.

3.3.1 Series Resistance

The major contribution of the conductance measured in a two-terminal measurement is theconductance of the sample device, but there are other components in the circuit which are resistive,such as the wires, the 2DEG region, resistors in low-temperature filters and ohmic contacts. Inorder to work out the actual conductivity of the sample, Gs, we need to remove all these additionalresistances, which we assume to be in series with the 1D constriction. The sample conductance inunits of 2e2/h is estimated to be

Gs = ([1/gT

Rs]

77.27)1 , (3.3)

where gT is the measured conductance in S , and Rs is the series resistance contribution inM. The approximation of Rs that we will take is the inverse of the open-channel conductance(the conductance of the device at zero gate voltage) [13].

3.3.2 Measuring the Test Structures

All test structures were tested at 4.2 K, by mounting the chip on the end of a purpose-built probeand dipping the probe in a liquid 4He. The probe has 20 BNC sockets which are each connectedto one of the 20 contacts of the chip carrier. At the end of the probe, there is a LED which can beilluminated by passing a small current (5 mA) through it. This increases the carrier density of thedevice by releasing electrons trapped in DX centres (deep potential wells in the dopant region)which fill the 2DEG [15]. This is only needed for devices which have poor initial conductance asthere is a risk of initiating parallel conduction. This is where the Fermi level of the 2DEG is higherthan the Schottky barrier formed by the doped AlGaAs layer and electrons populate in this bandminimum and becomes a secondary conducting channel. This 2DEG is almost perfectly screenedfrom the 2DEG and needs a large negative gate voltage to deplete the donors. Care is taken to ensurethe devices are only illuminated for a short time (i.e. a few seconds) to reduce the risk of parallelconduction.

Five batches of test structures were tested on:

(i) Four devices tested to compare two depletion gates, one of width 20 m and one of width x m,where x = 20, 5, 2 and 1 m.

(ii) As (i), but the x m wide gate has SiO2 underneath the top gates to act as an insulator.

(iii) As (ii), but the x m wide gate has a screening fabricated underneath the SiO 2 insulator.

(iv) As (i), but the x m wide gate has polyimide underneath the top gates to act as an insulator.

(v) As (iv), but the x m wide gate has a screening gate fabricated underneath the polyimideinsulator.

Each test structure has four of these pairs of depletion gates, one on each side of the device ascan be seen in Fig. 3.2. The top gates in all the structures were checked for continuity and thescreening gates were tested for shorts by measuring their contact resistance using a multimeter. Once

we established the best way to insulate the depletion gates, we fabricated the multiplexer circuit withthe array of split-gate transistors.

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Figure 3.9: The mask design of the multiplexer with insulator and screening gate. The contacts arelabelled in the scheme of the standard chip carrier package used in the research group.

3.3.3 Using the Multiplexer to Measure Split Gates

The mask layout of the multiplexer (with insulator and screening gate) is shown in figure . Each ofthe metal contacts are labelled by a letter and number which indicates which bonding pad on thechip package the contact is connected to. This multiplexer can measure 56 split-gates arranged in a7 8 array. A single split-gate is measured by addressing a single row using the multiplexer, andmeasuring the conductance through a single column. The conductance through the split-gate is thencontrolled by applying a gate voltage via the top central contact (C1).

The multiplexer device is initially tested at 4.2 K in the 4He Dewar to check it operates as expected.The multiplexer has a testing channel between contacts J1 and J2, with depletion gates after eachpath of the multiplexer. By sweeping the multiplexer gates according to Table 1, the pinch-offcharacteristics of each of these depletion gates can be observed. It may be possible to deduce ifthe multiplexer is functioning as expected, if there are no pinch-off traces are exactly the same.

Quantised conductance is only observed in split-gate devices if the thermal energy (kBT) is lessthan the 1D subband spacing (typically 1 3 meV). Hence, the multiplexer was measured in a bathcryostat with a sorption pumped 3He Heliox system. The system operates by pumping out the smallvolume of vapour above the condensed 3He. This reduces the vapour pressure and hence lowers the

temperature. A base temperature of 300 mK is maintained for over 50 hours and is controlled by

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a temperature controller. It is important that the input voltage, VB, should be less or equal to thethermal energy, otherwise it will cause an undesired heating effect, which is especially problematicwhen trying to observe quantised plateaux. The Heliox system also has an LED in order to illuminatethe sample device if necessary.

The split gates can be addressed and measured efficiently by programming the computer to

address the multiplexer gates as given on Table 1 in between measurements of split-gates, keepingthe column channel fixed. This is repeated for the other six columns by measuring the conductanceacross the corresponding channels. This will give the conductance traces for all 56 devices, assumingthat they are all accessible and working and we can perform statistical analyses on pinch-offcharacteristics such as pinch-off voltage or height of the 0.7 structure.

4 Results and Discussion

4.1 Test Structures

4.1.1 Pinch-off Characteristics of Depletion Gates with Different Widths

0.25 0.2 0.15 0.1 0.05 00

100

200

300

400

500

600

700

800

900Varying Stripe Gate Width, Devices Not Illuminated

Gate Voltage (V)

G(

S)

20m

2m

0.5 0.4 0.3 0.2 0.1 00

200

400

600

800

1000

1200

1400

1600

1800

2000

2200Varying Stripe Gate Width, Devices Partially Illuminated

Gate Voltage (V)

G(

S)

20m5m

1m

Figure 4.1: The pinch-off traces for the four test structures with varying depletion gate width. All 20m depletion gates, regardless of the device, are shown in black.

Figures 4.1 (a) & (b) show the pinch-off traces of the depletion gates of varying width. Initially,poor conductance (< 100 S) was observed in the 5 and 1 m devices, and partly in the 20 m device.Therefore, hese devices were illuminated using the LED at the end of the probe. This increased the

conductance substantially and hence these traces have higher conductances (> 1000 S) at zero gatevoltage, and also have a larger pinch-off voltage, because under illumination the carrier density ofthe device increases. Data shown in Fig. 4.1(a) are from the devices which were not illuminated andFig. 4.1(b) are from the devics which were illuminated.The pinch-off were very similar between varying gate widths. This should not surprise us as thesimulation on Fig. 3.5 has a different of peak potential between the 20m and the 1m gates of 0.03V. This is smaller than the statistical variation of the pinch-off voltages for a given gate width, andhence no correlation between pinch-off voltage and gate width was observed.

Under SEM, the gates were actually observed to be 1 m larger than expected (see Fig. 4.2).This is a systematic error due to the fabrication process and may give an additional reason why littledifference in pinch-off voltage was observed. It can be possible to try gates of width smaller than 1

m, although this would require the use of e-beam lithography and would be more time-consumingand expensive to fabricate.

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Figure 4.2: An SEM of the 5 m stripe depletion gate, which is actually measured to be 6.02 m atits centre.

4.1.2 Comparing SiO2 and Polyimide as Gate Insulators

3.5 3 2.5 2 1.5 1 0.5 00

200

400

600

800

1000

1200

SiO2

Devices

Gate Voltage (V)

G(

S)

20m normal20m SiO

2

5m SiO2

2m SiO2

1m SiO2

8 7 6 5 4 3 2 1 00

100

200

300

400

500

600

700

800

900

1000

Polyimide Devices

Gate Voltage (V)

G(

S)

20m normal

20m Poly5m Poly

2m Poly

1m Poly

Figure 4.3: (a) Pinch-off traces with of the four test structures with varying depletion gate width andSiO2 as a gate insulator. (b) Pinch-off traces with of the four test structures with varying depletiongate width and Polyimide as a gate insulator. These were compared to gates with no insulator (shownin black).

Figures 4.3 (a) and (b) show the pinch-off traces of the depletion gates where SiO 2 and polyimide,

respectively, were used as a gate insulator.

Gates insulated using SiO2 These showed a much more negative pinch-off voltage (between 2and 2.6 V) than the uninsulated gates. This is larger than the theoretical pinch-off voltage of0.9420V, but this is expected as all of these devices were illuminated due to poor conductances. Three outof 16 top gates were discontinuous, and the conductance of many of the channels was very low, evenafter illumination. The low conductivity may have been due to a thermal spike during the annealingprocess which degraded the quality of the ohmic contacts.

Gates insulated using Polyimide These devices showed an even larger difference in pinch-off

voltage between the insulated and uninsulated gates, with values reaching between 5.9 and 7.76V. There was only one anomalous result with the 1 m device where the channel pinched off at 1.71

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V. All gates were continuous and the conductances were all sufficiently high such that illuminationwas not necessary. The theoretical pinch-off voltage of7.0065 V is consistent with these results.

4.1.3 Adding a Screening Gate

5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0100

0

100

200

300

400

500

600

700

800

SiO2

+ Screening Gate Devices

Gate Voltage (V)

G(

S)

20m normal20m SiO

2+SG

5m SiO2+SG

2m SiO2+SG

1m SiO2+SG

10 9 8 7 6 5 4 3 2 1 00

100

200

300

400

500

600

700

800

900

1000

Polyimide + Screening Gate Devices

Gate Voltage (V)

G(

S)

20m normal

20m Poly+SG

5m Poly+SG

2m Poly+SG

1m Poly+SG

Figure 4.4: (Pinch-off traces with of the four test structures with varying depletion gate width witha screening gate and (a) SiO2 or (b) Polyimide as an insulator.These were compared to gates with noinsulator or screening gate (shown in black).

Figures 4.4 (a) and (b) show the pinch-off traces of the depletion gates where a screening gate wasused, and an insulator (SiO2 in (a), polyimide in (b)) was placed in between the screening gate andtop gate.

SiO2 with screening gate Half of the depletion gates behaved as expected, although there wereproblems with gate continuity and short circuits. Three out of the 16 top gates were discontinuous,and there were eight cases (out of 16) in which the screening gate was shorted to the top gate, whichprevented pinch off when the unscreened top gate was swept. Three of these are shown in Fig. 4.4(a)

by the three flat black lines (one in the 2 m device, two in the 5 m device). The 5 m device behavedoddly on the whole, as the screened gates (shown in red) behaved as if they should be unscreenedand vice versa. The low yield of working gates implies that the use of SiO2 would be unsuitable forthe multiplexer with a screening gate.

Polyimide with screening gate These devices proved to be more reliable with no gate shorts ordiscontinuities. For the 5, 2 and 1 m devices, the channels did not pinch-off before 10 V. The onlyanomaly was the 20 m device, where three of the four channels pinched off before 10 V.

After these experiments, it was decided that the best course of action was to fabricate multiplexerdevices with polyimide as the gate insulator. Two multiplexers without a screening gate (codenamedMux1 and Mux2) and two with a screening gate (MuxSG1 and MuxSG2) were sucessfullyfabricated, bonded and packaged ready to test. An optical micrograph of Mux1 is shown in Fig. 4.5.An SEM7 image of one of the split gates split gates is shown in Fig. 4.6(b).

7Scanning Electron Microscopy

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Figure 4.5: Optical Micrograph of multiplexer device without a screening gate (Mux1). Themultiplexer circuit is connected to a 7 8 array of split gate devices. The size of the device is 2.4mm 2.4 mm.

Figure 4.6: (a) A close up of the optical micrograph in Fig. 4.5 of a single split gate, marked in red. (b)

An SEM image of such a split gate. The split gate has length 0.4 m and width 0.5 m.

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4.2 The Multiplexer

Before any tests were carried out, the resistances of all the gate and ohmic contacts were measured toensure that there were no shorts or unusually high resistances. Mux1 appeared to have no shortsor discontinuities, but one of the top gates on Mux2 (H1) appeared to be shorting to something.Without the use of this addressing gate, it is not possible to individually select certain paths in which

H1 requires to be on. Hence, the only split-gates that can be measured with this multiplexer arethose which can only be addressed with L2 ON and H1 OFF (corresponding to even number paths,see Table 1).

4.2.1 Preliminary Tests

0.14 0.12 0.1 0.08 0.06 0.04 0.02 00

5

10

15

20

25

30

35

40

45

50

Mux Conductance J1J2, dipped at 4K

Gate Voltage (V)

G(

S)

Path 1

Path 2

Path 3

Path 4

Path 5

Path 6

Path 7

Path 8

0.11 0.1 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.010

5

10

15

20

25

30

Mux2 Conductance J1J2, T = 300mK

Gate Voltage (V)

G(

S)

Path 1

Path 2

Path 3

Path 4

Path 5

Path 6

Path 7

Path 8

Figure 4.7: The pinch-off traces for the conductivity of the testing channel J1J2 as a function of thegate voltage at C1. Above: Mux1 at 4.2 K. Below: Mux2 at 300 mK.

Multiplexers without a screening gate The two multiplexer devices fabricated without a screeninggate worked as expected. For Mux1 at least, the observation of different pinch-off traces isreassuring that the eight different paths are being addressed separately, since if the traces were thesame this might indicate the same depletion gate is operating each time.

In order to determine whether the multiplexer works as expected, a third type of multiplexerdevice was bonded; this time the bonds were connected to the end of the multiplexer rather thanthe ends of the columns of the split-gate array. The conductances were measured to make sure thatthe gate voltages applied to the addressing gates resulted in the correct path being chosen. The

multiplexer worked as expected and the results are presented in appendix A.

Multiplexers with a screening gate The two multiplexer devices fabricated with a screening gatedid not work well. The conductances measured when no path of the multiplexer was addressed werevery low ( 100 S). When any one of the paths were addressed by applying the appropriate gatevoltages, the conductance in all the channels dropped to zero, without any voltage applied to the gateC1. After turning off all the gates, the conductance of the channel remained zero until the BNC cablesconnected to the probe were removed and replaced. This implies that the charge becomes trapped inthe multiplexer structure somewhere, possibly at the screening gate. We decided that these deviceswere faulty and did not test them any further.

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4.2.2 Measuring Split-gate Pinch-off

0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 00

100

200

300

400

500

600

Mux1 Conductance All Devices, T=300mK

Gate Voltage (V)

G(

S)

Path 1

Path 2

Path 3

Path 4

Path 5

Path 6

Path 7

Path 8

Figure 4.8: The conductance of 55 out of 56 split gate devices as a function of gate voltage measuredin Multiplexer 1 at 300 mK in a 3He cryostat. One result showed an anomalously large pinch offat

1.5 V, and is not shown here. The colours indicate which path was selected. The split-gate row

which corresponds to the addressed path is denoted in Table 1.

Mux1 worked extremely well. Figure 4.8 shows the pinch-off of the split gate according to thepath that was selected. All split gates pinched off in the region 0.5 to 0.8 V, with the exceptionof one (Path 3, B2K1) which pinched off at 1.48 V. Some of the channels had relatively very lowconductances; this is most likely due to certain ohmic contacts in poor contact with the 2DEGunderneath, which may be due to thermal fluctuations during the annealing process. Figure 4.9shows the same data as Fig. 4.8, except the colour now denotes the column (i.e. the conductivechannel to K1) that was selected. For the low conductance channels (< 100 S) the condutancedecreases in the order F2K1, E2K1, D2K1 and C2K1. This corresponds to going from right to left atthe bottom of the device as seen in Fig. 4.5. This could be due to temperature gradients across the

device during annealing or local variations in carrier density. Mux2 also worked well, with all ofthe 28 split gates that could be measured, considering the gate short, pinching off. The conductancetraces for Mux2 can be found in appendix B.1.

Disappointingly, none of the traces showed well-resolved quantised plateaux, which we wouldcertainly have expected to see at 300 mK. This may imply some heating effect of electrons, perhapsfrom unwanted RF signals coupling to the excitation. The traces were corrected for series resistanceand were replotted (Fig. 4.10), but no plateaux emerged.

The maximum conductance measured was 600 S, which is lower than the expected conductance(1500 2000 S) for the type of wafer used in the experiment. Such low conductances may be anadditional reason why quantised plateaux cannot be resolved, as the conductance difference betweensubbands would be very small. We therefore attempted to increase the conductance by illuminating

device Mux1 (as described in section 3.3.2).After illuminating Mux1 for only 1 second, it was found that the pinch-off voltages for the

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0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 00

100

200

300

400

500

600

Mux1 Conductance All Devices, T=300mK

Gate Voltage (V)

G(

S)

A2K1

B2K1

C2K1

D2K1

E2K1

F2K1

L1K1

Figure 4.9: The same data as in Fig. 4.8 but with the traces coloured by which column conductingchannel was selected, rather than the path of the multiplexer which selects the row.

0.9 0.85 0.8 0.75 0.7 0.65 0.6 0.55 0.50

0.5

1

1.5

2

2.5

3

3.5

4

4.5 Mux1 Conductance All Devices with Correction, T=300mK

Gate Voltage (V)

G(

2e

2/h)

Path 1

Path 2

Path 3

Path 4

Path 5

Path 6

Path 7

Path 8

Figure 4.10: The same data as in Fig. 4.8 corrected for series resistance.

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Device N(in total) (V) (V) N(within fit)

Mux 1 56 -0.7190 0.0564 55

Mux 2 28 -0.6837 0.0547 27

Table 2: The mean and standard deviations of the distribution of split gate pinch-off voltages for bothMultiplexer devices, assuming a normal distribution in both cases.

split-gates reached -8.5V. This was unexpected: such brief illumination should only shift the pinch-off voltage by a maximum of a few volts [22]. With such a large shift in pinch-off voltage, it wasnecessary to experimentally verify, with one of the test structures, how much the pinch-off voltageincreases on illumination of the device. On illumination, the pinch-off voltage of the depletion gates

becomes more negative from 6 V to less than 10 V (see appendix B.2). This reassured us thatthe multiplexer was still accessing a single a split-gate at the point where the current pinched off.However, there is still the possibility that there may have been parallel conduction paths through thesurface states of the wafer, which has not been ruled out especially as the wafer is of poor quality. Itwas concluded that any results from the multiplexer after illumination were invalid.

4.2.3 Statistical Analysis of Split gates

Figure 4.11 shows a histogram showing the statistical distribution of pinch-off voltages measuredusing the Mux1 device, excluding the one statistical outlier. This is what we would expect,considering that the error in the fabrication of the split-gates (in length, width, roughness of theedges) is random. Figure 4.12 shows a histogram of the pinch-off voltages measured in Mux2.This is not a clear normal distribution as only 28 split-gates could be measured, with 27 falling inthe calculated distribution. The mean and standard deviations of these distributions are denoted inTable 2. We can qualitatively test the normal fit of both distributions by plotting a normal probabilityplot. This plots the data against the theoretical normal distribution in such a way that the points

should follow a straight line. Points which deviate from this line indicate deviations from the normaldistribution. It is found that for both multiplexers, most points closely follow near the theoreticalline, but deviate near the end of the distribution. These deviations are more pronounced for Mux2,indicative of the smaller sample set that was be measured [23]. These plots are shown in appendix C.

These distributions demonstrate that the multiplexer can be used to measure the statisticalvariations of a large array of quantum nano-devices on a single chip.

4.2.4 Correlations Between the Pinch-off Voltage and Definition Point

Another characteristic that was investigated was the position of the definition point of the 1D channel(point i in Fig. 2.9(b)) relative to its pinch-off voltage. We would expect these to be correlated with

each other if all of the split-gates were identical in dimensions, quality and background potential.The number of 1D subbands between pinch-off and definition is dependent on the dimensions of thesaddle-point potential, and hence dependent on the dimensions of the split-gate. Considering thata range of pinch-off voltage was observed, a correlation between pinch-off and definition point mayindicate that there is a variation in carrier density across the device [24].

Figure 4.13 shows a scatter plot of the definition point of each trace versus its pinch-off voltage.Traces which had low initial conductance were very noisy and it was difficult to judge the positionof the definition point precisely. It can be clearly seen that there is no correlation between these twovariables and hence the change in pinch-off voltages are caused by the variations in backgroundpotential and dimensions of split gate and roughness of edges.

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0.9 0.85 0.8 0.75 0.7 0.65 0.6 0.550

2

4

6

8

10

12Distribution of Split Gate Pinchoff Voltages0X[

Pinchoff Voltage (V)

No.ofMeasurements

Figure 4.11: A histogram of the measured pinch off voltages of 55 split gate devices in Mux1. Thedistribution is approximately normal: = 0.7190 V, = 0.0564 V. The normal fit is shown in red.The outlier at Vp = 1.5 V is not included.

0.8 0.7 0.6 0.50

1

2

3

4

5

6Distribution of Even Split Gate Pinchoff Voltages, Mux2


No

.ofMeasurements

Figure 4.12: A histogram of the measured pinch off voltages of 28 split gate devices in Mux2

that could be accessed individually. The distribution is approximately normal: = 0.7190 V,= 0.0564 V. The normal fit is shown in red.

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0.9 0.85 0.8 0.75 0.7 0.65 0.60.21

0.2

0.19

0.18

0.17

0.16

0.15

Definition Point vs Pinchoff


DefinitionPoint

A2K1

B2K1

C2K1

D2K1E2K1

F2K1

L1K1

Figure 4.13: Scatter plot showing the relationship between the definition and the pinch-off voltage ofthe split-gates in Mux1. There is no distinct correlation in any of the channels.

5 Further Work and Conclusions

5.1 Future Work

The next stage in the Quantum Multiplexer programme is to fabricate the devices on a higher qualitywafer, as the conductance should be sufficiently high enough such that a low input voltage can beused without illuminating the devices. It may also be possible that the split gates needed to be longerin order to increase the degree of confinement and get better defined quantised plateau. A possibleway to test this is to systematically examine the effect of split-gate dimensions on quantisation bymaking a device with the array of split gates of varying length (or width). Obtaining well-definedquantised plateaux will allow us to measure the variations in the width of the first plateau and theheight of the 0.7 structure, the latter being useful in investigating its physical origin.

It is also important to test the scalability of the multiplexer. A new device has been planned which,

by using two multiplexer structures, can address and measure 256 split gates (in a 16 16 array, seeappendix D). Sixteen gates are required to address the multiplexer to give a total of 32 outputs, whichscales the number of inputs to outputs more efficiently then the device discussed in this report. Thiswill give more data allowing more reliable statistical analysis of split-gate characteristics.

Large-scale arrays can provide more information than simply measuring the statistical variationsof the split-gate transistors. Impurities in split-gate devices cause resonance peaks in the conductanceplateaux [8]. By measuring the conductance of each split-gate, we can determine the proportion ofsplit-gates which contain an impurity and can determine the quality of the HEMT wafer that thedevice was fabricated on.

The multiplexer may also have a potential application to quantum computing. A recentexperiment involved coupling two pairs of adjacent quantum dots with two readout detectors. This

required twenty wires, which is at the limit of what can be integrated with most low temperaturesystems [25]. The addition of any more wires when placed down a low temperature cryostat would

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lead to unacceptable heat loads. We can overcome this by taking advantage of the scalability of themultiplexer, and it is possible to measure an array of such devices and demonstrate that a high yieldcan be achieved [6].

5.2 Conclusions

It has been shown that a multiplexer device can be used to measure a large array of split-gatedevices on a single microchip. Two such devices, which were fabricated and tested successfully,were used to investigate the statistical variations in pinch-off voltages of split gates. One devicecould measure the whole array of its devices and the distribution of pinch-off voltages appeared to

be a good normal fit. The other device could be used to measure only half of its devices due to a gateshort, and the distribution was approximately normal. Preliminary tests were carried out to optimisethe multiplexer operation by maximising the difference in pinch-off voltages between insulated anduninsulated depletion gates. It was concluded polyimide was a suitable insulator as this provideda sufficiently large difference and high yield. Correlations between the pinch-off voltage and thedefinition point of the 1D channel were not observed, indicating that the statistical spread in pinch-

off was due to variations in the lithography of the split gates.Quantised conductance in the split-gate devices were not observed which may be due tounwanted noise in the experimental set-up. The devices also had poor conductance which wasdue to poorly fabricated ohmic contacts. These problems will need to be addressed if we wish tomeasure statistical variations of other characteristics, such as the width of the first plateau and the0.7 structure.

Overall, this project has shown that the multiplexer is a key tool in performing detailedstatistical analyses of large numbers of quantum nano-devices, which is a major multiplication ofthe effectiveness of research in solid state physics and electronic device engineering [6].

Acknowledgements

I wish to thank Dr Luke Smith, Haider Al-Taie for designing and fabricating the devices, taking theoptical and SEM images and for their education and support. I also wish to thank Prof. CharlesSmith and the rest of the Semiconductor Physics group, Cavendish Laboratory for the use of theirlab, education and support.

References

[1] Berggren, K. and Pepper, M. Physics World , 3742 October (2002).

[2] Yang, Q., Kelly, M., and Farrer, I. Applied Physics . . . (2009).

[3] Hanson, R. et al. Phys. Rev. Lett. 94, 196802 (2005).

[4] Kouwenhoven, L. P. et al. Z. Phys. B. 85(3), 367373 (1991).

[5] Kouwenhoven, L. P. et al. Phys. Rev. Lett. 67, 16261629 (1991).

[6] Kelly, M. J., Ritchie, D. A., Smith, C. G., and Jones, G. A. C. Quantum Multiplexer: EPSRC GrantProposal. (2011).

[7] Beenakker, C. W. J. and van Houten, H. arXiv.org cond-mat, /0412664v1 December (2004).

[8] Graham, A. C. Many-body Interactions in Quantum Wires. PhD thesis, University of Cambridge,December (2006).

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[9] Buttiker, M. Physical Review B 41(11), 79067909 (1990).

[10] Economou, E. N. and Soukoulis, C. M. Phys. Rev. Lett. 46, 618 (1981).

[11] Smith, C. Reports on Progress in Physics (1996).

[12] Miller, W. H. Journal of Chemical Physics 48(1651) (1968).

[13] Smith, L. W. Electron Interaction Effects in Quasi-One-Dimensional Quantum Wires. PhD thesis,University of Cambridge, January (2012).

[14] Kishen, K. Electron Transport in Composite One-Dimensional Semiconductor Devices. PhD thesis,University of Cambridge, November (2006).

[15] Davies, J. H. The Physics of Low-Dimensional Semiconductors: An Introduction. CUP, 1st edition,(1998).

[16] Wharam, D. et al. J. Phys. C. 21, L209L214 (1988).

[17] Van Wees, B. et al. Phys. Rev. Lett. 60(9), 848850 (1988).

[18] Thomas, K., Nicholls, J., Simmons, M., Pepper, M., Mace, D., and Ritchie, D. Physical ReviewLetters 77(1), 135138 (1996).

[19] Micolich, A. P. Journal of Physics: Condensed Matter 23(44), 443201 October (2011).

[20] Thorn, A. L. Electron dynamics in surface acoustic wave devices. PhD thesis, University ofCambridge, March (2007).

[21] Davies, J. H. et al. J. Appl. Phys. 77, 4504 (1995).

[22] Smith, L. W. Private Communication.

[23] Chambers, J. M. et al. Graphical Methods for Data Analysis. Wadsworth, (1983).

[24] Smith, C. G. Private Communication.

[25] Perez-Martinez, F. et al. Appl. Phys. Lett. 91, 032102 (2007).

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A Testing the Output of the Multiplexer Circuit

Figure A.1: A schematic diagram of the multiplexer device bonded to test its opertature. The gatesand central ohmic contacts are labelled in the same manner as the labelling scheme for the standardchip carrier packages used in the research group. There were two detected shorts between the bondsconnected to the bottom contacts of the multiplexer.

Applied 1 V to multiplexer addressing gates and 0.5 V to C1:

Voltage on Contact H2 F2 E2 C2 B2 A2 L1 K1Corresponding Path 1 (V) 2 (V) 3 (V) 4 (V) 5 (V) 6 (V) 7 (V) 8 (V)

Addressed Path 1 -0.150 0 0 0 0 0 -0.150 0

Addressed Path 2 0 -0.333 -0.333 0 0 0 0 0

Addressed Path 3 0 -0.333 -0.333 0 0 0 0 0

Addressed Path 4 0 0 0 -0.333 0 0 0 0

Addressed Path 5 0 0 0 0 -0.340 0 0 0

Addressed Path 6 0 0 0 0 0 -0.338 0 0

Addressed Path 7 -0.337 0 0 0 0 0 -0.337 0

Addressed Path 8 0 0 0 0 0 0 0 -0.341

Table 3: A table showing the voltages measured on each contact when each path was addressed.Taking the short circuits into consideration, this is how we expect the multiplexer to operate.

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B Other Data

B.1 Multiplexer 2

0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 00

20

40

60

80

100

120

140

160

Mux2 Conductance Even Path Devices, T=300mK

Gate Voltage (V)

G(

S)

Path 2

Path 4

Path 6

Path 8

Figure B.1: The conductance of 28 split gate devices as a function of gate voltage measured inMultiplexer 1 at 300 mK in a 3He cryostat. The other 28 split gates could not be addressed dueto a fault with one of the addressing gates. The colour of the trace indicates which path was selected.

B.2 The Effect of Partial Illumination on a Polyimide-insulated Depletion Gate

10 9 8 7 6 5 4 3 2 1 00

200

400

600

800

1000

1200

1400

1600

Poly 20 Test Structure Device, Before and After Partial Il lumination

Gate Voltage (V)

G(

S)

20m normal, before illumination

20m Poly, before illumination

20m normal, after illumination

20m Poly, after illumination

Figure B.2: The effect of partial illumination (5 mA, > 1 s) on the pinch-off voltage of a channelcontaining a polyimide insulated depletion gate. The polyimide gate pinch-off voltages shifts from

6 V to a value less than 10 V, whereas the uninsulated gate pinch-off voltage changes very little.

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C Normal Probability Plots

Figure C.1: a) Normal probability plot of Mux1. b) Normal probability plot of Mux2. Thecurvature at both ends show that these data have a distribution is longer-tailed than a normaldistribution [23].

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D 256 split-gate multiplexer

This image has been omitted in this public file.

Figure D.1: A preliminary design for the 256 split-gate multiplexer. There are a total of sixteen

addressing gates (blue) which address two multiplexers. These both select the row and column ofthe array. The insulator is marked in red and the screenin gate in yellow. Designed by Dr Luke Smithand Haider Al-Taie.

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Measuring Statistical Variations in Large Numbers of Nano-scale Quantum Devices at Low Temperatures

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