Mech Lab Manual

Sathyabama University Department of ETCE

SATHYABAMA UNIVERSITY (Established under section 3 of UGC Act, 1956)

Jeppiaar Nagar, Rajiv Gandhi Salai, Chennai 600119, Tamilnadu. INDIA.

DEPT. OF ELECTRONICS AND TELECOMMUNICATION ENGG.

LAB MANUAL

ELECTRONICS AND MICROPROCESSOR LABORATORY

SECX4014

B.E. Mechanical Engg.

II YEAR (III SEMESTER)

JUNE 2011


ELECTRONICS & MICROPROCESSOR LABORATORY LIST OF EXPERIMENTS 100 Marks ELECTRONICS LAB

1. Study of Logic gates 2. Half and Full adder/Subtractor 3. Grey code converter 4. Ripple counters and Mod-N counters 5. Encoders and Decoders 6. Multiplexers and Demultiplexers

MICROPROCESSOR AND MICROCONTROLLER LAB I. 8085 Programming 1. Programs based on arithmetic operations

a. Addition b. Subtraction c. Multiplication d. Division.

2. Programs based on Sorting a. Ascending order b. Descending order

3. Interfacing of Stepper motor 4. Interfacing ADC and DAC 5. Interfacing Traffic Light Control

II. 8051 Programming 6. Programs based on arithmetic operations

a. Addition b. Subtraction c. Multiplication d. Division.

7. Programs based on Sorting a. Ascending order b. Descending order

8. Interfacing of Stepper motor 9. Interfacing Traffic Light Control


ELECTRONICS LAB 1. VERIFICATION OF LOGIC GATES (STUDY) AIM:

To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:

THEORY: Circuit that takes the logical decision and the process are called logic

gates. Each gate has one or more input and only one output.

OR, AND and NOT are basic gates. NAND, NOR are known as universal gates. Basic gates form these gates.

AND GATE:

The AND gate performs a logical multiplication commonly known as

AND

function. The output is high when both the input are high. The output is low level when any one of the input is low.

OR GATE:

The OR gate performs a logical addition commonly known as OR function. The output is high when any one of the input is high. The output is low level when both the input are low.

SL No. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1

2. OR GATE IC 7432 1

3. NOT GATE IC 7404 1

4. NAND GATE IC 7400 1

5. NOR GATE IC 7402 1

6. X-OR GATE IC 7486 1


NOT GATE: The NOT gate is called an inverter. The output is high when the input is low. The output is low when the input is high. NAND GATE:

The NAND gate is a contraction of AND-NOT. The output is high when

both input are low and any one of the input is low .The output is low level when both

input are high.

NOR GATE:

The NOR gate is a contraction of OR-NOT. The output is high when both input

are low. The output is low when one or both input are high.

EX-OR GATE: The output is high when any one of the input is high. The output is

low

when both the input are low and both the input are high.

PROCEDURE:

(i) Connections are given using PATCH CORDS as per circuit

diagram.

(ii) Logical input are given through TOGGLE SWITCHES as per

circuit diagram.

(iii) Observe the output USING LED’s and verify the truth table.

DIAGRAM :

AND GATE:

SYMBOL:


LOGIC DIAGRAM :

TRUTH TABLE :

OR GATE:

SYMBOL:

LOGIC DIAGRAM :


TRUTH TABLE :

NOT GATE:

SYMBOL:

LOGIC DIAGRAM :

TRUTH TABLE :

NAND GATE:

SYMBOL:


LOGIC DIAGRAM :

TRUTH TABLE :

NOR GATE:

SYMBOL:

LOGIC DIAGRAM :

TRUTH TABLE :


EX-OR GATE:

SYMBOL:

LOGIC DIAGRAM :

TRUTH TABLE :

RESULT:

Logic gates are studied and their truth tables are verified.


2.. [a] HALF ADDER AND FULL ADDER

AIM:

To construct verify the truth table of half adder and full adder circuits and

using logic gates.

APPARATUS REQUIRED:

Sl. No. COMPONENTS SPECIFICATION QTY. 1. AND GATE IC 7408 1 2. X-OR GATE IC 7486 1 3. OR GATE IC 7432 1

THEORY:

HALF ADDER:

A half adder has two input for the two bits to be added and two

output one from the sum ‘ S’ and other from the carry ‘ c’ into the higher adder

position. Above circuit is called as a carry signal from the addition of the less

significant bits sum from the X-OR Gate the carry out from the AND gate.

FULL ADDER:

A full adder is a combinational circuit that forms the arithmetic sum

of input; it consists of three input and two output. A full adder is useful to add

three bits at a time but a half adder cannot do so. In full adder sum output will be

taken from X-OR Gate, carry output will be taken from OR Gate.

PROCEDURE:

(i) Connections are given using PATCH CORDS as per circuit diagram.

(ii) Logical input are given through TOGGLE SWITCHES as per circuit diagram.

(iii) Observe the output USING LED’s and verify the truth table. LOGIC DIAGRAM:


HALF ADDER:

TRUTH TABLE:

INPUT OUTPUT

A B SUM (S) CARRY (C)

0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1

FULL ADDER:

FULL ADDER USING TWO HALF ADDERS


TRUTH TABLE:

INPUT OUTPUT

A B C SUM (S) CARRY (C)

0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

SUM = ABC+ABC+ABC+ABC CARRY = AB + BC + AC

RESULT:

Half adder and Full adder circuits are constructed and their truth tables are verified.

[b] HALF SUBTRACTOR AND FULL SUBTRACTOR

AIM:

To construct and verify the truth table of half subtractor and full subtractor

circuits using logic gates.

APPARATUS REQUIRED:

Sl. No. COMPONENTS SPECIFICATION QTY. 1. AND GATE IC 7408 1 2. X-OR GATE IC 7486 1 3. NOT GATE IC 7404 1 4. OR GATE IC 7432 1

THEORY:

HALF SUBTRACTOR:


The half subtractor is constructed using X-OR and AND Gate. The half

subtractor has two input and two output. The output are difference and borrow.

The difference can be applied using X-OR Gate, borrow output can be

implemented using an AND Gate and an inverter.

FULL SUBTRACTOR:

The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full

subtractor the logic circuit should have three input and two output. The two half

subtractor put together gives a full subtractor .The first half subtractor will be C

and A B. The output will be difference output of full subtractor. The expression

AB assembles the borrow output of the half subtractor and the second term is

the inverted difference output of first X-OR.

PROCEDURE: (i) Connections are given using PATCH CORDS as per circuit

diagram. (ii) Logical input is given through TOGGLE SWITCHES as per circuit

diagram. (iii) Observe the output USING LED’s and verify the truth table.

LOGIC DIAGRAM:

HALF SUBTRACTOR

TRUTH TABLE:

INPUT OUTPUT A B DIFFERENCE BORROW


(D) (B) 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0

DIFFERENCE = AB+AB BORROW = AB

LOGIC DIAGRAM:

FULL SUBTRACTOR

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:

TRUTH TABLE:

INTPUTS OUTPUT

A B C DIFFERENCE (D)

BORROW (B)

0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1


⊕ ⊕DIFFERENCE = ABC+ABC+ABC+ABC = A B C BORROW = AB+BC+AC RESULT:

Half Subtractor and Full Subtractor circuits are constructed and

their truth tables are verified. 3 .GREY CODE CONVERTER AIM:

To design and implement 4-bit (i) Binary to gray code converter (ii) Gray to binary code converter

APPARATUS REQUIRED:

Sl.No. COMPONENTS SPECIFICATION QTY. 1. X-OR GATE IC 7486 1 2. IC TRAINER KIT - 1 3. PATCH CORDS - -

THEORY:

The availability of large variety of codes for the same discrete elements of

information results in the use of different codes by different systems. A

conversion circuit must be inserted between the two systems if each uses

different codes for same information. Thus, code converter is a circuit that

makes the two systems compatible even though each uses different binary code.

The bit combination assigned to binary code to gray code. Since each

code uses four bits to represent a decimal digit. There are four input and four

output. Gray code is a non-weighted code.

The input variable are designated as B3, B2, B1, B0 and the output

variables are designated as C3, C2, C1, Co. from the truth table, combinational

circuit is designed. The Boolean functions are obtained from K-Map for each

output variable.


A code converter is a circuit that makes the two systems compatible even

though each uses a different binary code. To convert from binary code to

Excess-3 code, the input lines must supply the bit combination of elements as

specified by code and the output lines generate the corresponding bit

combination of code. Each one of the four maps represents one of the four

output of the circuit as a function of the four input variables.

A two-level logic diagram may be obtained directly from the Boolean

expressions derived by the maps. These are various other possibilities for a

logic diagram that implements this circuit. Now the OR gate whose output is C+D

has been used to implement partially each of three output.

PROCEDURE:


diagram.


circuit diagram.


LOGIC DIAGRAM:

BINARY TO GRAY CODE CONVERTOR


G3 =B3

TRUTH TABLE:

Binary input Gray code output B3 B2 B1 B0 G3 G2 G1 G0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 0 0 0 1 1 0 0 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 0 0 0

LOGIC DIAGRAM:

GRAY CODE TO BINARY CONVERTOR


B3 = G3

⊕B2 = G3 G2 ⊕ ⊕B1= G3 G2 G1

TRUTH TABLE:

Gray Code Binary Code G3 G3 G3 G3 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 0 0 1 1 1 1 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 0 1 1 0 0 1 0 1 1 1 1 0 1 1 0 0 1 1 1 1 0 1 0 0 0 1 1 1 1

RESULT:

Gray to Binary and Binary to Gray converter circuits are constructed and their truth tables are verified.


4. DECADE COUNTER

AIM: To construct and verify the truth table of Decade Counter using IC 7490

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY. 1. DECADE COUNTER IC 7490 1 2. IC TRAINER KIT - 1 3. PATCH CORDS - 15

THEORY: A counter is a register capable of counting number of clock pulse arriving

at its clock input. Counter represents the number of clock pulses arrived. A

specified sequence of states appears as counter output. This is the main

difference between a register and a counter. There are two types of counter,

synchronous and asynchronous. In synchronous common clock is given to all

flip flop and in asynchronous first flip flop is clocked by external pulse and then

each successive flip flop is clocked by Q or Q output of previous stage. A soon

the clock of second stage is triggered by output of first stage. Because of

inherent propagation delay time all flip flops are not activated at same time

which results in asynchronous operation.


diagram.


circuit diagram.



PIN DIAGRAM FOR IC 7490

Note: • R01,R02,Rg1,Rg2(Pin no.2,3,6,7) = All are connected to Ground • Pin no. 1 & 12 are shorted • Clock pulse input is given to pin no 14 • QA, QB, QC, QD are connected to Output LED’s.

LOGIC DIAGRAM:


TRUTH TABLE:

INPUT OUTPUT Clock Count QD QC QB QA

0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 10 0 0 0 0

RESULT:

Decade Counter circuit is constructed and its truth table is verified using IC 7490.


5. ENCODER AND DECODER AIM: To construct and verify the truth table of encoder and decoder using IC

74145 and IC 74147.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY. 1. ENCODER IC 74147 1 2. DECODER IC 74145 3

THEORY:

ENCODER: An encoder is a digital circuit that perform inverse operation of a decoder.

An encoder has 2n input lines and n output lines. In encoder the output lines

generates the binary code corresponding to the input value. In octal to binary

encoder it has eight input, one for each octal digit and three output that generate

the corresponding binary code. In encoder it is assumed that only one input has

a value of one at any given time otherwise the circuit is meaningless. It has an

ambiguity that when all input are zero the output are zero. The zero output can

also be generated when D0 = 1.

DECODER:

A decoder is a multiple input multiple output logic circuit which converts

coded input into coded output where input and output codes are different. The

input code generally has fewer bits than the output code. Each input code word

produces a different output code word i.e. there is one to one mapping can be expressed in truth table. In the block diagram of decoder circuit the encoded information is present as n input producing 2n possible output. 2n output values

are from 0 through out 2n – 1.


diagram.


circuit diagram.



PIN DIAGRAM FOR IC 74147(ENCODER):

TRUTH TABLE:

INPUT OUTPUT

E1 E2 E3 E4 E5 E6 E7 QA QB QC

0 0 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 1

0 1 0 0 0 0 0 0 1 0

0 0 1 0 0 0 0 0 1 1

0 0 0 1 0 0 0 1 0 0

0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 1 1 1 1


PIN DIAGRAM FOR IC 74145(DECODER):

TRUTH TABLE:

INPUT OUTPUT

QA QB QC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

RESULT:

Encoder and Decoder circuits are constructed and their truth tables are verified.


6. MULTIPLEXER AND DEMULTIPLEXER AIM:

To construct and verify the truth table of multiplexer and demultiplexer

using IC 74153 and IC 74139

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY. 1. MULTILXER IC 74153 1 2. DEMULTIPLEXER IC 74139 1 3. IC TRAINER KIT - 1 4. PATCH CORDS - -

THEORY:

MULTIPLEXER:

Multiplexer means transmitting a large number of

information units over a smaller number of channels or lines. A digital

multiplexer is a combinational circuit that selects binary information from one of

many input lines and directs it to a single output line. The selection of a

particular input line is controlled by a set of selection lines. Normally there are 2n

input line and n selection lines whose bit combination determine which input is

selected.

DEMULTIPLEXER:

The function of Demultiplexer is in contrast to

multiplexer function. It takes information from one line and distributes it to a

given number of output lines. For this reason, the demultiplexer is also known as

a data distributor. Decoder can also be used as demultiplexer.

PROCEDURE:


diagram.


(ii) Logical input is given through TOGGLE SWITCHES as per circuit

diagram.


LOGIC DIAGRAM :

MULTIPLEXER:

TRUTH TABLE:


DEMULTIPLEXER:

TRUTH TABLE:

RESULT:

Multiplexer and Demultiplexer are constructed and its truth table are verified.


MICROPROCESSOR AND MICROCONTROLLER LAB

OBSERVATION / RECORD FORMAT

AIM: ALGORITHM: FLOWCHART: PROGRAM: Memory Address

Hex code Label

Mnemonics Comments

Opcode Operand

SAMPLE INPUT & OUTPUT:

INPUT OUTPUT

RESULT: Note:

i) AIM, APPARATUS REQUIRED, ALGORITHM, – Right Hand Side PROGRAM, SAMPLE INPUT & OUTPUT, RESULT – Right Hand Side

ii) FLOWCHART – Left Hand Side

Memory Address

Data

Memory Address

Data


1. (a) ADDITION OF TWO 8 BIT NUMBERS AIM:

To write an assembly language program for addition of two 8 bit numbers using 8085. ALGORITHM: 1) Start the program by loading the first data into Accumulator. 2) Move the data to a register (B register). 3) Get the second data and load into Accumulator. 4) Add the two register contents. 5) Check for carry. 6) Store the value of sum and carry in memory location. 7) Terminate the program. PROGRAM:

Memory Address Hex Code Label

Mnemonics Comments

Opcode Operand

OBSERVATION: Input: Output:

Memory Address

Data (Sum)

Data (Carry)

RESULT: The assembly language program for addition of two 8-bit numbers has been written and executed using microprocessor 8085. (B)SUBTRACTION OF TWO 8 BIT NUMBERS AIM: To write an assembly language program for subtraction of two 8 bit numbers using 8085.

Memory Address

Data


ALGORITHM: 1. Start the program by loading the first data into Accumulator. 2. Move the data to a register (B register). 3. Get the second data and load into Accumulator. 4. Subtract the two register contents. 5. Check for carry. 6. If carry is present take 2’s complement of Accumulator. 7. Store the value of borrow in memory location. 8. Store the difference value (present in Accumulator) to a memory 9. location and terminate the program. PROGRAM:


Mnemonics Comments

Opcode Operand


Memory Address

Data (Difference)

Data (Borrow)

RESULT: The program for subtraction of two 8-bit numbers has been written and executed using microprocessor 8085. (C)MULTIPLICATION OF TWO 8 BIT NUMBERS AIM: To write an assembly language program for multiplication of two 8 bit numbers using 8085. ALGORITHM: 1) Start the program by loading HL register pair with address of memory location. 2) Move the data to a register (B register). 3) Get the second data and load into Accumulator. 4) Add the two register contents. 5) Check for carry.

Memory Address

Data


6) Increment the value of carry. 7) Check whether repeated addition is over and store the value of product and carry in memory location. 8) Terminate the program. PROGRAM:


Mnemonics Comments

Opcode Operand


Memory Address

Data (LSB of Product)

Data (MSB of Product)

RESULT: The program for multiplication of two 8-bit numbers has been written and executed using microprocessor 8085. (D)DIVISION OF TWO 8 BIT NUMBERS AIM: To write an assembly language program for division of two 8 bit numbers using 8085. ALGORITHM: 1) Start the program by loading HL register pair with address of memory location. 2) Move the data to a register(B register). 3) Get the second data and load into Accumulator. 4) Compare the two numbers to check for carry. 5) Subtract the two numbers. 6) Increment the value of carry . 7) Check whether repeated subtraction is over and store the value of product and carry in memory location. 8) Terminate the program.

Memory Address

Data


PROGRAM:


Mnemonics Comments

Opcode Operand


Memory Address

Data (Quotient)

Data (Reminder)

RESULT: The program for division of two 8-bit numbers has been written and executed using microprocessor 8085.

Memory Address

Data


2.PROGRAMS BASED ON SORTING (A ) Ascending order AIM: To write an assembly language program to sort the array of numbers in ascending/descending order using 8085 microprocessor . ALGORITHM: 1) Initialize the size of array 2) Initialize the memory pointer 3) Get the number in Accumulator 4) Increment the memory pointer 5) Compare. 6) If A,< M don’t interchange 7) If A=M Don’t Interchange 8) Otherwise swap & Interchange numbers 9) Increment the next memory 10) Decrement the C and check till C not equal to 0 11) Decrrement the outside counter. 12) Check till B not equal to 0. 13) Terminate the program. PROGRAM:


Mnemonics Comments

Opcode Operand


Memory Address

Data

RESULT: The program for finding the smallest number in an array has been written and executed using microprocessor 8085. Note: For Descending order use JNC instead of JC

Memory Address

Data


3. STEPPER MOTOR INTERFACING AIM: To write an assembly language program to interface a stepper motor using 8085 microprocessor. ALGORITHM:

1. Initialize the Accumulator with control register address 2. Move the control word (all ports as output) in I/O mode

through ‘A’ register. 3. Initialize the Accumulator with Port A address . 4. Move the first sequence of data to Port A address through ‘A’ register. 5. Call the delay subroutine 6. Move the second sequence of data to Port A address through ‘A’ register. 7. Call the delay subroutine 8. Move the third sequence of data to Port A address through ‘A’ register. 9. Call the delay subroutine 10. Move the fourth sequence of data to Port A address through ‘A’ register. 11. Call the delay subroutine 12. Repeat 4-10 steps

PROGRAM:


Mnemonics Comments

Opcode Operand

OBSERVATION: Clockwise rotation: Anticlockwise rotation:

Memory Address

Data

RESULT: The program for interfacing a stepper motor has been written and executed using microprocessor 8085.

Memory Address

Data


4. INTERFACING ADC AND DAC DAC: Aim : To write an assembly language program to generate square and triangular waves using DAC interface. Algorithm: [a] Square Wave Generation

1. Start 2. Initialize the control register 3. Give the input as high and out in port B 4. Call Delay 5. Give the input as low and out in Port B 6. Call Delay 7. Jump to step 3

Delay (Subroutine)

1. Start 2. Set the count 3. Decrement the count till zero 4. Return to main program

[b] Triangular Wave Generation

1. Start 2. Initialize the control register 3. Give the input as low 4. out in port B 5. Increment the count 6. Check the count is equal to FF 7. If it is not equal then jump to step 4 8. If it is not equal then jump to step 9 9. Out this in port B 10. Decrement the count 11. Check the count is equal to 00 12. If it is not equal then jump to step 9 13. If it is equal then jump to step 4

Result:

The program for interfacing a DAC has been written and executed using microprocessor 8085.


ADC: Aim : To write an assembly language program to interface an ADC with 8085 microprocessor. Algorithm:

1. Start 2. Initialize the control register port A as input ,Port B and port C as output 3. Give the Start of Conversion 4. Call Delay 5. End of Conversion Port A as input 6. Break point

Delay (Subroutine)


Result:

The program for interfacing a ADC has been written and executed using microprocessor 8085.


5. TRAFFIC LIGHT CONTROL USING 8085 Aim: To write an assembly language program to interface a Traffic Light Control system with 8085 microprocessor. Algorithm:

1. Start 2. Initialize the control register, set the ports as output 3. Give the input value through the assigned ports (first) 4. Call delay 5. Give the input value through the assigned ports (second) 6. Call delay 7. Give the input value through the assigned ports (third) 8. Call delay 9. Give the input value through the assigned ports (fourth) 10. Call delay 11. Jump to step 3

Delay (Subroutine)


Result:

The program for interfacing a Traffic light control system has been written and executed using microprocessor 8085.


6. PROGRAMS BASED ON ARITHMETIC OPERATIONS AIM: To write an 8051 assembly language program to perform the following for two 8 bit numbers by using Internal and External Memory. a) Addition b) Subtraction c) Multiplication d) Division

APPARATUS REQUIRED:

i) 8051 Microcontroller Kit ii) Power Supply iii) Keyboard

ALGORITHM: INTERNAL MEMORY :

a) Addition

1. Move the first data to ‘A’ register. 2. Move the second data to ‘R0’ register. 3. Add the contents of ‘A’ register and ‘R0’ register. 4. Store the result (Sum & Carry) from ‘A’ to the location pointed by Internal memory.

EXTERNAL MEMORY :

Addition

1. Initialize the data pointer.

2. Move the first data to ‘R0’ register through ‘A’ register.

3. Increment the data pointer.

4. Move the second data to ‘A’ register.

5. Add the values of ‘A’ and ‘R0’ registers.


7. Store the result (Sum & Carry) from ‘A’ to the location pointed by

Data Pointer (DPTR).


INTERNAL MEMORY :

b) Subtraction

1. Clear the carry flag. 2. Move the first data to ‘A’ register. 3. Move the second data to ‘R0’ register. 4. Subtract the contents of ‘R0’ register from ‘A’ register. 5. Store the result (Difference) from ‘A’ to the location pointed by

Internal memory.

EXTERNAL MEMORY :

Subtraction

1. Clear the Carry flag.

2. Initialize the data pointer.

3. Move the first data to ‘R0’ register through ‘A’ register.


5. Move the second data to ‘A’ register.

6. Subtract the values of ‘R0’ and ‘A’ register.


8. Store the result (Difference) from ‘A’ to the location pointed by

Data Pointer (DPTR).

INTERNAL MEMORY :

Multiplication

Move the first data to ‘A’ register. Move the second data to “B(0F0)” register. Multiply the contents of ‘A’ register and ‘B’ register. Store the result from ‘A’ and ‘B’ to the location pointed by

Internal memory.

EXTERNAL MEMORY:

c) Multiplication 1. Initialize the data pointer. 2. Move the first data to ‘B’ register through ‘A’ register. 3. Increment the data pointer.


4. Move the second data to ‘A’ register. 5. Multiply the values of ‘A’ and ‘B’ registers. 6. Increment the data pointer. 7. Store the result (LSB) from ‘A’ to the location pointed by Data Pointer (DPTR). 8. Increment the data pointer. 9. Move the contents of ‘B’ register to ‘A’ register. 10. Store the result (MSB) from ‘A’ to the location pointed by Data Pointer (DPTR).

INTERNAL MEMORY :

Division

a. Move the first data to ‘A’ register. b. Move the second data to “B(0F0)” register. c. Divide the contents of ‘A’ register and ‘B’ register. d. Store the result from ‘A’ and ‘B’ to the location pointed by

Internal memory.

EXTERNAL MEMORY:

d) Division

1. Initialize the data pointer. 2. Move the first data to ‘B’ register through ‘A’ register. 3. Increment the data pointer. 4. Move the second data to ‘A’ register. 5. Divide the values of ‘A’ and ‘B’ registers. 6. Increment the data pointer. 7. Store the result (Quotient ) from ‘A’ to the location pointed by Data Pointer (DPTR). 8. Increment the data pointer. 9. Move the contents of ‘B’ register to ‘A’ register. 10. Store the result (Remainder) from ‘A’ to the location pointed by Data Pointer (DPTR).

RESULT: Thus the 8051 Assembly Level Language Program for Addition, Subtraction,

Multiplication and Division of two 8 bit numbers are written and executed by using

Internal and External Memory


7.PROGRAMS BASED ON SORTING [a & b] ASCENDING AND DESCENDING ORDER

AIM: To write an 8051 assembly language program to arrange the numbers in

a)Ascending order b)Descending order

APPARATUS REQUIRED:

i) 8051 Microcontroller Kit ii) Power Supply iii) Keyboard

ALGORITHM:

a) Ascending Order

1. Start the program. 2. Get the first data and compare with the second Data. 3. If the two data are in ascending order then no swap. 4. Else swap the data byte by ascending order and then again compare

the other data bytes up to the count. 5. Do the above comparison as many times as the count. 6. Finally the array is arranged in ascending order.

b) Descending Order

1. Start the program. 2. Get the first data and compare with the second Data. 3. If the two data are in descending order then no swap. 4. Else swap the data byte by descending order and then again

compare the other data bytes up to the count. 5. Do the above comparison as many times as the count. 6. Finally the array is arranged in descending order.

RESULT: Thus the 8051 Assembly Level Language Program to arrange the numbers

in ascending order, descending order are written and executed.


8. STEPPER MOTOR INTERFACING AIM: To write an 8051 assembly language program to run the stepper motor in

i) Clockwise direction. ii) Anticlockwise direction.

APPARATUS REQUIRED:

ii) 8051 Microcontroller Kit iii) Power Supply iv) Keyboard v) Stepper motor with interface board

ALGORITHM:

1. Initialize the Data Pointer(DPTR) with control register address 4003 2. Move the control word (all ports as output) in I/O mode to the DPTR

through ‘A’ register. 3. Initialize the Data Pointer(DPTR) with Port A address 4000. 4. Move the first sequence of data to Port A address through ‘A’ register. 5. Call the delay subroutine 6. Move the second sequence of data to Port A address through ‘A’ register. 7. Call the delay subroutine 8. Move the third sequence of data to Port A address through ‘A’ register. 9. Call the delay subroutine 10. Move the fourth sequence of data to Port A address through ‘A’ register. 11. Call the delay subroutine 12. Repeat 4-10 steps

CONTROL WORD REGISTER (CWR) D7 D6 D5 D4 D3 D2 D1 D0

CONTROL WORD : All the Ports as Outputs. D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 0 0 - 80


Step sequence of data for one step Clockwise rotation PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 1 0 0 0 0 0 0 0 - 80 1 0 1 0 0 0 0 0 - A0 1 1 1 0 0 0 0 0 - E0 1 1 0 0 0 0 0 0 - C0 Step sequence of data for one step anticlockwise rotation PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 1 1 0 0 0 0 0 0 - C0 1 1 1 0 0 0 0 0 - E0 1 0 1 0 0 0 0 0 - A0 1 0 0 0 0 0 0 0 - 80 Working Procedure for stepper motor:

1. Connect the 5V supply to the trainer kit and stepper motor chord. 2. Connect the + 12V supply to the power bit wire (yellow color) in the chord. 3. Connect the corresponding grounds. 4. Connect the 26 pin FRC from the kit to the chord. 5. Switch on the Power supply. 6. Assemble the program and execute it. 7. The stepper motor will start rotating either in clockwise or anticlockwise direction

based on the order of the coil excitation. 8. Switch off the power supply and remove all the connections

RESULT: Thus the 8051 Assembly Level Language Program, to run the stepper motor

in Clockwise direction and anticlockwise direction are written and executed.


9.TRAFFIC LIGHT CONTROL USING 8051 Aim: To write an assembly language program to interface a Traffic Light Control system with 8051 microcontroller. Algorithm:

1. Start 2. Initialize the control register, set the ports as output 3. Give the input value through the assigned ports (first) 4. Call delay 5. Give the input value through the assigned ports (second) 6. Call delay 7. Give the input value through the assigned ports (third) 8. Call delay 9. Give the input value through the assigned ports (fourth) 10. Call delay 11. Jump to step 3

Delay (Subroutine)


Result:

The program for interfacing a Traffic light control system has been written and executed using microcontroller 8051.

Date post:	14-Apr-2015
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