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Mehdi Sadi , Italo Armenti

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Design of a Near Threshold Low Power DLL for Multiphase Clock Generation and Frequency Multiplication. Mehdi Sadi , Italo Armenti. Outline. Introduction and Motivation Background Our Works and simulations Conclusions and Future Works. Introduction and Motivation. - PowerPoint PPT Presentation
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Mehdi Sadi, Italo ArmentiDesign of a Near Threshold Low Power DLL for Multiphase Clock Generation and Frequency MultiplicationOutlineIntroduction and MotivationBackgroundOur Works and simulationsConclusions and Future Works

Introduction and MotivationDelay Locked Loops (DLL) are extensively used for multiphase clock generation in SoC and in clock and data recovery circuits.

DLL`s counterpart Phase Locked Loops(PLL) suffer from instability due to PVT variation and noise.

Very few researchers have looked into the effect of voltage scaling on DLL performance .

Design Challenges Design challenges when voltage supply is scaled down

Appropriate device sizes in the critical path, Ensuring correct duty cycle at output frequency. Keeping static phase error within bounds.

Background (Mesgardazeh et. al)Possible to redesign with reduced components but same performance at operating frequency.

Block diagram

Phase DetectorC2MOS DFF with Reset option.Critical path devices are sized to ensure faster charging and discharging at the desired frequency range.

FreqMinimum ResolutionPower(uW)1GHz45p40700M55p39.88500M55p39.63200M55p39.63100M55p39.62Delay LineBinary weighted switched capacitors control the delay per stage.

Delay Line DesignDelay per stage,

At lock in condition

The switching voltage should be adjusted at VDD/2 to avoid duty cycle error.

**

Counter8 bit binary up down counter with reset and hold options.The counter is power and clock gated to reduce power when the clock phases are aligned.During Sleep mode the counting states are held in a latch.

Power without gating = 9.1uWPower with gating = 2.72 uW

70 % Power saved with gatingGating Effect StartedEdge CombinerXOR Gate Based Edge Combiner. Generates 4 times the reference frequencyTo ensure proper duty cycle the Devices in the critical path must be sized properly. Sizing also depends on operating frequency range.

Full Waveform

Process VariationProcess CornerStatic Phase error (ps)Lock in time at 200 MHzTT5050 cyclesSS5555 cyclesFS4750 cyclesSF4550 cycles (also duty cycle mismatch)FF4560 cyclesPerformanceThis workIEEE Tran 08JSSC 09VLSI Symp 07TypeAll DigitalDigitalDigitalDigitalProcess45nm0.35 um90nm0.13umSupply0.7V3.3V1V1.2VFrequency Range80 MHZ - 200MHz4 -200MHz2GHz1.6GHzStatic Phase Error55ps N/A N/A N/ALock in timeBetween 28 to 110 Cycles 16 cycles N/A N/APower120uW17mW7mW6mWConclusionWe have designed a ultra low power all digital DLL operating at 80 -200MHz with 0.7V supply and 120uW.

The DLL can be scaled down to operate at further low voltage by adjusting the critical path device widths

Thank YouD

CLK

Reset

VDD

Reference

Other signal

Control Signal Generator

Lead

D

CLK

Reset

VDD

Reference

Other signal

Lag

Stable

Up/Down~

Stage 1

Buffer

Stage 2

Stage 8

Buffer

Buffer

Input Signal to be delayed

Delayed Output

Cap


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