Memory and Memory Interfacing Pertemuan V

8/6/2019 Memory and Memory Interfacing Pertemuan V

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Memory and MemoryMemory and MemoryInterfacingInterfacing

Kuliah Pertemuan VSistem BerbasisMikroprosesor

Lie Jasa

SEMICONDUCTORSEMICONDUCTOR MEMORYMEMORYFUNDAMENTALSFUNDAMENTALS

In the design of all computers, semiconductor memoriesare used as primary storage for code and data

Semiconductor memories are connected directly to theCPU and

they are the memory that the CPU first asks for information(code and data)

For this reason, semiconductor memories are sometimes referred to as primary

memory

The main requirement of primary memory is that it must be fast inresponding to the CPU;

only semiconductor memories can do that.


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Memory capacityMemory capacity

The number of bits that a semiconductor memorychip can store is called its chip capacity.

It can be in units of Kbits (kilobits), Mbits(megabits), and so on.

While the memory capacity of a memory 1C chipis always given in bits,

the memory capacity of a computer is given inbytes.

Memory organizationMemory organization Memory chips are organized into a number of locations

within the IC. Each location can hold 1 bit, 4 bits, 8 bits, or even 16

bits, depending on how it is designed internally. The number of bits that each location within the memory

chip can hold is always equal to the number of data pinson the chip.

How many locations exist inside a memory chip? That depends on the number of address pins. The

number of locations within a memory IC always equals 2to the power of the number of address pins (there is aslight modification of this rule for dynamic memory, aswill be explained later).


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Memory organizationMemory organization

Therefore, the total number of bits that a memory chipcan store is equal to the number of locations times thenumber of data bits per location. To summarize:

1. Each memory chip contains 2X locations, where x isthenumber of address pins on the chip.

2. Each location contains ybits, where yis the number ofdata pins on the chip.

3. The entire chip will contain 2xx ybits, where xis thenumber of address pins and yis the number of data

pins on the chip.

SpeedSpeed One of the most important characteristics of a memory

chip is the speed at which data can be accessed from it. To access the data, the address is presented to the

address pins, and after a certain amount of time has elapsed, the data

shows up at the data pins. The shorter this elapsed time, the better, and

consequently, the more expensive the memory chip. The speed of the memory chip is commonly referred to

as its access time. The access time of memory chipsvaries from a few nanoseconds to hundreds ofnanoseconds, depending on the IC technology used inthe design and fabrication.


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ROM (readROM (read--only memory)only memory)

ROM is the type of memory that does notlose its contents when the power is turnedoff.

For this reason, ROM is also callednonvolatile memory. There are differenttypes of read-only memory, such asPROM, EPROM, EEPROM, flash

EPROM, and mask ROM. Each isexplained below.

PROM (programmable ROM)PROM (programmable ROM) PROM refers to the kind of ROM that the user can burn

information into. In other words, PROM is a user-pro-grammable memory. For every bit of the PROM,there exists a fuse. PROM is programmed by blowingthe fuses.

If the information burned into PROM is wrong, thatPROM must be discarded since internal fuses are blownpermanently.

For this reason, PROM is also referred to as OTP (one-time programmable). The process of programming ROMis also called burning ROM and requires specialequipment called a ROM burner or ROM programmer.


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ExampleExample

A given memory chip has 12 address pins and 4 datapins. Find

(a) the organization

(b) the capacity

Solution:

(a) This memory chip has 4096 locations (212 = 4096),and each location can hold 4 bits of data. This gives anorganization of 4096 x 4, often represented as 4Kx4.

(b) The capacity is equal to 16K bits since there is a totalof 4K locations and each location can hold 4 bits of data.

ExampleExample

A 512K memory chip has 8 pins for data. Find:

(a) the organization

(b) the number of address pins for this memory chip

Solution:

(a) A memory chip with 8 data pins means that eachlocation within the chip can hold 8 bits of data. To findthe number of locations within this memory chip, divide

the capacity by the number of data pins. 512K/8 =64K;therefore, the organization for this memory chip is64Kx8;

(b) The chip has 16 address lines since 216 = 64K.


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EPROM (erasable programmable ROM)EPROM (erasable programmable ROM)

EPROM was invented to allow making changes in thecontents of PROM after it is burned.

In EPROM, one can program the memory chip anderase it thousands of times.

This is especially useful during development of theprototype of a microprocessor-based project.

The only problem with EPROM is that erasing itscontents can take up to 20 minutes.

All EPROM chips have a window that is used to shineultra-violet (UV) radiation to erase its contents.

For this reason, EPROM is also referred to as UV-erasable EPROM or simply UV-EPROM.

pins for a UVpins for a UV--EPROM chipEPROM chip


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To program a UVTo program a UV--EPROM chipEPROM chip

the following steps must be taken:

1. Its contents must be erased. To erase a chip, it isremoved from its socket on the system board andplaced in EPROM erasure equipment to expose it to UVradiation for 15 - 20 minutes.

2. Program the chip. To program a UV-EPROM chip,place it in the ROM burner (programmer). To bum codeor data into EPROM, the ROM burner uses 12.5 volts orhigher, depending on the EPROM type. This voltage isreferred to as VPP in the UV-EPROM data sheet.

3. Place the chip back into its socket on the systemboard.

EEPROMEEPROM(electrically erasable programmable ROM)(electrically erasable programmable ROM)

EEPROM method of erasure is electrical and therefore instant, asopposed to the 20-minute erasure time required for UV-EPROM.

in EEPROM, one can select which byte to be erased, in contrast toUV-EPROM, in which the entire contents of ROM are erased.

EEPROM is the fact that one can program and erase its contentswhile it is still in the system board. It does not require physicalremoval of the memory chip from its socket.

unlike UV-EPROM, EEPROM does not require an external erasureand programming device.

To utilize EEPROM fully, the designer must incorporate into the

system board the circuitry to program the EEPROM, using 12.5 V forVPP. EEPROM with VPP of 5 - 7 V is available, but it is expensive.In general, the cost per bit for EEPROM is much higher than for UV-EPROM.


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Flash memory EPROMFlash memory EPROM

Since the early 1990s, flash EPROM hasbecome a popular user-programmable memorychip, and for good reasons.

First, the process of erasure of the entire

contents takes less than a second, or one mightsay in a flash, hence its name: flash memory.

In addition, the erasure method is electrical andfor this reason it is sometimes referred to asflash EEPROM

The major difference between EEPROM and flashmemory is the fact that when flash memory's contentsare erased the entire device is erased,

in contrast to EEPROM, where one can erase a desiredsection or byte.

Although there are some flash memories recently madeavailable in which the contents are divided into blocksand the erasure can be done block by block,

unlike EEPROM, no byte erasure option is available.Due to the fact that flash memory can be programmedwhile it is in its socket on the system board, it isbecoming widely used as a way to upgrade the BIOS

ROM of the PC. Some designers believe that flash memory will replace

the hard disk as a mass storage medium.


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This would increase the performance of thecomputer tremendously, since flash memory is

semiconductor memory with access time in therange of 100 ns compared with disk access timein the range of tens of milliseconds.

For this to happen, flash memory'sprogram/erase cycles must become infinite, justlike hard disks.

Program/erase cyclerefers to the number oftimes that a chip can be erased andprogrammed before it becomes unusable.

At this time, the program/erase cycle is 10,000for flash and EEPROM, 1000 for UV-EPROM,and for RAM and disks it is infinite.

Mask ROMMask ROM Mask ROM refers to a kind of ROM whose contents are

programmed by the IC manufacturer. In other words, it is not a user-programmable ROM. The

terminology maskis used in IC fabrication. Since the process is costly, mask ROM is used when the

needed volume is high and it is absolutely certain thatthe contents will not change.

It is common practice to use UV-EPROM for thedevelopment phase of a project, and only after the

code/data have been finalized is mask ROM ordered. The main advantage of mask ROM is its cost, since it is

significantly cheaper than other kinds of ROM, but if anerror in the data/code is found, the entire batch must bethrown away.


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RAM (random access memory)RAM (random access memory)

RAM memory is called volatile memorysincecutting off the power to the IC will mean the lossof data.

Sometimes RAM is also referred to as RAWM(read and write memory), in contrast to ROM,which cannot be written to.

There are three types of RAM: static RAM (SRAM),

dynamic RAM (DRAM), NV-RAM (nonvolatile RAM).

SRAM (static RAM)SRAM (static RAM)

Storage cells in static RAM memory are made of flip-flops and therefore do not require refreshing in order tokeep their data. This is in contrast to DRAM,

The problem with the use of flip-flops for storage cells isthat each cell requires at least 6 transistors to build, andthe cell holds only 1 bit of data. In recent years, the cellshave been made of 4 transistors, which still is too many.The use of 4-transistor cells plus the use of CMOS

technology has given birth to a high-capacity SRAM, butthe capacity of SRAM is far below DRAM.

SRAMs are widely used for cache memory.


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SRAM (static RAM)SRAM (static RAM)

DRAM (dynamic RAM)DRAM (dynamic RAM) the need for huge, inexpensive read/write memory was a major

preoccupation of computer designers. In 1970, Intel Corporation introduced the first dynamic RAM (random

access memory). Its density (capacity) was 1024 bits and it used a capacitor to store

each bit. The use of a capacitor as a means to store data cuts down the

number of transistors needed to build the cell;

however, it requires constant refreshing due to leakage. This is in contrast to SRAM (static RAM), whose individual cells are

made of flip-flops. Since each bit in SRAM uses a single flip-flop and each flip-flop

requires 6 transistors, SRAM has much larger memory cells andconsequently lower density.

The use of capacitors as storage cells in DRAM results in muchsmaller net memory cell size.


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DRAM (dynamic RAM)DRAM (dynamic RAM)

The major advantages are high density

(capacity),

cheaper cost per bit,

and lower power consumption per bit.

The disadvantage is that it must be refreshedperiodically, due to the fact that the capacitor cellloses its charge;

furthermore, while it is being refreshed, the datacannot be accessed. This is in contrast to

SRAM's flip-flops, which retain data as long asthe power is on, which do not need to berefreshed, and whose contents can be accessedat any time.


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After the IK-bit (1024) chip came the 4K-bit in1973, and then the 16K chip in 1976. The 1980s

saw the introduction of 64K, 256K, and finally1M and 4M memory chips.

The 1990s will see 16M, 64M, 256M, andpossibly IG-bit DRAM chips.

motherboards use 256K, 1M, 4M, and 16Mchips. These will be discussed along with howthey are used in the PC and compatibles. Keepin mind that when talking about IC memorychips, the capacity is always assumed to be in

bits.

Packaging issue in DRAMPackaging issue in DRAM

In DRAM there is a problem of packing a largenumber of cells into a single chip with thenormal number of pins assigned to addresses.

For example, a 64K-bit chip (64Kx1) must have16 address lines and 1 data line, requiring

1. 16 pins to send in the address if theconventional method is used. This is in addition

to2. Vcc power, ground,

3. and read/write control pins.


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Packaging issue in DRAMPackaging issue in DRAM

Using the conventional method of data access, the largenumber of pins defeats the purpose of high density andsmall packaging, to reduce the number of pins neededfor addresses, multiplexing / demultiplexing is used.

The method used is to split the address into half andsend in each half of the address through the same pins,thereby requiring fewer address pins.

Internally, the DRAM structure is divided into a square ofrows and columns. The first half of the address is called

the rowand the second half is called the column. Forexample, in the case of DRAM of 64Kx 1 organization,

the first half of the address is sent in through the 8 pins A0 - A7, and

by activating RAS (row address strobe), the internal latches inside DRAM grab the first half of the address.

After that,

the second half of the address is sent in through the same pins andby activating CAS (column address strobe), the internal latchesinside DRAM again latch this second half of the address.

This results in using 8 pins for addresses plus RAS and CAS,

for a total of 10 pins, instead of 16 pins that would be requiredwithout multiplexing.

To access a bit of data from DRAM, both row and column addressesmust be provided. For this concept to work, there must be a 2 by 1multiplexer outside the DRAM circuitry and a demultiplexer insideevery DRAM chip.

Due to the complexities associated with DRAM interfacing (RAS,CAS, the need for multiplexer and refreshing circuitry), there areDRAM controllers designed to make DRAM interfacing much easier.However, many small microprocessor-based projects that do notrequire much RAM (usually less than 64K bytes) use SRAM insteadof DRAM.


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DRAM organizationDRAM organization

EPROM, have 8 pins for data.

This is not the case for RAM. Although SRAMvery often are x4 or x8, DRAM can have any ofx1, x4, x8, or xl6 organizations. However, mostDRAMs are xl and x4.

In some memory chips (notably ROM), the datapins are called I/O.

In some DRAMs there are separate pins Din and

Dout.

DRAM organization ExampleDRAM organization Example Show possible organizations and number of address pins for 256K

DRAM chip Solution: For 256K chips, possible organizations are 256Kx1 or 64Kx4. In the case of 256Kxl, there are 256K locations and each location

inside DRAM provides 1 bit. The 256K. locations are accessed through the 18-bit address A0

A17 since 218 = 256K.

The chip has only A0 - A8 physical pins plus RAS and CAS and onepin for data in addition to Vcc, ground, and the R/W pin that everyDRAM chip must have.

For 64Kx4 organization, it requires 16 address bits to access eachlocation (216 = 64K), and each location inside the DRAM has 4 cells.That means that it must have 4 data pins, D0 - D3, 8 address pins,A0 - A7, plus RAS and CAS.


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DRAM organization ExampleDRAM organization Example

Show possible organizations and number of addresspins for 1M DRAM chip

Solution:

In the case of a 1M chip, there can be either 1Mx1 or256Kx4 organizations.

For 1Mx1, there are A0 - A9, 10 pins, to access 220 =1M locations with the help of RAS and CAS and one pinfor data.

The 256Kx4 has 9 (A0 - A8) and 4 (D0 - D3) pins,

respectively, for address and data plus RAS and CASpins.

ExampleExample Discuss the number of pins set aside for addresses in

each of the following memory chips.

(a) 16Kx4 DRAM

(b) 16Kx4 SRAM

Solution:

(a) For DRAM we have 7 pins (A0 - A6) for the addresspins and 2 pins for RAS and CAS.

(b) For SRAM we have 14 pins for address and no pinsfor RAS and CAS since they are associated only withDRAM. In both cases we have 4 pins for the data bus.


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NVNV--RAM (nonvolatile RAM)RAM (nonvolatile RAM)

While both DRAM and SRAM are volatile, there is a new type of RAM calledNV-RAM, nonvolatile RAM.

Like other RAMs, it allows the CPU to read and write to it, but when thepower is turned off the contents are not lost, just like ROM.

NV-RAM combines the best of RAM and ROM: the read and writ ability ofRAM, plus the nonvolatility of ROM.

To retain its contents, every NV-RAM chip internally is made of the followingcomponents:

1. It uses extremely power efficient (very, very low power consumption) SRAMcells built out of CMOS.

2. It uses an internal lithium battery as a backup energy source.3. It uses an intelligent control circuitry.

The main job of this control circuitry is to monitor the Vcc pin constantly todetect loss of the external power supply. If the power to the Vcc pin falls

below out-of-tolerance conditions, the control circuitry switchesautomatically to its internal power source, the lithium battery. In this way,the internal lithium power source is used to retain the NV-RAM contentsonly when the external power source is off.

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Memory and Memory Interfacing Pertemuan V

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