23
Early Memories
Williams Tube CRT-based random accessmemory, 1946. Used on the Manchester Mark I.2048 bits.
Memory – p.
Early Memories
Mercury acousticdelay line.Used in the EDASC,1947.32 × 17 bits
Memory – p.
Early Memories
Magnetic core memory, 1952. IBM.
Memory – p.
Early Memories
Magnetic drum memory. 1950s & 60s.Secondary storage.
Memory – p.
Modern Memory Choices
Family Programmed Persistence
Mask ROM at fabrication ∞
PROM once ∞
EPROM 1000s, UV 10 years
FLASH 1000s, block 10 years
EEPROM 1000s, byte 10 years
NVRAM ∞ 5 years
SRAM ∞ while powered
DRAM ∞ 64 msMemory – p.
ROMs
Memory – p.
EPROMs
Memory – p.
EEPROM and FLASH
Source
Drain(bit line)Channel
Word Linefloating gate
Oxide
Slow write
Fowler-NordheimTunneling
EEPROM: bitat a time
FLASH: blockat a time
Source: SST
Memory – p.
Static RAM Cell
Word
Bit Bit
Memory – p. 10
Standard SRAM: 6264
CS226CS1
20WE
27OE
22Addr[12:0]10–2,25–23,21D[7:0]19–15,13–11
8K × 8
Can be very fast:Cypress sells a 55nsversion
Simple, asynchronousinterface
Memory – p. 11
Standard SRAM: 6264
HHH�LLLLL�HHH�LLLLL�HHHCS1
LLL�HHHHH�LLL�HHHHH�LLLCS2
HHHH�LLL�HHHHHHHHHHHHHHHHWE
HHHHHHHHHHHHHHHHH�LL�HHHHOE
UU�VVVVVVV�UUU�VVVV�UUUAddr
ZZ�VVVVVVVV�ZZZZ�VV�ZZZData Memory – p. 12
Standard SRAM: 6264
CY6264-1
A1A2A3A4A5A6A7A8
I/O0
256 x 32 x 8ARRAY
INPUT BUFFER
COLUMN DECODERPOWERDOWN
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7CE1CE2WE
OE
Memory – p. 13
Toshiba TC55V16256J 256K × 16
CE6
WE17
OE41
LB39
UB40
Addr[17:0]23,22,18–21,24–27,42–44,1–5D[15:0]38–35,32–29,16–13,10–7
12 or 15 ns access time
Asynchronous interface
UB, LB select bytesMemory – p. 14
Toshiba TC55V16256J 256K × 16
Memory – p. 15
Dynamic RAM Cell
Row
Column
Basic problem: Leakage
Solution: Refresh
Memory – p. 16
Ancient DRAM: 4164
64K × 1Apple IIe vintage
RAS4
CAS15
WE3
DIN2 DOUT 14Addr[7:0]9,13,10–12,6,7,5
Memory – p. 17
Basic DRAM read and write cycles
HH�LLLLLLLLL�HH�LLLLLL�HHRAS
HHHHHH�LLLLL�HHHHHH�LL�HHCAS
�VV�VV�UUUUU�VV�VV�UUUUAddr
FFFFÆHH�FFFFFFFFFF LL�FFFWE
UUUUUUUUUUUUUUUUUUUU�VV�UUUDin
ZZZZZZZZ�VVV�ZZZZZZZZZZZZZZDout
Row Col Row Col
Memory – p. 18
Page mode read cycle
HH�LLLLLLLLLLLLLLLLLLLLLL�HRAS
HHHHHH�LLL�H�LLL�H�LL�HCAS
�VV�VV�UUU�VV�U�VV�UUUAddr
FFFFÆHHH�FÆHHH�ÆHHHH�FFWE
UUUUUUUUUUUUUUUUUUUUUUUUUUUUUDin
ZZZZZZZZ�VVV�Z�VVV�Z�VVVDout
Row Col Col Col
Memory – p. 19
Samsung 8M × 16 SDRAM
CLK38CKE37RAS
15CAS
15WE
3LDQM15UDQM39DQ[15:0]Addr[11:0]BA[1:0]21,20 Bank address
Address (multiplexed)Data I/OUpper byte enableLower byte enableWrite enableColumn Address StrobeRow Address StrobeClock EnableClock
Synchronous interfaceDesigned for burst-mode operationFour separate banks; pipelined operation Memory – p. 20
Samsung 8M × 16 SDRAM
Bank Select
Data Input Register
8M x 4 / 4M x 8 / 2M x 16
8M x 4 / 4M x 8 / 2M x 16
Sense A
MP
Outp
ut B
uffe
rI/O
Contro
l
Column Decoder
Latency & Burst Length
Programming Register
Addre
ss R
egis
ter
Row
Buffe
r
Re
fresh
Cou
nte
r
Row
Decoder
Col. B
uffe
r
LR
AS
LC
BR
LCKE
LRAS LCBR LWE LDQM
CLK CKE CS RAS CAS WE L(U)DQM
LWE
LDQM
DQi
CLK
ADD
LCAS LWCBR
8M x 4 / 4M x 8 / 2M x 16
8M x 4 / 4M x 8 / 2M x 16
Timing Register
Memory – p. 21
SDRAM: Control Signals
RAS CAS WE action1 1 1 NOP0 0 0 Load mode register0 1 1 Active (select row)1 0 1 Read (select column, start burst)1 0 0 Write (select column, start burst)1 1 0 Terminate Burst0 1 0 Precharge (deselect row)0 0 1 Auto Refresh
Mode register: selects 1/2/4/8-word bursts, CASlatency, burst on write
Memory – p. 22
SDRAM: Timing with 2-word bursts
L����������������������Clk
��HHHH��HHHHHHHHHHHHHHHHHHHHHHHHHHHH��HRAS
��HHHHHHHHHHHH��HHHH��HHHHHHHHHHHH��HCAS
��HHHHHHHHHHHH��HHHHHHHHHHHHHHHHHHHHHHHHHWE
��UUUU��UUUU��UUUU��UUUUUUUUUUUUUUUUUAddr
UUUUUUUU��UUUU��UUUU��UUUUUUUUUUUUUUUUUBA
ZZZZZZZZZZZZZZZZ����ZZZZZZZZ����ZZZZZDQ
Op R
B
C
B
C
B
W W R R
Load Active Write Read Refresh
Memory – p. 23
