Memory Management - web.cse.ohio-state.eduweb.cse.ohio-state.edu/~babic.1/I.2s.pdf3 g. babic...

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04-13-2020

Memory ManagementPresentation I

CSE 2431: Introduction to Operating Systems

Gojko Babić

Study: Chapter 9

g. babic Presentation I 2

1. Contiguous allocation2. Non-contiguous allocation

a. Paging– one level paging– two-level paging– inverted page table

b. Segmentation– pure segmentation– segmentation with paging

3. Virtual memory– with demand paging– with demand segmentation– with demand segmentation and paging

Memory Management Techniques

2


User programs go through several steps before being run.

Multi-Step Processing of a User Program

Kernel memory

Run‐time heap(created by malloc)

User stack(created at runtime)

Unused0

%rsp

Memory invisible to user code

0x400000

Read/write segment:.data, .bss

Read‐only segment:.init, .text, .rodata

Loaded from the executable file

Run-Time Memory Image in X86-64

4Presentation I

248-1

Program code(instructions)

Global variables &local variables withstatic attribute

Local variables;Stack increases and shrinks

Heap increases and shrinks

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Program must be brought into memory and placed within a process for it to be run.

The concept of a logical address space that is bound to a separate physical address space is central to proper memory management.

– Logical address – address generated by the CPU; also referred to as virtual address.

– Physical address – address seen by the memory unit.

The user program deals with logical addresses; it never sees the real physical addresses.

Address binding is a process of mapping a logical (virtual) address into physical (memory) address.

Logical vs. Physical Address Space


Address binding of instructions and data to memory addresses can happen at three different stages.

Compile time: If memory locations known a priori, absolute code generated; must recompile code if starting location changes.

Load time: Must generate relocatable code if memory location is not known at compile time.

Execution time: Binding delayed until run time. Needs hardware support for address mapping.

Logical and physical addresses are the same in compile-time and load-time address-binding schemes; logical (virtual) and physical addresses differ in execution-time address-binding scheme.

Address Binding

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7

Compile Time Address Binding

High level language code

Compiler

Executable code(in file; size 6,000bytes)

14,000--

15,000 branch 19,000 branch z---------

19,000 - z:---

19,999

loader

14,000

19,999

• Program has to be loaded in region 14,000-19,999• Memory image identical to executable file content • Logical address identical to physical address and

CPU generates addresses in range 14,000-19,999

--branch z----z:-

Starting address given in compilationcommand

When code is to run, O.S.activates loader

Main memory

branch 19,000 15,000

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Load Time Address Binding


Compiler


0--

1,000 branch 5,000 branch z---------

5,000 - z:---

5,999

loader

14,000

15,000

19,000

19,999

• Loader is loading code in free region 14,000-19,999and it adjusts required (flagged) instructions and data,e.g. by adding 14,000.

• Logical address identical to physical address, and CPU generates addresses in range 14,000-19,999

--branch z----z:-

Compilationstarts at

address 0 When code is to run, O.S. findsfree region of6,000B & actives relocatable loader

branch 19,000

Main memory

5

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Execution Time Address Binding


Compiler


0--

1,000 branch 5,000 branch z---------

5,000 - z:---

5,999

loader

14,000

15,000

19,000

19,999

• Loader is loading code in free region 14,000-19,999 and memory image identical to executable file content

• Mapping from logical address to physical address done during executing. CPU generates addresses in range 0-5,999

--branch z----z:-

Compilationstarts at

address 0 When code is to run, O.S. findsfree region of6,000B & actives loader

branch 5,000

Main memory


Memory Management Unit – MMU

In this simplest MMU scheme, the value in the relocation register is added to every address generated by a user process at the time it is sent to memory.

MMU is a hardware device that maps logical to physical address.

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Resident operating system, usually held in low memory with

interrupt vectors.

User processes then held in high memory.

Each process is allocated one (variable size) partition.

Load time and execution time address binding possible.

Protection in load time address binding:

– base & limit register scheme used to protect user

processes from each other, and from changing operating

system code and data.

Contiguous Allocation


MMU: Load Time Address Biding

The instructions to load base and limit registers privileged instructions.

process

process

process

process

Operatingsystem

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MMU: Execution Time Address Binding

– Limit register contains range of logical addresses – each logical address must be less than the limit register.

– Relocation register contains value of smallest physical address.– Memory protection achieved.– But applicable only when program loaded in contiguous locations.


Hole – block of available memory; holes of various size are scattered throughout memory.

When a process arrives, it is allocated memory from a hole large enough to accommodate it.

Operating system maintains information about:– allocated partitions – free partitions (hole)

OS

process 5

process 8

process 2

OS

process 5

process 2

OS

process 5

process 2

OS

process 5

process 9

process 2

process 9

process 10

Contiguous Allocation (Cont.)

OS

process 5

process 2

process 10

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How to satisfy a request from a list of free holes?

First-fit: Allocate the first hole that is big enough.

Best-fit: Allocate the smallest hole that is big enough; must

search entire list, unless ordered by size. Produces the

smallest leftover holes.

Worst-fit: Allocate the largest hole; must also search entire

list. Produces the largest leftover hole.

Contiguous Allocation (Cont.)


External Fragmentation – memory may end with many small holes, and although the total available memory space exists to satisfy a new process code, but it is not contiguous.

Internal Fragmentation – allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used. This reduces external fragmentation.

Reduce external fragmentation also by compaction:– Shuffle memory contents to place all free memory together

in one large block.– Compaction is possible only in execution time address

biding.– I/O problem: Do I/O only into OS buffers.

Fragmentation

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Physical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available.

Divide physical memory into fixed-sized blocks called frames(size is power of 2, between 512 bytes and 8192 bytes).

Divide logical memory (program address space) into blocks of same size called pages.

Keep track of all free frames.

To run a program of size n pages, need to find n free frames and load program.

Set up a page table to be used to translate logical to physical addresses.

Internal fragmentation in the frame loaded with the last page.

Paging


Page Table Set Up: Example 1

Program address space

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Before allocation After allocation

Page Table Set Up: Example 2


Address generated by CPU is divided into:

– Page number (p) – used as an index into a page table which contains base address of each page in physical memory.

– Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit.

Paging: Address Translation

2d = page size= frame size

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g. babic 21

Paging Address Translation: Example

2 2p d

3 2f d

0 1 0 1

0

1

2

3

0

1

2

3

4

5

6

7

1 1 0 0 1

logical address 5 maps into physical address 25

Logical address Physical address

=510 =2510

Presentation I

Presentation I 22

Page table is kept in main memory only.

– Page-table base register (PTBR) points to the page table.

– Page-table length register (PTLR) indicates size of the page

table and it is used for memory protection

– Both PTBR and PTLR are parts of MMU.

– In this scheme every data/instruction access requires two

memory accesses. One for accessing the page table by

MMU and one for the data/instruction (as usual).

– Thus a memory access time is doubled and this approach is obviously not appropriate.

Paging Implementation

g. babic

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Presentation I 23

Page table is kept in main memory and in MMU.

– the two memory access problem is thus being avoided

since MMU has its own copy of page table and it doesn’t

need to access main memory.

– but then we need a large number of registers in MMU to accommodate whole page table,

– and, what is more important, CPU switch time may be significant, since each time O.S. switches from process to process, whole page table (which can be very large) of next process to run has to be copied from memory to MMU.

Thus, neither this approach is appropriate for paging.

Instead, the approach with a special fast-lookup hardware called translation look-aside buffers (TLB) is used to implement paging

Paging Implementation (cont.)


MMU with TLB

– Note that page tables of all processes are kept in main memory.– Besides TLB, MMU also has PTBR and PTLR.– The locality of reference leads to MMU with TLB.

v

13


TLB contains only parts of a page table

TLB allows parallel (and thus fast) search of Page No. column

Address translation:

– If a page number is in TLB, get associated Frame No. out.

– Otherwise get Frame No. from page table in memory

If the required page entry is in a TLB, then a TLB hit happened.

If Page No. required is not found in a TLB, then a TLB miss happened and an entry from the page table is brought into TLB.

A hit rate or a hit ratio is the fraction of logical addresses for which appropriate entries is found in TLB.

TLB (Fully Associative Cache)

V Page No. Frame No.


Principle of locality of reference states that a program accesses a relatively small portion of its address space at any instant of time during its execution. There are two types of locality:

– temporal locality: if one memory location is referenced at some instance of time during a program execution, there is a high probability that the same memory location will be referenced again very soon.

– spatial locality: if one memory location is referenced at some instance of time during a program execution, there is a high probability that neighboring memory locations will be referenced very soon.

Locality of Reference (again)

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TLB (Associative Memory) Lookup = time units Memory access time = ma time units Assume hit ratio = – percentage of times that a page

number is found in the associative memory; Effective Access Time (eat) = (ma + ) + (2*ma + )(1 – ) Example:

– TLB access time = 0.5 nsec– Main memory access time ma = 50 nsec– TLB hit ratio = 0.98

– Effective Access Time (eat) = (50+.5)*.98+(2*50+.5)(1-.98) = 51.5 nsec

– Thus in this case, paging introduces 1.5 nsec overhead.

Effective Access Time

g. babic 28

Cache & Paging: Effective Access Time

Let TLB access time = 0.5nsec, main memory access time ma = 50nsec and TLB hit ratio = 0.98Effective Access Time (paging only, no cache) =

= (ma + )* + (2*ma + )(1–) = 51.5nsec Let cache access time c_a = 2nsec and cache hit ratio β=0.95

Effective access time (cache only, no paging) eat_c == cache_access_time+ (1− β)*miss_penalty= c_a + (1−β)*ma = 2 + (1–0.95)*50 = 4.5nsec

Cache improves memory access from 50nsec to 4.5nsec Effective (cache & paging) access time =

= (eat_c + )* + (ma + eat_c + )(1– )= (4.5 + 0.5)*0.98 + (50 + 4.5 + 0.5)(1– 0.98)= 6nsec

Cache+paging improve memory access from 50nsec to 6nsec.Presentation I

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Sharing of Code in Paging Environment

– One copy of reentrant code (e.g. text editor) shared among processes.

– Similarly, pages of data can be shared among several processes.


Paging allows benefits during process creation.

Copy-on-Write (COW) allows both parent and child processes

to initially share the same pages in memory, except the page

with the variable for return value of fork system call.

If either process modifies a shared page, only then is the

page copied.

COW allows more efficient process creation as only modified

pages are copied.

Copy on write is a common technique used by many Unix

operating systems.

Copy-on-Write

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Assuming single-level paging, i.e. the paging we have introduced so far, and 4Kbyte page size, then 32-bit logical address is divided into:

– a page offset d consisting of 12 bits, since 212 = 4K

– a page number p consisting of 20 bits.

But what if a page table is larger than one frame? And that is normally a case.

Then the page table has to be paged, i.e. divided into pages, and each page of page table will be loaded into its allocated frame; but those frames aren’t necessarily contiguous.

Then the page table has to have its own page table, called outer page table.

Two-Level Paging


Assuming 4 bytes per page entry (and as in the example on the previous slide), then one page would accommodate 1024 page entries (4Bx1024=4KB page).

Then the page number p is further divided into:

– a page offset p2 of 10-bit, since 210 = 1024 entries per page

– a 10-bit page table page number p1.

page number page offset

p1 p2 d

10 10 12

Two-Level Paging (cont.)

– p1 is used as an index into the outer page table, and p2 is

the displacement within the page of the outer page table.

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Address Translation in Two-Level Paging

Physicalmemory

This is a page table entryaccessed directly in one level paging.


– There is only one table, with one entry for each frame of memory,thus the table size equals to number of frames,

– Each entry consists of the page number of page stored in that frame, with information about the process that owns that page.

Inverted Page Table

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Memory-management scheme that supports user view of memory.

A program is a collection of segments. A segment is a logical unit such as:

– main program,

– procedures,

– functions,

– objects,

– local variables, global variables,

– stack,

– symbol table,

– arrays.

Segmentation


3functionA

1main

2 functionB

4sqrt

logical space

1

4

2

3

physical memory space

Logical View of Segmentation

– Since segments vary in length, memory allocation is as in the

contiguous allocation.

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Example of Segmentation

Any process has its segment table with one entry for each segment

Logical address consists of a two tuple:<segment-number, offset>


Segmentation Address Mapping

• Mapping using segment table

Improved protection: With each entry in segment table associate bits that define read/write/execute access privileges.

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Each segmentation table entry has:

– base – contains the starting physical address where the segment reside in memory.

– limit – specifies the length of the segment.

Segment-table base register (STBR) points to the segment table’s location in memory.

Segment-table length register (STLR) indicates number of segments used by a program;

Segment number s is legal if s < STLR.

By the similar arguments as in paging, MMU here has to use TLB

Segmentation Architecture


MULTICS Address Translation

– This is an example of segmentation with single-level paging

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Intel IA-32 Address Translation

– Identical address mapping mechanism used in from Intel 80386 processor of 1980’s to today’s Intel processors.

– This is an example of segmentation with two-level paging.

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Memory Management - web.cse.ohio-state.eduweb.cse.ohio-state.edu/~babic.1/I.2s.pdf3 g. babic...

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