MEMORY-MAPPED I/O

INTROInput/ output devices are the means through

which the MPU communicates with “the outside world”.

It accepts binary data as input from input devices(keyboard, A/D convertors)

Sends data to output devices(LEDs or Printer)

FOR THIS WE HAVE TWO METHODS:1) PERIPHERAL MAPPED2) MEMORY MAPPED

PERIPHERAL MAPPED

MPU uses 8-address lines to identify I/O device.

This is an 8-bit numbering system for I/O used in conjugation with input/output instructions.

(CALLED AS I/O SPACE)

THE entire range from 00 – FF is known as an i/o map and individual addresses are known as I/O port number.

In bus architecture, these devices cannot be connected directly to the data bus or address bus, all connections should made through tri-state interfacing devices so they will be enabled and connected to the buses

only when MPU wants them to communicate.

CAN IDENTIFY 256 I/O

DEVICES

the input and output devices are assigned and identified by 16-address lines.

MEMORY-MAPPED

memory-related instructions(such as LDA, STA, etc.) and memory control signals(MEMR’ and MEMW’) are used.

I/O is connected as if it is a memory register.

CAN IDENTIFY 64K I/O DEVICES

• The microprocessor communicates with an I/O device as if it were one of the memory location

MEMORY-MAPPED I/O

The microprocessor communicates with an i/o device as if it were one of the memory locations.

In many ways, it is similar to peripheral I/O technique.

To understand similarities, we’ll take an example:

HERE IF AN OUTPUT DEVICE IS CONNECTED AT THIS ADDRESS, THE ACCUMULATOR CONTENTS, WILL BE TRANSFERRED TO THE OUTPUT DEVICE. THIS IS CALLED MEMORY-MAPPED I/O TECHNNIQUE

MEMORY ADDRESS

MACHINE CODE MNEMONICS COMMENTS

2050 32 STA 8000H STORE CONTENTS OF ACCUMULATOR IN MEMORY LOCATION 8000H

2051 00

2052 80

EXAMPLE:

Memory related instructions have 16-bit addresses.

P requires four machine cycles(13 t-states) to execute the instruction STA

Machine cycle M4 for STA is similar to M3 for the out instruction.

EXECUTION OF MEMORY-RELATED DATA TRANSFER INSTRUCTIONS

TIMING EXECUTION OF THE INSTRUCTION STA 8000H

EXPLANATION:

For STA

To execute the instruction STA 8000H in the fourth machine

cycle(M4), the p places memory address 8000H on the entire

address bus(A15 – A0). The accumulator contents are sent

on the data bus, followed by the control signal memory write

MEMW’.The entire bus is to be decoded.

In executing the OUT instruction, the 8-bit device address is repeated on the low-order

address bus(A0 – A7) as well as on the high-order bus, and the IOW’

control signal is usedEither high or low order is to be

decoded.

For OUT

ILLUSTRATION: SAFETY CONTROL SYSTEM USING MEMORY-MAPPED I/O INTERFACING

• Various process control devices are connected to the data bus through the latch 74LS373 and the solid state relays.

• If output bit of latch is high: corresponding relay is activated and process turns on.

• 74LS373 is a latch followed by a tri-state buffer.• Latch and buffer are controlled independently by the latch

enable(LE) and output enable(OE)’.• When LE high: data enter the latch.• When LE low: data is latched.• Latched data is available on the output lines of the 74LS373 if the

buffer is enabled by OE’. If OE’ high, o/p lines go into high impedance state.

OUTPUT PORT AND ITS ADDRESS

OE’ is connected to ground, thus latched data keep the relays on/off according to the bit pattern. The LE is connected to the device select pulse, which is asserted when the o/p O0 of the decoder and the control signal MEMW’ go low. Thus, to assert the i/o select pulse, the output port address should be FFF8H.

A15 – A8 =‘1’ To 8-INPUT NAND GATE to enable E2’ A7 – A4 =‘1’ To 8-INPUT NAND GATE to enable E1’ A3 =‘1’ to enable E3

A2 – A0 =‘0’ decoder input-------- FFF8H

Cont……

INPUT PORT AND ITS ADDRESS

The DIP switches are interfaced with the 8085 using the tri-state buffer 74LS244. the switches are tied high. They are turned on by grounding. The switch position can be read by enabling the signal OE’, which is asserted when the o/p O1 of the decoder and the control signal MEMR’ go low. Thus, to read the i/p port, the port address should be FFF9H.A15 – A8 =‘1’ To 8-INPUT NAND GATE to enable E2’A7 – A4 =‘1’ To 8-INPUT NAND GATE to enable E1’A3 =‘1’ to enable E3

A2 – A1 =‘0’ and A0 =‘1’ decoder input-------- FFF9H

READ LDA FFF9H READ THE SWITCHES

CMA COMPLEMENT SWITCH READING, CONVERT ON-SWITCH(LOGIC 0) INTO LOGIC 1 TO TURN ON APPLIANCES

STA FFF8H SEND SWITCH POSITION TO O/P PORT AND TUR ON/OFF APPLIANCES

JMP READ GO BACK AND READ AGAIN

INSTRUCTIONS

To control the process according to switch position, the microprocessor should read the bit pattern at the input port and send that bit pattern to the output port.

The 1ST Instruction reads the bit pattern 1011 0111(B7H) at the i/p port FFF9H and places the reading in the accumulator; this bit pattern represents the on-position of switches S6 and S3.

The 2nd instruction complements the reading: this instruction is necessary because the on-position has logic 0. and to turn on solid state relays logic 1 is necessary.

The 3rd instruction sends the complemented accumulator contents (0100 1000=48H) to the output port FFF8H.

The 74LS373 latches the data byte 0100 1000 and turns back to the beginning and repeats the loop continuously. Thus, it monitors the switches continuously.

EXPLANATION

CHARACTERSTICS MEMORY-MAPPED I/O PERIPHERAL I/O

1. Device address 16-bit 8-bit

2. Control signal MEMR’/ MEMW’ IOR’/ IOW’

3. Instruction available STA, LDA, LDAX, STAX, etc. IN and OUT

4. Data transfer b/w any register and I/O b/w I/O and accumulator

5. Maximum number of I/Os possible

Memory map (64K) is shared b/w I/Os and system memory

I/O map is independent of the memory map; 256 input devices and 56 output devices can be connected

6. Execution speed 13 T-states or 7 T-states 10 T-states

7. Hardware requirements More hardware required to decode 16-bit address

Less hardware required to decode 8-bit address

COMPARISION

Check the wiring and the pin connectionsNow, generate a constant and identifiable

signal and check, we need to generate a constant and identifiable signal and check various points in relation to that signal

We can generate such a signal by asking the processor to execute a continuous loop, called a DIAGNOSTIC ROUTINE.

TESTING AND TROUBLESHOOTING I/O INTERFACING CIRCUITS

INSTRUCTION BYTES T-STATES MACHINE CYCLES M1 M2 M3

START: MVI A,78H 2 7(4,3) OPCODE FETCH

MEMORY READ

OUT F5H 3 10(4,3,3) OPCODE FETCH

MEMORY READ

I/O WRITE

JMP START 3 10(4,3,3) OPCODE FETCH

MEMORY READ

MEMORY READ

DIAGNOSTIC ROUTINE AND MACHINE CYCLEs

T-STATES: 27MACHINE CYCLES: 8To execute: the microprocessor asserts the RD’ signal seven times(opcode fetch is also a read operation) and WR’ signal once.

The IOW must be low and the IOSEL must be high.

When 8085 asserts the WR’ signal, the port address F5H must be on the address bus A7 – A0, the output O5 of the

decoder must be low

If the circuit is not properly functioning, we check various signals in reference to the WR’ signal as suggested below:

Now, if we check the data bus in relation to the WR’ signal, one line at a time, we must read the data byte 78H.

NECESSARY CONDITIONS:

If decoder not enabled, check the address lines A4 – A7; all of them must be high and address line A3 must be low.

If one of the output is low, it suggests that the input address lines are improperly connected.

May be the port is enabled but the seven segment display is wrong. The problem must be with data lines. Try different codes to display other digits.

If O5 of the decoder is high, check all the output lines O0 to O7 of the decoder. If all high: decoder not enabled.

If IOW’ is high, check the input to the or gate. Both should be low.

If IOSEL is low, check IOW’

and O5 of the decoder.

IF CIRCUIT IS NOT FUNCTIONING PROPERLY, CHECK VARIOUS SIGNALS IN REFERENCE TO WR’ SIGNAL