Memory Organization (Memory Hierarchy) Memory hierarchy in a computer system : Fig. 12-1

Main Memory : memory unit that communicates directly with the CPU (RAM) Auxiliary Memory : device that provide backup storage (Disk Drives) Cache Memory : special very-high-speed memory to increase the processing

speed by making current programs and data available to the CPU at a very fast rate .

» It is used to compensate the speed difference between main memory access time and processor logic.

» While the I/O processor manages data transfer between auxiliary memory and main memory, the cache memory is concerned with the data transfer between main memory and CPU.

Magnetictapes

Magneticdisks

I/O processor

CPU

Mainmemory

Cachememory

Auxiliary memory

Multiprogramming : Enables the CPU to process a number of independent program concurrently.

Multiprogramming refers to the existence of two or more programs in different parts of the memory hierarchy at the same time.

It is possible to keep all parts of CPU busy by working with several programs in sequence.

In multiprogramming environment when one program is waiting for input or output transfer there is another program ready to utilize the CPU.

12-2 Main Memory Bootstrap Loader

A program whose function is to start the computer software operating when power is turned on

RAM and ROM Chips Typical RAM chip : Fig. 12-2

» 128 X 8 RAM : 27 = 128 (7 bit address lines) Typical ROM chip : Fig. 12-3

» 512 X 8 ROM : 29 = 512 (9 bit address lines)

×

1 2 8 × 8R A M

C S 1

A D 7

W R

R D

C S 2

C h i p s e l e c t 1

C h i p s e l e c t 2

R e a d

W r i t e

7 b i t a d d r e s s

8 b i t d a t a b u s

( a ) B l o c k d i a g r a m

C S 1 W RR DC S 2 M e m o r y f u n c t i o n S t a t e o f d a t a b u s

0

×

×

×

00 0

0 0

01 1

1

1

1

1

×

0

×

×

0

1

1

I n h i b i t

I n h i b i t

I n h i b i t

W r i t e

R e a d

I n h i b i t

H i g h - i m p e d a n c e

H i g h - i m p e d a n c e

H i g h - i m p e d a n c e

I n p u t d a t a t o R A M

O u t p u t d a t a f r o m R A M

H i g h - i m p e d a n c e

( b ) F u n c t i o n t a b l e

5 1 2 × 8R O M

C S 1

A D 9

C S 2

C h i p s e l e c t 1

C h i p s e l e c t 2

9 b i t a d d r e s s

8 b i t d a t a b u s

Power- ON

FFFF:0000(Reset Point)

POST

System Init.

INT 19

Load Bootstrap Record(Track 0, Sector 0)

Load Operating System(IO.SYS, MSDOS.SYS, COMMAND.COM)

Bootstrap LoaderBootstrap ROMBoot ROM

Memory Address Map Memory Configuration : 512 bytes RAM + 512 bytes ROM

» 1 x 512 byte ROM + 4 x 128 bytes RAM Memory Address Map : it is a pictorial representation of assigned address space

for each chip in the system.» Address line 10 9 8 7 6 5 4 3 2 1

RAM 1 0 0 0 x x x x x x x : 0000 - 007F RAM 1 0 0 1 x x x x x x x : 0080 - 00FF RAM 1 0 1 0 x x x x x x x : 0100 - 017F RAM 1 0 1 1 x x x x x x x : 0180 - 01FF ROM 1 x x x x x x x x x : 0200 - 03FF The small x’s under the address bus lines, designate those lines that must be connected to the

address input in each chip. RAM chips have 128 bytes and needs 7 address lines. ROM chip have 512 bytes and needs 9 address lines

Memory Connection to CPU : 2 x 4 Decoder : RAM select (CS1)

» Address line 10 RAM select : CS2 ROM select : CS2 의 Invert

RD : ROM CS1 OE(Output Enable)

1 2 8 × 8R A M 1

C S 1

A D 7

W R

R D

C S 2

1 2 8 × 8R A M 2

C S 1

A D 7

W R

R D

C S 2

1 2 8 × 8R A M 4

C S 1

A D 7

W R

R D

C S 2

1 2 8 × 8R A M 3

C S 1

A D 7

W R

R D

C S 2

1 2 8 × 8R O M

C S 1

C S 2

A D 9

D a t a

D a t a

D a t a

D a t a

D a t a

C P U

W RR D1 6 - 1 1 1 0 9 8 7 - 1

A d d r e s s b u s

D a t a b u s

D e c o d e r

3 2 1 0

1 - 7

8

9

12-3 Auxiliary Memory Magnetic Disk : FDD, HDD Magnetic Tape : Backup or Program Optical Disk : CDR, ODD, DVD

12-4 Associative Memory Content Addressable Memory (CAM)

A memory unit accessed by content Block Diagram : Fig. 12-6

texttexttexttext

Secto

r

R e a d / W r i t eh e a d

T r a c k s

A Register 101 111100K Register 111 000000

Word 1 100 111100 M = 0Word 2 101 000011 M = 1

A r g u m e n t r e g i s t e r ( A )

K e y r e g i s t e r ( K )

A s s o c i a t i v e m e m o r ya r r a y a n d l o g i c

m w o r d s n b i t s p e r w o r d

M

M a t c hr e g i s t e r

I n p u t

W r i t e

R e a d

O u t p u t

이름 주소

Argument

Key (Mask)

Match Logic

Memory 내용

M = 1 일때출력

m word x n cells per word : Fig. 12-7

Match Logic One cell of associative memory : Fig. 12-8

» Input = 1 or 0 Write F/F» A 와 K 에의해 Match Logic 에서 M=1 이면 (M을 READ에 직접 연결 가능함)» Read 신호에 따라 F/F에서 데이터를 읽는다

A 1

C 1 1

A nA j

K 1 K nK j

C 1 j C 1 n

C i 1 C i j C i n

C m 1 C m j C m n

M 1

M m

M i

B i t 1 B i t nB i t j

W o r d 1

W o r d m

W o r d i

R S M a t c hl o g i c

I n p u t

R e a d

W r i t e

O u t p u t

T o M i

K jA i

F i j

Match Logic : Fig. 12-9» Aj = Argument, Fij = Cell ij bit» j 1 bit match

xj = Aj Fij (1 AND 1)+ Aj’ Fij’ (0 AND 0) » 1 - n , n bits match Mi = x1x2…..xn» Key bit Kj : xj + Kj’

Kj = 0 : Aj 와 Fij 는 no comparison ( Kj : xj + 1 = 1 ) Kj = 1 : Aj 와 Fij 는 comparison ( Kj : xj + 0 = xj )

» Match Logic for word I : Mi = (x1 + K1’) (x2 + K2’)…. (xn + Kn’)

= (xj + Kj’) = (Aj Fij + Aj’ Fij’ + Kj’)

n

j 1

n

j 1

F'i1 Fi1

A1K1

F'i2 Fi2

A2K2

F'in Fin

AnKn

Mi

12-5 Cache Memory Locality of Reference

the references to memory tend to be confined within a few localized areas in memory. Ex. Program loops or subroutine. It states that over a short interval of time the addresses generated by a typical program refers to a few localized areas of memory repeatedly.

Cache Memory : a fast small memory keeping the most frequently accessed instructions and data in the fast cache

memory Cache

cache size : 256 K byte (512 K byte) mapping method : 1) associative, 2) direct, 3) set-associative replace algorithm : 1) LRU, 2) LFU, 3) FIFO write policy : 1) write-through, 2) write-back

Hit Ratio the ratio of the number of hits divided by the total CPU references (hits + misses)

to memory» hit : the CPU finds the word in the cache » miss : the word is not found in cache (CPU must read main memory)

An example where cache memory access time = 100 ns, main memory access time = 1000 ns, hit ratio = 0.9 produces an average access time of 200 ns.

» 1 * miss : 1 x 1000 ns without the cache memory the time is 1000ns» 9 * hit : 9 x 100 ns10 Memory

1900 ns / 10 = 190 ns

Mapping The transformation of data from main memory to cache memory

» 1) Associative mapping» 2) Direct mapping» 3) Set-associative mapping

Example of cache memory : main memory : 32 K x 12 bit word (15 bit address lines)cache memory : 512 x 12 bit word

» CPU sends a 15-bit address to cache Hit : CPU accepts the 12-bit data from cache Miss : CPU reads the data from main memory (then data is written to cache)

M a i n m e m o r y3 2 K × 1 2

C P UC a c h e m e m o r y

5 1 2 × 1 2

Associative mapping : associative memory stores both address and data of the memory word.

A r g u m e n t r e g i s t e r

0 1 0 0 0

2 2 3 4 5

0 2 7 7 7

3 4 5 0

1 2 3 4

6 7 1 0

A d d r e s s D a t a

C P U a d d r e s s ( 1 5 b i t s )

If the address is found, the corresponding12-bit data is read and send to the CPU. IFNO MATCH OCCURS, then main memoryis accessed for the word. The address pair isthen transferred to the associative memory.If the cache is full, an address-data pairmust be displaced to make room for a pairthat is needed and not presently is in cache.

This is done with replacement algorithm.

Direct mapping cache organization : Fig. 12-13For address 020001) Index 000 cache , tag 00 and data 12202) Suppose CPU wants to access the word at address 02000.3) The index address is 000 so it is used to Access cache. Two tags then compared.4)Cache tag 00 but address tag 02, not match5)Main m/m accessed & data word 5670 is Transferred to CPU.6)Now 000 is replaced with tag 02 & data 5670.

3 2 K × 1 2

M a i n m e m o r y

A d d r e s s = 1 5 b i t sD a t a = 1 2 b i t s

T a g I n d e x

6 b i t s 9 b i t s

H e xA d d r e s s

0 0 0 0 0

3 F 1 F F

5 1 2 × 1 2C a c h e m e m o r y

A d d r e s s = 9 b i t sD a t a = 1 2 b i t s

0 0 0

1 F F

O c t a la d d r e s s

1 2 2 0

2 3 4 0

3 4 5 0

4 5 6 0

5 6 7 0

6 7 1 0

M e m o r y d a t aM e m o r y

a d d r e s s

0 0 0 0 0 0

0 2 7 7 7

0 2 0 0 0

0 1 7 7 7

0 1 0 0 0

0 0 7 7 7

0 0 1 2 2 0

0 2 6 7 1 0

T a g D a t aIn d e x

a d d r e s s

0 0 0

7 7 7

( a ) M a i n m e m o r y

( b ) C a c h e m e m o r y

Tag (6 bit)00 - 63

Index (9 bit)000 - 511

Direct mapping : Fig. 12-12Cache memory

Tag field (n - k)

Index field (k)»2k words cache memory and 2n words

main memoryTag = 6 bit (15 - 9), Index = 9 bit

Direct mapping cache with block size of 8 words : Fig. 12-14» 64 block x 8 word = 512 cache words size

0 0 0

0 0 7

0 1 0

0 1 7

0 1

0 1

7 7 0

7 7 7

0 2

0 2

3 4 5 0

6 5 7 8

6 7 1 0

I n d e x T a g D a t a

B lo c k 0

B lo c k 1

B lo c k 6 3

T a g B l o c k W o r d

6 36

I n d e x

0 1 3 4 5 0 0 2 5 6 7 0

0 2 6 7 1 0 0 0 2 3 4 0

0 0 0

7 7 7

I n d e x T a g D a t a T a g D a t a

Set-associative mapping : Disadvantage of direct mapping: two words with the same index in their address but with different tag values can not reside in cache memory at the same time.

Each data word is stored together with its tag and the number of tag-data item in one word of cache is said to form a set.

Replacement Algorithm : cache miss or full 1) LRU (Least Recently Used) : 2) LFU (Least Frequently Used) 3) FIFO (First-In First-Out) :

Writing to Cache: Write Through: Advantage that main m/m always contain same data as cache.Write back: only the cache location is updated during a Write operation. Cache Initialization

Cache is initialized :» 1) when power is applied to the computer» 2) when main memory is loaded with a complete set of programs from auxiliary memory

valid bit» indicate whether or not the word contains valid data

Cache READ