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Memory Packaging Technology & ModelingRandy Wolff Micron Technology DesignCon IBIS Summit 2014 Santa...

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©2014 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron’s production data sheet specifications. Information, products, and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Dates are estimates only. Drawings are not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. ©2014 Micron Technology, Inc. | 1 Randy Wolff Micron Technology DesignCon IBIS Summit 2014 Santa Clara, CA Memory Packaging Technology & Modeling January 31, 2014
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Page 1: Memory Packaging Technology & ModelingRandy Wolff Micron Technology DesignCon IBIS Summit 2014 Santa Clara, CA Memory Packaging Technology & Modeling January 31, 2014 ©2014 Micron

©2014 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron’s production data sheet specifications. Information, products, and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Dates are estimates only. Drawings are not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.

©2014 Micron Technology, Inc. | 1

Randy Wolff

Micron Technology

DesignCon IBIS Summit 2014

Santa Clara, CA

Memory Packaging Technology & Modeling

January 31, 2014

Page 2: Memory Packaging Technology & ModelingRandy Wolff Micron Technology DesignCon IBIS Summit 2014 Santa Clara, CA Memory Packaging Technology & Modeling January 31, 2014 ©2014 Micron

©2014 Micron Technology, Inc. | 2

Outline

January 31, 2014

• Packaging Tradeoffs

• DRAM packaging

• NAND/MCP/NOR packaging

• Package Modeling

Page 3: Memory Packaging Technology & ModelingRandy Wolff Micron Technology DesignCon IBIS Summit 2014 Santa Clara, CA Memory Packaging Technology & Modeling January 31, 2014 ©2014 Micron

©2014 Micron Technology, Inc. | 3

Memory Packaging Tradeoffs

January 31, 2014

Cost Custom

Performance Density

CiP SiP 2D

DCA

mNAND HMC

TSOP BOC

LOC

F2F

Up to 16Die in a Single Package

System in Package

PoPt

Integrated Shields

3D

TSV DRAM

Page 4: Memory Packaging Technology & ModelingRandy Wolff Micron Technology DesignCon IBIS Summit 2014 Santa Clara, CA Memory Packaging Technology & Modeling January 31, 2014 ©2014 Micron

©2014 Micron Technology, Inc. | 4

DRAM Packaging Terminology

• Number of identical die in package:

▶ 1=SDP, 2=DDP, 3=3DP, 4=QDP

• FBGA BOC – Board On Chip

▶ For SDPs

• FBGA COB – Chip on Board

▶ For DDP+

• Stacking Technologies:

▶ RDL – Re-Distribution Layer, routes edge to center of die

▶ 2-4 COB – Bondwire (BW) to each die edge, RDL to center

▶ F2F DDP – 1 BW, 1 RDL, 2 die connected (Face-to-Face)

▶ DCA – Direct Chip Attach – no BWs

▶ TSV – Through Silicon Via – in Hybrid Memory Cube (HMC)

January 31, 2014

2-4 COB

F2F DDP

DDP-QDP TSV (DCA)

BOC

Page 5: Memory Packaging Technology & ModelingRandy Wolff Micron Technology DesignCon IBIS Summit 2014 Santa Clara, CA Memory Packaging Technology & Modeling January 31, 2014 ©2014 Micron

©2014 Micron Technology, Inc. | 5

RDL in Stacked DRAM

• RDL metal is added on top of a

finished die (1 or 2 layers)

▶ Added Resistance

▶ Lossy T-line like characteristics

• 2COB – lower speeds

▶ RDL routes from edge to center

▶ Long RDL for each die (long stubs)

• F2F DDP – faster speeds

▶ Long RDL on bottom die

▶ Short RDL on flipped top die (short stubs)

January 31, 2014

2COB

F2F DDP

RDL

Page 6: Memory Packaging Technology & ModelingRandy Wolff Micron Technology DesignCon IBIS Summit 2014 Santa Clara, CA Memory Packaging Technology & Modeling January 31, 2014 ©2014 Micron

©2014 Micron Technology, Inc. | 6

NAND/MCP/NOR Packaging Terminology

• Number of die in package:

▶ 8=8DP, 16=16DP

• MCP – Multi Chip Package (combos of LPDRAM, NAND, NOR)

• eMMC – Embedded NAND with MultiMediaCard controller

• uSD – Micro SD card format

• PoP – Package on Package

• PoPt – PoP, top package of PoP stack

• WLCSP – Wafer Level Chip Scale Package

• uCuS – Microcontroller under stack

January 31, 2014

8DP + uCtrl, eMMC

BGA 1-8DP

8 die uSD

WLCSP

PoP

8 Die uCuS

Page 7: Memory Packaging Technology & ModelingRandy Wolff Micron Technology DesignCon IBIS Summit 2014 Santa Clara, CA Memory Packaging Technology & Modeling January 31, 2014 ©2014 Micron

©2014 Micron Technology, Inc. | 7

Package Modeling - Current

• SDP modeling formats

▶ [Pin] RLC, [Package Model] – coupled matrices

▶ Full package, coupled SPICE for DDR4

▶ S-param , .s4p, .s12p, .sxxp for HMC SerDes packages

• Stacked package modeling formats

▶ EBD – lossless, uncoupled, but models forks/splits

▶ SPICE – lossy, uncoupled/coupled

January 31, 2014

Page 8: Memory Packaging Technology & ModelingRandy Wolff Micron Technology DesignCon IBIS Summit 2014 Santa Clara, CA Memory Packaging Technology & Modeling January 31, 2014 ©2014 Micron

©2014 Micron Technology, Inc. | 8

Package Modeling - Future

• SDP modeling formats

▶ Increased use of SPICE (IBIS-ISS) for packages

▶ Inclusion of on-die PDN models – SPICE (IBIS-ISS) format

▶ Increased use of S-param format for SerDes, high speed

packages

▶ Mixed formats, IBIS-ISS + S-param + [Pin]

▶ Pre-layout models: full byte lane (coupled) and single data

bit (uncoupled) S-params

• Stacked package modeling formats

▶ EMD – coupled/uncoupled models in IBIS-ISS format

• Identical or mixed die types

January 31, 2014

Page 9: Memory Packaging Technology & ModelingRandy Wolff Micron Technology DesignCon IBIS Summit 2014 Santa Clara, CA Memory Packaging Technology & Modeling January 31, 2014 ©2014 Micron

June 3, 2014


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