Memristive crossbar arrays for convolutional neural network

Byung Joon Choi1 and Kyeong-Sik Min2

1. The Department of Materials Science and Engineering, Seoul National University of Science and

Technology, Seoul 01811, Republic of Korea 2. School of Electrical Engineering, Kookmin University, Seoul 02707, Republic of Korea

The deep learning techniques reach to human-level ability in some applications of image and

speech recognition recently. One big reason why deep-learning techniques are very important in future

is Internet of Things (IoT) which produces huge amounts of big data sensed from humans, machines,

environment, etc. Considering the tradeoff between the performance and cost, many IoT systems do not

require high performance in their functions. Thus, we propose a new energy-efficient memristor-

CMOS hybrid system for in-memory learning/execution in low-cost IoT systems.

Convolutional Neural Network (CNN) is the most popular among many deep-learning

algorithms. The convolution operation is composed of iterative multiplications of analog matrices. The

matrix multiplication which is performed by Von Neumann architecture consumes very large amount of

energy and causes the memory bottleneck in interfacing between the computing and memory units.

Thus, for avoiding the complicated matrix multiplication memory bottleneck, we try to replace this

high-cost convolution of Von Neumann architecture with low-cost memristor crossbar array operation

with the event-driven parallel architecture.

We are developing Memristive Convolutional Neural Network (MCNN) in this work,

summarized as follows. (1) Material/process/device technologies of neurotransmitter-mimicking

memristor array (Implementation of selector-free/self-rectifying and neurotransmitter-mimicking

memristor devices by stacking of multiple layers and alloying diffusive metal into the memristive

layer, atomic layer deposition technology as key enabler for multi-layer stacking and synapse-gap

engineering for memristor array) (2) Basic building blocks, hardware/software platform, and algorithm

of MCNN (Scalable and expandable memristor array architecture of MCNN kernels and synapses with

memristor-array tiles, CMOS circuits for sub-sampling, read, write, and threshold functions of MCNN,

Hardware/software platform for MCNN training and executing, MCNN learning algorithm and defect-

repair scheme for memristive kernels and synapses considering defective memristors) (3) MCNN

Applications (MNIST hand-written digits with 28x28 pixels, Event-driven operation of MNIST-DVS

(Dynamic Vision Sensor) and Poker-DVS images, ImageNet testing vectors)

At the present phase, we introduce the fabrication of low-power/self-rectifying memristors with

the multi-layer architecture of active-switching and tunnel-barrier layers to enable the low-power and

selector-free memritive crossbar arrays.